JP2000150566A - Connecting structure and its connection method - Google Patents
Connecting structure and its connection methodInfo
- Publication number
- JP2000150566A JP2000150566A JP10332042A JP33204298A JP2000150566A JP 2000150566 A JP2000150566 A JP 2000150566A JP 10332042 A JP10332042 A JP 10332042A JP 33204298 A JP33204298 A JP 33204298A JP 2000150566 A JP2000150566 A JP 2000150566A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- circuit board
- bump
- electrode
- connection structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、パッド上にバンプ
が形成された半導体チップを回路基板電極上にフリップ
チップ方式で接続し、半導体チップ・回路基板間を樹脂
で封止した接続構造および、この接続構造を得るための
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection structure in which a semiconductor chip having a bump formed on a pad is connected to a circuit board electrode by a flip chip method, and the semiconductor chip and the circuit board are sealed with resin. It relates to a method for obtaining this connection structure.
【０００２】[0002]
【従来の技術】従来、ＬＳＩなどの半導体集積回路の実
装技術の一つとして、フリップチップ方式が採用されて
いる。この実装方式では、半導体チップのパッド上に電
極（以下、バンプという）を形成するとともに、回路基
板（実装基板）にも電極（以下、回路基板電極というこ
とがある）を形成しておき、半導体チップのバンプと回
路基板電極との位置合わせを行って、半導体チップを回
路基板に接続するものである。2. Description of the Related Art Conventionally, a flip chip method has been adopted as one of the mounting techniques for a semiconductor integrated circuit such as an LSI. In this mounting method, an electrode (hereinafter, referred to as a bump) is formed on a pad of a semiconductor chip, and an electrode (hereinafter, also referred to as a circuit board electrode) is formed on a circuit board (mounting board). The semiconductor chip is connected to the circuit board by aligning the bumps of the chip with the circuit board electrodes.
【０００３】ところで、特開平９−２２３７２１号公報
には、半導体チップを回路基板に安定してフリップチッ
プ接続することができる構造が提案されている。この接
続構造では図８に示すように、半導体チップ５０に形成
されたパッド６７上に、先端に錐状の尖鋭部５５を有す
るバンプ５３が設けられ、尖鋭部５５を回路基板５１の
電極５８に突き刺す形で接続されている。Japanese Patent Application Laid-Open No. 9-223721 proposes a structure in which a semiconductor chip can be stably flip-chip connected to a circuit board. In this connection structure, as shown in FIG. 8, a bump 53 having a conical sharp part 55 at the tip is provided on a pad 67 formed on the semiconductor chip 50, and the sharp part 55 is connected to an electrode 58 of the circuit board 51. They are connected in a piercing manner.
【０００４】上記公報記載の接続構造には、従来のフリ
ップチップ接続技術、すなわちメッキ法あるいはワイヤ
ーバンピング法で半導体チップにバンプを形成し、異方
性導電部材で接続するものに比べて、以下の利点があ
る。 （１）半導体チップのバンプ先端部を尖鋭化し、回路基
板電極に突き刺す形態で接続することで、接続面積が大
きくなるので、バンプの大きさに多少のバラツキがあっ
ても確実な電気的接続が得られる。 （２）バンプ先端部を回路基板電極に機械的に突き刺す
ので、従来方法と違って、異方性導電部材（ＡＣＦ，Ａ
ＣＰなど）で接続する必要がない。[0004] The connection structure described in the above publication has the following advantages over the conventional flip-chip connection technology, ie, a method in which bumps are formed on a semiconductor chip by a plating method or a wire bumping method and connected by an anisotropic conductive member. There are advantages. (1) The connection area is increased by sharpening the tip of the bump of the semiconductor chip and piercing the circuit board electrode, so that a reliable electrical connection can be obtained even if the size of the bump is slightly varied. can get. (2) Since the tip of the bump is mechanically pierced into the circuit board electrode, unlike the conventional method, the anisotropic conductive member (ACF, A
CP, etc.).
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記公
報の実装技術では、（ａ）バンプ先端部を尖鋭化する工
程が必要である、（ｂ）バンプ間のピッチが微細になる
と、尖鋭部を形成するための治具の作製が困難になって
くる、（ｃ）半導体チップのバンプパターンに対応し
て、バンプ先端部を尖鋭化するための治具を何種類も用
意する必要がある、という不具合があった。However, the mounting technique disclosed in the above publication requires (a) a step of sharpening the tip of the bump, and (b) formation of a sharp part when the pitch between the bumps becomes fine. (C) It is necessary to prepare several types of jigs for sharpening the tip of the bump corresponding to the bump pattern of the semiconductor chip. was there.
【０００６】したがって本発明の目的は、バンプの大き
さや高さに多少のバラツキがあっても確実な電気的接続
が得られる、フリップチップ方式による半導体チップの
接続構造を、簡便な工程で安価に提供することにある。
本発明の別の目的は、この接続構造を得るのに好適な方
法を提供することである。Accordingly, an object of the present invention is to provide a flip-chip type semiconductor chip connection structure which can provide reliable electrical connection even if there is some variation in the size and height of bumps, by a simple process and at low cost. To provide.
Another object of the present invention is to provide a method suitable for obtaining this connection structure.
【０００７】[0007]
【課題を解決するための手段】請求項１に記載の半導体
チップの接続構造は、パッド上にバンプが形成された半
導体チップを回路基板電極上にフリップチップ方式で接
続し、半導体チップ・回路基板間を樹脂で封止した接続
構造において、バンプ先端部が回路基板電極に食い込む
形で接続されていることを特徴とする。According to a first aspect of the present invention, there is provided a semiconductor chip connection structure, wherein a semiconductor chip having a bump formed on a pad is connected to a circuit board electrode by a flip chip method. In a connection structure in which the space is sealed with resin, the bump tip is connected so as to cut into the circuit board electrode.
【０００８】請求項２に記載の半導体チップの接続構造
は、請求項１において、バンプが基底部とこの基底部上
に連なる柱状部とからなる凸形状のものであって、前記
柱状部が回路基板電極に食い込む形で接続されているこ
とを特徴とする。According to a second aspect of the present invention, in the semiconductor chip connection structure according to the first aspect, the bump has a convex shape including a base portion and a columnar portion connected to the base portion, wherein the columnar portion is a circuit. It is characterized by being connected so as to bite into the substrate electrode.
【０００９】請求項３に記載の半導体チップの接続構造
は、請求項２において、バンプがワイヤーバンピング法
により形成された凸形状のものであって、基底部とこの
基底部上に連なる、前記柱状部としてのヒゲ部とからな
り、該ヒゲ部が回路基板電極に食い込む形で接続されて
いることを特徴とする。According to a third aspect of the present invention, in the connection structure of the semiconductor chip according to the second aspect, the bump is formed in a convex shape by a wire bumping method, and the columnar shape is continuous with the base. And a beard portion as a portion, wherein the beard portion is connected so as to cut into the circuit board electrode.
【００１０】請求項４に記載の半導体チップの接続方法
は、請求項２または３の接続構造を得るための方法であ
って、半導体チップを回路基板に接続する際に、高加重
を加えることにより前記バンプの柱状部を、これが回路
基板電極に食い込む形で接続することを特徴とする。According to a fourth aspect of the present invention, there is provided a method for connecting a semiconductor chip to a connection structure according to the second or third aspect, wherein a high weight is applied when the semiconductor chip is connected to a circuit board. The pillar-shaped portions of the bumps are connected so as to bite into the circuit board electrodes.
【００１１】請求項５に記載の半導体チップの接続方法
は、請求項４において、あらかじめ回路基板上に封止樹
脂層を形成し、その後に半導体チップを加熱・加圧して
接続することを特徴とする。According to a fifth aspect of the present invention, there is provided a method of connecting a semiconductor chip according to the fourth aspect, wherein a sealing resin layer is formed in advance on a circuit board, and then the semiconductor chip is connected by heating and pressing. I do.
【００１２】請求項６に記載の半導体チップの接続方法
は、請求項４において、あらかじめ回路基板上に封止樹
脂層を形成するとともに、回路基板電極に異方性導電ペ
ーストを塗布し、その後に半導体チップを加熱・加圧し
て接続することを特徴とする。According to a sixth aspect of the present invention, there is provided a method of connecting a semiconductor chip according to the fourth aspect, wherein a sealing resin layer is formed on a circuit board in advance, and an anisotropic conductive paste is applied to circuit board electrodes. The semiconductor chip is connected by heating and pressing.
【００１３】[0013]
【発明の実施の形態】以下、本発明の実施の形態を、図
面を参照しながら説明する。 実施の形態１（請求項１〜４） 図１は半導体チップの接続構造を示す模式的断面図、図
２はバンプ形成工程の説明図、図３は半導体チップの接
続工程を示す模式的断面図である。この接続構造では、
半導体チップ１０上にパッド１１と、このパッド１１の
中心部上にバンプ１２を形成し、回路基板２０上には回
路基板電極２１を設け、半導体チップ１０を回路基板電
極２１上にフリップチップ方式で接続した構造であっ
て、バンプ１２の先端部が回路基板電極２１に食い込む
形態で接続されている。すなわち、バンプ１２はワイヤ
ーバンピング法により形成された凸形状のもので、基底
部１２ａと、その上に連なる柱状部（ヒゲ部）１２ｂと
からなっている。そして、このヒゲ部１２ｂの全体が回
路基板電極２１に食い込む形で接続されている。Embodiments of the present invention will be described below with reference to the drawings. First Embodiment (Claims 1 to 4) FIG. 1 is a schematic cross-sectional view showing a connection structure of a semiconductor chip, FIG. 2 is an explanatory view of a bump forming step, and FIG. 3 is a schematic cross-sectional view showing a connection step of a semiconductor chip. It is. In this connection structure,
A pad 11 is formed on a semiconductor chip 10 and a bump 12 is formed on the center of the pad 11. A circuit board electrode 21 is provided on a circuit board 20, and the semiconductor chip 10 is mounted on the circuit board electrode 21 by a flip chip method. The connection structure is such that the tip of the bump 12 is connected to the circuit board electrode 21. That is, the bump 12 has a convex shape formed by a wire bumping method, and includes a base portion 12a and a columnar portion (whisker portion) 12b continuous thereon. The whole of the beard portion 12b is connected so as to cut into the circuit board electrode 21.
【００１４】上記接続構造を得る方法について説明する
と、まず、図２（ａ）〜（ｄ）に示す工程で、半導体チ
ップ１０上にバンプ１２を形成する。それには、ワイヤ
ーボンディング装置により、半導体チップ１０のバンプ
形成位置に（すなわちパッド上に）金ワイヤー４１を接
合した後、キャピラリー４２を微小に上昇させた時点で
ワイヤーカットを行う。なお、図２には上記パッドは示
されていない。The method for obtaining the connection structure will be described. First, bumps 12 are formed on the semiconductor chip 10 in the steps shown in FIGS. To this end, after the gold wire 41 is bonded to the bump formation position of the semiconductor chip 10 (that is, on the pad) by a wire bonding apparatus, the wire is cut when the capillary 42 is slightly raised. The pads are not shown in FIG.
【００１５】このバンプ１２の形成方法では、ワイヤー
として例えば直径２５μｍ程度の金ワイヤーを用いるこ
とにより、高さが約２５μｍで直径が約８０μｍの基底
部１２ａと、高さが約５０μｍで直径が２５μｍのヒゲ
部１２ｂとからなる、全高約７５μｍのバンプ１２を形
成することができる。これにより、約１００μｍまでの
バンプ間ピッチに対応することが可能になる。なお、バ
ンプ間ピッチを更に微細にする場合には、ワイヤー径を
更に細くすることによって、基底部１２ａの径を小さく
すれば良い。ワイヤーの材料としては、金（Ａｕ）の他
に、高融点ハンダ等のワイヤーバンピング法が実施可能
な金属材料が採用できる。In the method of forming the bumps 12, for example, a gold wire having a diameter of about 25 μm is used as a wire to form a base 12a having a height of about 25 μm and a diameter of about 80 μm, and a base part 12a having a height of about 50 μm and a diameter of 25 μm. The bump 12 having a total height of about 75 μm, which is composed of the whiskers 12b, can be formed. This makes it possible to cope with a pitch between bumps of up to about 100 μm. When the pitch between the bumps is further reduced, the diameter of the base portion 12a may be reduced by further reducing the wire diameter. As a material of the wire, other than gold (Au), a metal material such as a high melting point solder that can be subjected to a wire bumping method can be used.
【００１６】つぎに、図３をもとに、半導体チップ１０
を回路基板２０にフリップチップ方式で接続する方法に
ついて説明する。温度調節自在のヒーター（図示せず）
を備えたヘッド４３で半導体チップ１０を支持し、半導
体チップ１０のバンプ１２と回路基板２０の電極２１を
アライメント（位置合わせ）した後〔図３（ａ）〕、ヘ
ッド４３を回路基板２０に向けて降下させる〔図３
（ｂ）〕ことで、１バンプ当たり３０〜４０ｇｆの加重
を加えるとの同時に加熱（加熱・加圧工程）して、半導
体チップ１０を回路基板２０に接続する。この場合、ヒ
ゲ部１２ｂは多少潰れながら、その全体が電極２１に食
い込んだ形となる〔図３（ｃ）〕。Next, based on FIG.
Will be described with reference to FIG. Temperature adjustable heater (not shown)
After the semiconductor chip 10 is supported by the head 43 provided with the semiconductor chip 10 and the bumps 12 of the semiconductor chip 10 are aligned with the electrodes 21 of the circuit board 20 (FIG. 3A), the head 43 is directed toward the circuit board 20. And lower it (Fig. 3
(B)], the semiconductor chip 10 is connected to the circuit board 20 by heating (heating / pressing step) at the same time as applying a weight of 30 to 40 gf per bump. In this case, while the whisker portion 12b is slightly crushed, the entire portion is cut into the electrode 21 (FIG. 3C).
【００１７】ところで、ワイヤーバンピング法で形成さ
れたバンプ間には、数μｍの高さバラツキが生じるの
で、異方性導電部材（ＡＣＦ，ＡＣＰ）を用いる従来の
半導体チップ接続方法では、バンプ高さを揃えるための
レベリング工程が必要であった。これに対し本発明で
は、接続時にバンプ先端部が押し潰された形状に変形す
るとともに、電極に食い込んで接続されるため、バンプ
間の高さバラツキが吸収され、したがって上記レベリン
グ工程が不要となる。また、回路基板電極の材料は特別
柔らかいものである必要はなく、銅で形成された電極上
にニッケルメッキ、金フラッシュメッキ等を施した、回
路基板に一般的に使用されている電極で良い。さらに、
接続時に熱を加えバンプ材料と電極材料との相互の拡散
を促進させることにより、接続の信頼性を安定させると
ともに、次工程（封止樹脂の注入・硬化）でのハンドリ
ング時の、半導体チップと回路基板とのズレを防止する
ことができる。By the way, since a height variation of several μm occurs between the bumps formed by the wire bumping method, the bump height is reduced by the conventional semiconductor chip connecting method using anisotropic conductive members (ACF, ACP). A leveling step was needed to make the adjustments. On the other hand, in the present invention, the bump tip is deformed into a crushed shape at the time of connection, and the connection is made by biting into the electrode, so that the height variation between the bumps is absorbed, and the leveling step is not required. . The material of the circuit board electrode does not need to be particularly soft, and may be an electrode generally used for a circuit board in which nickel plating, gold flash plating, or the like is applied to an electrode made of copper. further,
Heat is applied at the time of connection to promote mutual diffusion between the bump material and the electrode material, thereby stabilizing the reliability of the connection and at the same time handling the semiconductor chip during handling in the next step (injection and curing of the sealing resin). The deviation from the circuit board can be prevented.
【００１８】つぎに、図３（ｄ）に示すように、半導体
チップ１０・回路基板２０間に封止樹脂３１ａを注入
し、硬化させて工程が完了する。封止樹脂３１ａとして
は、半導体チップのフリップチップ実装の封止工程で一
般に使用されているエポキシ系樹脂が採用できる。また
硬化条件は、封止樹脂注入後の半導体チップ・回路基板
を、例えばオーブンに入れて約１５０℃で約２時間加熱
すれば良い。Next, as shown in FIG. 3 (d), a sealing resin 31a is injected between the semiconductor chip 10 and the circuit board 20 and cured to complete the process. As the sealing resin 31a, an epoxy resin generally used in a sealing step of flip chip mounting of a semiconductor chip can be employed. The curing condition may be such that the semiconductor chip / circuit board after the injection of the sealing resin is heated, for example, at about 150 ° C. for about 2 hours in an oven.
【００１９】実施の形態２（請求項１〜５） 図４は半導体チップの接続方法を示す模式的断面図であ
る。図４（ａ）に示すように、回路基板２０上に電極２
１を多数設け、電極２１群で包囲される基板部分に封止
樹脂層３１を形成する。他方、図２に示す方法により半
導体チップ１０上にバンプ１２群を形成する。ついで、
図４（ｂ）に示すように、半導体チップ１０をヘッド４
３で支持し、半導体チップ１０のバンプ１２と回路基板
２０の電極２１をアライメントした後、図４（ｃ）
（ｄ）のようにヘッド４３により半導体チップ１０を、
加熱しながら回路基板２０に対して押する（加熱・加圧
工程）ことで、半導体チップ１０を回路基板２０に接続
する。Embodiment 2 (Claims 1 to 5) FIG. 4 is a schematic sectional view showing a method of connecting semiconductor chips. As shown in FIG. 4A, the electrode 2 is placed on the circuit board 20.
1 are provided, and a sealing resin layer 31 is formed on a substrate portion surrounded by the electrode 21 group. On the other hand, a group of bumps 12 is formed on the semiconductor chip 10 by the method shown in FIG. Then
As shown in FIG. 4B, the semiconductor chip 10 is
3 and the bumps 12 of the semiconductor chip 10 and the electrodes 21 of the circuit board 20 are aligned.
The semiconductor chip 10 is moved by the head 43 as shown in FIG.
The semiconductor chip 10 is connected to the circuit board 20 by pressing against the circuit board 20 while heating (heating / pressing step).
【００２０】上記封止樹脂層３１の形成〔図４（ａ）の
工程〕は印刷、ディスペンス方式等で行い、封止樹脂層
３１の量は、接続後の半導体チップ・回路基板間の隙間
を充填するのに充分なものとするとともに、封止樹脂層
３１が電極２１に接触しないように配慮する。この状態
で接続（上記加熱・加圧工程）すると、バンプ１２が電
極２１に接触し食い込んだ後に、封止樹脂がバンプ１２
周辺および半導体チップ１０のエッジ部に移動するの
で、バンプ１２と電極２１との接続部に封止樹脂が介在
することなく、安定した接続構造が得られる。The formation of the sealing resin layer 31 (the step of FIG. 4A) is performed by printing, dispensing, or the like, and the amount of the sealing resin layer 31 is determined by the gap between the semiconductor chip and the circuit board after connection. It should be sufficient to be filled and care should be taken so that the sealing resin layer 31 does not contact the electrode 21. If connection (heating / pressing step) is performed in this state, after the bump 12 contacts and bites into the electrode 21, the sealing resin
Since it moves to the periphery and to the edge of the semiconductor chip 10, a stable connection structure can be obtained without the sealing resin intervening at the connection between the bump 12 and the electrode 21.
【００２１】接続後、封止樹脂をオーブン等で加熱し、
完全に硬化させることでプロセスが完了する。この実施
の形態によれば、あらかじめ回路基板上に封止樹脂層を
形成するので、封止樹脂の注入工程を省略することがで
きる。After the connection, the sealing resin is heated in an oven or the like,
Complete curing completes the process. According to this embodiment, since the sealing resin layer is formed on the circuit board in advance, the step of injecting the sealing resin can be omitted.
【００２２】実施の形態３（請求項１〜４および６） 図５は半導体チップの接続方法を示す模式的断面図であ
る。図５（ａ）に示すように、回路基板２０上に電極２
１を多数設け、電極２１群で包囲される基板部分に封止
樹脂層３１を形成し、電極２１群上に異方性導電ペース
ト３２を塗布する。他方、図２に示す方法により半導体
チップ１０上にバンプ１２群を形成する。ついで、図５
（ｂ）に示すように、半導体チップ１０をヘッド４３で
支持し、半導体チップ１０のバンプ１２と回路基板２０
の電極２１をアライメントした後、図５（ｃ）（ｄ）の
ようにヘッド４３により半導体チップ１０を、加熱しな
がら回路基板２０に対して押圧する（加熱・加圧工程）
ことで、半導体チップ１０を回路基板２０に接続する。Third Embodiment (Claims 1 to 4 and 6) FIG. 5 is a schematic sectional view showing a method of connecting semiconductor chips. As shown in FIG. 5A, the electrode 2 is placed on the circuit board 20.
The sealing resin layer 31 is formed on the substrate portion surrounded by the electrode 21 group, and an anisotropic conductive paste 32 is applied on the electrode 21 group. On the other hand, a group of bumps 12 is formed on the semiconductor chip 10 by the method shown in FIG. Then, FIG.
As shown in (b), the semiconductor chip 10 is supported by the head 43, and the bumps 12 of the semiconductor chip 10 and the circuit board 20 are supported.
After the electrodes 21 are aligned, the semiconductor chip 10 is pressed against the circuit board 20 while being heated by the head 43 as shown in FIGS. 5C and 5D (heating / pressing step).
Thus, the semiconductor chip 10 is connected to the circuit board 20.
【００２３】電極２１群上に異方性導電ペースト３２を
薄く塗布することで、図６に示すように、ペースト３２
中に存在する導電粒子３２ａ（金、銀、銅、ニッケル等
の金属粒子、あるいはこれらの金属粒子を樹脂で絶縁被
覆したもの）を介してバンプ１２が電極２１に食い込ん
だ形態で接続される。これに対し、従来の接続方法では
図７に示すように、バンプ１２・電極２１間に存在する
導電粒子３２ａの量を多くするのは難しい。このよう
に、図５の接続方法によれば、一般的なフリップチップ
接続方法、すなわちバンプ形成後にレベリングを行い、
異方性導電部材により接続する方法に比べて、バンプと
電極の接触面積が増大するので、バンプ・電極間に介在
する導電粒子の数が多くなり、安定した接続抵抗が得ら
れる。By applying a thin anisotropic conductive paste 32 on the group of electrodes 21, as shown in FIG.
The bumps 12 are connected to the electrodes 21 via conductive particles 32a (metal particles of gold, silver, copper, nickel, or the like, or those obtained by insulating these metal particles with a resin). On the other hand, as shown in FIG. 7, it is difficult to increase the amount of the conductive particles 32a existing between the bump 12 and the electrode 21 by the conventional connection method. As described above, according to the connection method of FIG. 5, a general flip-chip connection method, that is, leveling is performed after bump formation,
Since the contact area between the bump and the electrode is increased as compared with the connection method using an anisotropic conductive member, the number of conductive particles interposed between the bump and the electrode is increased, and a stable connection resistance is obtained.
【００２４】[0024]
【発明の効果】以上の説明で明らかなように、本発明に
よれば以下の効果が得られる。 （１）請求項１，２に係る発明の効果 バンプ先端部が回路基板電極に食い込む形で接続されて
いるため、バンプと電極との接触面積が大きくなるう
え、横方向（回路基板面に沿う方向）に働く力に対して
もバンプと電極との接触が保たれるので、高い接続信頼
性が得られる。As apparent from the above description, the following effects can be obtained according to the present invention. (1) Effects of the Inventions According to Claims 1 and 2 Since the tip of the bump is connected so as to bite into the circuit board electrode, the contact area between the bump and the electrode is increased, and the bump area is increased in the horizontal direction (along the circuit board surface). Direction), the contact between the bump and the electrode is maintained, so that high connection reliability can be obtained.
【００２５】（２）請求項３に係る発明の効果 バンプがワイヤーバンピング法により形成された凸形状
のものであって、基底部とこの基底部上に連なる柱状の
ヒゲ部とからなり、該ヒゲ部が回路基板電極に食い込む
形で接続されているため、請求項１，２の発明による効
果が得られるバンプを容易に形成することができる。す
なわち、ワイヤーバンピング法による凸形状のバンプを
そのまま利用することで、凸形状を得るための特別の治
具や工程が不要になる。(2) Effect of the invention according to claim 3 The bump has a convex shape formed by a wire bumping method, and comprises a base portion and a column-shaped mustache portion continuous on the base portion. Since the parts are connected to the circuit board electrodes so as to bite, the bumps having the effects of the first and second aspects of the present invention can be easily formed. That is, by using the bumps of the convex shape by the wire bumping method as they are, a special jig or process for obtaining the convex shape is not required.
【００２６】（３）請求項４に係る発明の効果 半導体チップを回路基板に接続する際に、高加重を加え
ることによりバンプの柱状部を、これが回路基板電極に
食い込む形で接続するので、回路基板電極に凹部を形成
するための前処理を行うが必要がない。また、接続時に
バンプ柱状部が多少変形して複数のバンプ間で高さが揃
うため、バンプのレベリング工程を省略することができ
る。(3) Effect of the Invention According to Claim 4 When connecting the semiconductor chip to the circuit board, the columnar portion of the bump is connected to the circuit board electrode by applying a high load so that the bump bites into the circuit board electrode. A pretreatment for forming a concave portion in the substrate electrode is not required, but is necessary. In addition, the bump columnar part is slightly deformed at the time of connection, and the height is uniform among the plurality of bumps, so that the bump leveling step can be omitted.
【００２７】（４）請求項５に係る発明の効果 あらかじめ回路基板上に封止樹脂層を形成し、その後に
半導体チップを加熱・加圧して接続するので、接続と樹
脂封止を同時に行うことができる。このため樹脂注入工
程が省略でき、工程の短縮が可能となる。(4) Effect of the invention according to claim 5 Since a sealing resin layer is formed on a circuit board in advance, and then the semiconductor chip is connected by heating and pressing, the connection and resin sealing are performed simultaneously. Can be. For this reason, the resin injection step can be omitted, and the step can be shortened.
【００２８】（５）請求項６に係る発明の効果 回路基板上に封止樹脂層を形成するとともに、回路基板
電極に異方性導電ペーストを塗布した後に、半導体チッ
プを加熱・加圧して接続するので、バンプが電極に食い
込むことによって異方性導電ペースト中の導電粒子がバ
ンプと接触する面積が大きくなり、バンプ・電極間に介
在する導電粒子数が増加するため、安定した接続抵抗が
得られるうえ、請求項５の発明による効果も得られる。(5) Effects of the Invention According to Claim 6 After forming a sealing resin layer on a circuit board and applying an anisotropic conductive paste to circuit board electrodes, the semiconductor chip is connected by heating and pressing. As a result, the area where the conductive particles in the anisotropic conductive paste comes into contact with the bumps increases as the bumps dig into the electrodes, and the number of conductive particles interposed between the bumps and the electrodes increases, resulting in a stable connection resistance. In addition, the effect of the invention of claim 5 can be obtained.
【図１】本発明の実施の形態１を示す模式的断面図であ
る。FIG. 1 is a schematic sectional view showing Embodiment 1 of the present invention.
【図２】実施の形態１に係るバンプ形成工程の説明図で
ある。FIG. 2 is an explanatory diagram of a bump forming step according to the first embodiment.
【図３】実施の形態１に係る半導体チップの接続工程を
示す模式的断面図である。FIG. 3 is a schematic cross-sectional view showing a step of connecting a semiconductor chip according to the first embodiment.
【図４】本発明の実施の形態２を示す模式的断面図であ
る。FIG. 4 is a schematic sectional view showing Embodiment 2 of the present invention.
【図５】本発明の実施の形態３を示す模式的断面図であ
る。FIG. 5 is a schematic sectional view showing Embodiment 3 of the present invention.
【図６】実施の形態３に係る半導体チップの接続構造を
示す模式的断面図である。FIG. 6 is a schematic sectional view showing a connection structure of a semiconductor chip according to a third embodiment.
【図７】従来技術に係る半導体チップの接続構造を、図
６の接続構造と比較して示す模式的断面図である。FIG. 7 is a schematic cross-sectional view showing a connection structure of a semiconductor chip according to a conventional technique in comparison with the connection structure of FIG.
【図８】特開平９−２２３７２１号公報に開示された半
導体チップの接続構造を示す断面図である。FIG. 8 is a cross-sectional view showing a connection structure of a semiconductor chip disclosed in Japanese Patent Application Laid-Open No. 9-223721.
１０ 半導体チップ １１ パッド １２ バンプ １２ａ 基底部 １２ｂ 柱状部（ヒゲ部） ２０ 回路基板 ２１ 回路基板電極 ３１ 封止樹脂層 ３１ａ 封止樹脂 ３２ 異方性導電ペースト ３２ａ 導電粒子 ４１ 金ワイヤー ４２ キャピラリー ４３ ヘッド DESCRIPTION OF SYMBOLS 10 Semiconductor chip 11 Pad 12 Bump 12a Base part 12b Column part (whisker part) 20 Circuit board 21 Circuit board electrode 31 Sealing resin layer 31a Sealing resin 32 Anisotropic conductive paste 32a Conductive particles 41 Gold wire 42 Capillary 43 Head
Claims (6)
ップを回路基板電極上にフリップチップ方式で接続し、
半導体チップ・回路基板間を樹脂で封止した接続構造に
おいて、バンプ先端部が回路基板電極に食い込む形で接
続されていることを特徴とする半導体チップの接続構
造。A semiconductor chip having a bump formed on a pad is connected to a circuit board electrode by a flip chip method;
A connection structure for a semiconductor chip, wherein a connection portion in which a semiconductor chip and a circuit board are sealed with a resin is connected so that a tip portion of a bump bites into a circuit board electrode.
の基底部上に連なる柱状部とからなる凸形状のものであ
って、前記柱状部が回路基板電極に食い込む形で接続さ
れていることを特徴とする半導体チップの接続構造。2. The bump according to claim 1, wherein the bump has a convex shape including a base portion and a columnar portion connected to the base portion, and the columnar portion is connected so as to bite into a circuit board electrode. A connection structure of a semiconductor chip characterized by the above-mentioned.
ンピング法により形成された凸形状のものであって、基
底部とこの基底部上に連なる、前記柱状部としてのヒゲ
部とからなり、該ヒゲ部が回路基板電極に食い込む形で
接続されていることを特徴とする半導体チップの接続構
造。3. The whiskers according to claim 2, wherein the bumps have a convex shape formed by a wire bumping method, and include a base portion and a whisker portion as the columnar portion connected to the base portion. A connection structure for a semiconductor chip, wherein the parts are connected so as to bite into circuit board electrodes.
の方法であって、半導体チップを回路基板に接続する際
に、高加重を加えることにより前記バンプの柱状部を、
これが回路基板電極に食い込む形で接続することを特徴
とする半導体チップの接続方法。4. A method for obtaining the connection structure according to claim 2 or 3, wherein when connecting the semiconductor chip to the circuit board, a columnar portion of the bump is formed by applying a high load.
A method of connecting a semiconductor chip, wherein the connection is made by cutting into a circuit board electrode.
上に封止樹脂層を形成し、その後に半導体チップを加熱
・加圧して接続することを特徴とする半導体チップの接
続方法。5. The method of connecting a semiconductor chip according to claim 4, wherein a sealing resin layer is formed on the circuit board in advance, and then the semiconductor chip is connected by heating and pressing.
上に封止樹脂層を形成するとともに、回路基板電極に異
方性導電ペーストを塗布し、その後に半導体チップを加
熱・加圧して接続することを特徴とする半導体チップの
接続方法。6. The method according to claim 4, wherein a sealing resin layer is previously formed on the circuit board, an anisotropic conductive paste is applied to the circuit board electrodes, and then the semiconductor chip is connected by heating and pressing. A method for connecting semiconductor chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10332042A JP2000150566A (en) | 1998-11-05 | 1998-11-05 | Connecting structure and its connection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10332042A JP2000150566A (en) | 1998-11-05 | 1998-11-05 | Connecting structure and its connection method |
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| Publication Number | Publication Date |
|---|---|
| JP2000150566A true JP2000150566A (en) | 2000-05-30 |
Family
ID=18250497
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|---|---|---|---|
| JP10332042A Pending JP2000150566A (en) | 1998-11-05 | 1998-11-05 | Connecting structure and its connection method |
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| Country | Link |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002097877A1 (en) * | 2001-05-28 | 2002-12-05 | Infineon Technologies Ag | A method of packaging a semiconductor chip |
-
1998
- 1998-11-05 JP JP10332042A patent/JP2000150566A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002097877A1 (en) * | 2001-05-28 | 2002-12-05 | Infineon Technologies Ag | A method of packaging a semiconductor chip |
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