JP3351091B2 - Semiconductor device mounting method - Google Patents

Semiconductor device mounting method

Info

Publication number
JP3351091B2
JP3351091B2 JP6471094A JP6471094A JP3351091B2 JP 3351091 B2 JP3351091 B2 JP 3351091B2 JP 6471094 A JP6471094 A JP 6471094A JP 6471094 A JP6471094 A JP 6471094A JP 3351091 B2 JP3351091 B2 JP 3351091B2
Authority
JP
Japan
Prior art keywords
bump
wiring board
electrode
bonding
resin liquid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP6471094A
Other languages
Japanese (ja)
Other versions
JPH07273147A (en
Inventor
俊夫 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP6471094A priority Critical patent/JP3351091B2/en
Publication of JPH07273147A publication Critical patent/JPH07273147A/en
Application granted granted Critical
Publication of JP3351091B2 publication Critical patent/JP3351091B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は、フェイスダウンで実
装される半導体装置の実装方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor device mounted face-down.

【0002】[0002]

【従来の技術】特開平3−108734号公報号公報
は、半導体チップのバンプを配線基板の配線電極に接合
するフェィスダウンのフリップチップ実装方法の例を開
示している。前記公報によれば、バンプを配線基板の配
線電極に接合した後に半導体チップと配線基板との間の
隙間に樹脂液を注入し、この樹脂液を硬化させて電極表
面などの保護、及び両者の接合強度の向上を図ることを
開示している。更に、前記の公報は、バンプを配線基板
の配線電極に接合する前に半導体チップと配線基板との
間の隙間となる予定の領域に樹脂液を予め付着させてお
き、バンプ接合時により生じた上記隙間をこの樹脂液で
満たし、この樹脂液を硬化させて電極表面などの保護、
及び両者の接合強度の向上を図ることを開示している。
2. Description of the Related Art Japanese Patent Laying-Open No. 3-108734 discloses an example of a face-down flip-chip mounting method in which bumps of a semiconductor chip are joined to wiring electrodes of a wiring board. According to the publication, after bonding the bump to the wiring electrode of the wiring board, a resin liquid is injected into a gap between the semiconductor chip and the wiring board, and the resin liquid is cured to protect the electrode surface and the like, It discloses that the joining strength is improved. Further, the above publication discloses that a resin liquid is previously adhered to an area to be a gap between a semiconductor chip and a wiring board before the bump is bonded to a wiring electrode of the wiring board, and the resin liquid is caused at the time of bump bonding. Fill the gap with this resin liquid, cure this resin liquid to protect the electrode surface, etc.
And that the joint strength between the two is improved.

【0003】[0003]

【発明が解決しようとする課題】しかしながら上記した
従来の樹脂液充填方式は、以下の問題点を有していた。
まず、バンプの熱圧着後の樹脂液注入では、半導体チッ
プと配線基板との間の隙間が狭小であるので樹脂液の注
入が容易でなく、注入時間が長くなったり、内部に気泡
(ボイド)を巻き込むという問題があった。
However, the above-mentioned conventional resin liquid filling method has the following problems.
First, in the injection of the resin liquid after the thermocompression bonding of the bumps, the gap between the semiconductor chip and the wiring board is narrow, so that the injection of the resin liquid is not easy, and the injection time becomes long or bubbles (voids) are formed inside. Was involved.

【0004】一方、予め、配線基板又は半導体チップに
樹脂液を付着させておき、バンプの熱圧着時にこの樹脂
液を押し広げて、上記隙間に樹脂液を充満させる方法で
は、バンプと配線基板の配線電極との間に樹脂液が回り
込み、バンプの接合不良を招く可能性があった。特に、
通常は樹脂液にガラスの小片からなるフィラーを樹脂液
に混入するために、このフィラーがバンプと配線電極と
の間に噛み込んで接合不良を生じる可能性があった。
On the other hand, in a method in which a resin liquid is previously adhered to a wiring board or a semiconductor chip, and the resin liquid is pushed and spread at the time of thermocompression bonding of the bumps so that the gap is filled with the resin liquid, There is a possibility that the resin liquid wraps around between the wiring electrodes and leads to defective bonding of the bumps. In particular,
Normally, since a filler made of small pieces of glass is mixed into the resin liquid, the filler may bite between the bumps and the wiring electrodes, which may cause a bonding failure.

【0005】本発明は上記問題点に鑑みなされたもので
あり、バンプと配線電極との接合性を悪化させることな
く樹脂液の注入の容易化を実現可能な半導体装置の実装
方法を提供することを、その目的としている。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a method of mounting a semiconductor device capable of facilitating the injection of a resin solution without deteriorating the bondability between a bump and a wiring electrode. For that purpose.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置の実
装方法は、半導体チップの接続電極表面に形成された軟
質突起電極を配線基板の接続電極上に当接させるチップ
載置工程と、その後、前記軟質突起電極をその融点未満
の温度条件にて加熱して前記配線基板の接続電極に押し
付けることにより、前記軟質突起電極を塑性変形させ、
高さを縮小させ、前記配線基板の接続電極と接合させる
前期接合工程と、その後、前記半導体チップ及び前記配
線基板の間の隙間に樹脂液を注入する樹脂液注入工程
と、その後、前記軟質突起電極をその融点未満の温度条
にて加熱して前記配線基板の接続電極に押し付けるこ
とにより、前記軟質突起電極を更に塑性変形させ、高さ
を更に縮小させ、前記配線基板の接続電極との前記接合
を強化させ、その後、前記樹脂液を熱で硬化させる後期
接合工程とを備えることを特徴としている。
According to the present invention, there is provided a method of mounting a semiconductor device, comprising: a chip mounting step of bringing a soft projection electrode formed on a connection electrode surface of a semiconductor chip into contact with a connection electrode of a wiring board; , by pressing the connecting electrodes of the wiring substrate by heating the soft protruding electrode at a temperature of less than its melting point, it is plastically deforming the soft protrusion electrodes,
A first bonding step of reducing the height and bonding to a connection electrode of the wiring board; a resin liquid injection step of subsequently injecting a resin liquid into a gap between the semiconductor chip and the wiring board; By heating the electrode under a temperature condition lower than its melting point and pressing the electrode against the connection electrode of the wiring board, the soft projection electrode is further plastically deformed, the height is further reduced, and the connection between the soft projection electrode and the connection electrode of the wiring board is reduced. to strengthen the bonding, then, it is characterized in that the resin solution and a late joining step Ru cured with heat.

【0007】第1の態様によれば、前記前期接合工程の
後から前記後期接合工程の開始までの間に前記塑性変形
を持続しつつ前記樹脂液注入工程を実施する。
[0007] According to a first aspect, implement the resin injection step while sustaining the plastic deformation during the later of the previous term bonding step and the start of the late joining step.

【0008】[0008]

【作用及び発明の効果】本発明は、半導体チップの軟質
突起電極(以下、バンプともいう)を配線基板の接続電
極上に当接させた後、熱圧着によりバンプを配線電極に
接合する前期接合工程を行い、その後、半導体チップと
配線基板の間の隙間に樹脂液を注入し、その後、再度の
熱圧着によりバンプ配線電極との接合を更に強化する
後期接合工程を行って上記接合を強化する。樹脂液はそ
の後、硬化してチップと配線基板とを接着するとともに
バンプや電極などを封止する。
According to the present invention, after a soft bump electrode (hereinafter, also referred to as a bump) of a semiconductor chip is brought into contact with a connection electrode of a wiring board, the bump is bonded to the wiring electrode by thermocompression bonding.
The first bonding step for bonding is performed, and then, a resin liquid is injected into a gap between the semiconductor chip and the wiring board, and then the bonding between the bump and the wiring electrode is further strengthened by thermocompression bonding again.
A late bonding step is performed to strengthen the bonding . Thereafter, the resin liquid is cured to bond the chip and the wiring board and to seal the bumps and the electrodes.

【0009】この発明は、バンプの熱圧着が終了する前
に樹脂液を注入するので、樹脂液が注入される上記隙間
を従来より格段に幅広とすることができ、樹脂液注入が
容易となり気泡の巻き込みを防止することができ、注入
時間も短縮することができる。また、この発明は、樹脂
液の注入前に配線基板の配線電極とバンプとの接合を開
始するので、バンプと配線電極との間に樹脂液が介在す
ることが少なく、両者の接合性を向上することができ
る。特に、樹脂液が硬質のフィラーを含む場合でも、こ
のフィラーがバンプと配線電極との間に噛み込むことが
殆どない。これは、たとえ、バンプと配線電極との当接
領域の近傍空間にフィラーがあっても、バンプの塑性変
形の過程でこの近傍空間の塑性変形方向の断面が略三角
形状となっており、この近傍空間が上記当接領域側から
滅失していくので、フィラーや樹脂が自然にこの近傍空
間から外部に押し出されるためである。これに比較し
て、バンプを配線電極に当接させる前に樹脂液をバンプ
又は配線電極に塗布する場合、バンプの頂点付近ではこ
のような押出し力が充分に作用せず、樹脂液やフィラー
が残留して接合を妨害する場合が生じてしまう。
According to the present invention, since the resin liquid is injected before the completion of the thermocompression bonding of the bumps, the gap into which the resin liquid is injected can be made much wider than before, and the injection of the resin liquid becomes easier and the air bubbles are reduced. Can be prevented, and the injection time can be shortened. Also, according to the present invention, before the resin liquid is injected , the bonding between the wiring electrode of the wiring board and the bump is opened.
Since starting, less likely to be mediated resin liquid between the bump and the wiring electrodes, it is possible to improve the bonding properties of both. In particular, even when the resin liquid contains a hard filler, the filler hardly bites between the bump and the wiring electrode. This is because, even if there is a filler in the space near the contact area between the bump and the wiring electrode, the cross section of the space in the direction of plastic deformation in the process of plastic deformation of the bump has a substantially triangular shape. This is because the filler and the resin are naturally extruded from the neighboring space to the outside because the neighboring space is lost from the contact area side. In contrast, when the resin liquid is applied to the bump or the wiring electrode before the bump is brought into contact with the wiring electrode, such a pushing force does not sufficiently act near the apex of the bump, and the resin liquid or the filler may not be applied. There is a case where it remains and hinders bonding.

【0010】[0010]

【0011】[0011]

【0012】[0012]

【実施例】【Example】

(実施例1)以下、この発明を具体化した一実施例を図
面に従って説明する。本実施例の半導体装置の実装方法
を図1を参照して説明する。図1(a)は、ガラス基板
1上に半導体チップ(ICチップ)2のバンプ3を熱圧
着する前を示し、図1(b)は、ガラス基板1上の所定
位置に半導体チップ2のバンプ3を当接し、バンプ3の
熱圧着を一部実施した後、樹脂液4を注入している状態
を示し、図1(c)は、上記樹脂液注入後、バンプ3の
熱圧着を完了した後の状態を示している。
(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings. A method for mounting the semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 1A shows a state before the bumps 3 of the semiconductor chip (IC chip) 2 are thermocompression-bonded on the glass substrate 1, and FIG. 3 shows a state in which the resin liquid 4 is injected after the thermocompression bonding of the bump 3 is partially performed, and FIG. 1C shows that the thermocompression bonding of the bump 3 is completed after the resin liquid injection. The latter state is shown.

【0013】図1(a)において、バンプ3ははんだバ
ンプであり、めっきにより形成しているが、金や銅や錫
などを含む軟質の金属からなるバンプであればよく、ま
た、印刷やウエハの表面を金属浴に濡らしてバンプを形
成してもよい。図2に、熱圧着前のバンプ3の断面図を
示す。ICチップ2の表面(図2では下面)にはチップ
側の接続電極としてアルミ電極23が形成されており、
その表面はパッシベーション層24にて覆われている。
又、アルミ電極23の一部が露出され、この露出部分に
おいて、アルミ電極23上にはクロムやチタンよりなる
バリアメタル25が形成されている。バリアメタル25
上には銅バンプ31が形成され、銅バンプ31の表面に
ははんだバンプ32が形成されている。はんだバンプ3
2としては、Pbー63Sn(共晶ハンダ)が用いられ
ており、このはんだの融点は183℃である。バンプ3
の高さすなわち銅バンプ31+はんだバンプ32の合計
の高さHoは熱圧着前で100μmとした。
In FIG. 1A, a bump 3 is a solder bump and is formed by plating. The bump 3 may be a bump made of a soft metal such as gold, copper, tin, or the like. May be wetted with a metal bath to form bumps. FIG. 2 shows a sectional view of the bump 3 before thermocompression bonding. An aluminum electrode 23 is formed on the surface (the lower surface in FIG. 2) of the IC chip 2 as a connection electrode on the chip side.
Its surface is covered with a passivation layer 24.
Further, a part of the aluminum electrode 23 is exposed, and a barrier metal 25 made of chromium or titanium is formed on the aluminum electrode 23 in this exposed part. Barrier metal 25
A copper bump 31 is formed thereon, and a solder bump 32 is formed on the surface of the copper bump 31. Solder bump 3
For Pb-63Sn (eutectic solder), the melting point of this solder is 183 ° C. Bump 3
, That is, the total height Ho of the copper bumps 31 and the solder bumps 32 was 100 μm before thermocompression bonding.

【0014】製造工程としては、バリアメタル25を蒸
着後、銅及びはんだの連続メッキを行い、さらに、不活
性ガス雰囲気炉中にて250℃ではんだバンプ32をリ
フローすることによりこの軟質突起電極(バンプ)3の
はんだバンプ32を半球状とすればよい。ボンディング
前のガラス基板(配線基板)1を図3に示す。
In the manufacturing process, after the barrier metal 25 is deposited, continuous plating of copper and solder is performed, and the solder bumps 32 are reflowed at 250 ° C. in an inert gas atmosphere furnace so that the soft bump electrodes ( The solder bumps 32 of the (bump) 3 may be hemispherical. FIG. 3 shows a glass substrate (wiring substrate) 1 before bonding.

【0015】ガラス基板1には、チップ側の接続電極と
しての導電パタ−ン10が形成されている。導電パタ−
ン10は三層構造をなし、ソーダガラス上にITO(イ
ンジウム・スズ・オキサイド)層11とニッケル層12
と金層13とが順に積層されている。この積層構造は、
ITO/Ni/Auを蒸着又はメッキすることにより形
成される。ここで、表面の金層13は、配線母材として
のITO層11とニッケル層12の酸化防止材となって
いる。
A conductive pattern 10 is formed on the glass substrate 1 as a connection electrode on the chip side. Conductive pattern
The iron 10 has a three-layer structure, and has an ITO (indium tin oxide) layer 11 and a nickel layer 12 on soda glass.
And the gold layer 13 are sequentially laminated. This laminated structure,
It is formed by depositing or plating ITO / Ni / Au. Here, the gold layer 13 on the surface is an antioxidant for the ITO layer 11 and the nickel layer 12 as the wiring base material.

【0016】次に、工程を説明する。 (チップ載置工程)まず、ガラス基板(配線基板)1を
所定位置に置き、吸着ヘッド(図示せず)によりICチ
ップ2をガラス基板1の上方に搬送し、位置合わせを行
う(図1(a)参照)。次に、ICチップ2をガラス基
板1上の所定位置に載置する。これにより、バンプ3を
ガラス基板1上の導電パターン10に当接させる。 (前期接合工程)その後、タングステン(W)製の加熱
ヘッド(図示せず)にてICチップ2の裏面(図1の上
面)から1つのバンプ3当たり所定荷重をかけるととも
に、加熱ヘッドの温度を120〜175℃として5〜1
0秒間保持する。つまり、バンプ3のはんだバンプ32
の融点の183℃よりも低い温度で、ICチップ2とガ
ラス基板1との間を加圧してはんだバンプ32を塑性変
形させながら接合する。このとき、加熱温度がはんだバ
ンプ32の融点以下なのではんだバンプ32は溶融して
いないが柔らかくなっており、接合部は変形し面接触と
なっており、その分、バンプ3の高さは図1(b)に示
すように元の高さHoからH1まで減る。
Next, the steps will be described. (Chip mounting step) First, the glass substrate (wiring substrate) 1 is placed at a predetermined position, and the IC chip 2 is transported above the glass substrate 1 by a suction head (not shown) to perform alignment (FIG. 1 ( a)). Next, the IC chip 2 is placed at a predetermined position on the glass substrate 1. Thereby, the bump 3 is brought into contact with the conductive pattern 10 on the glass substrate 1. (First bonding step) Thereafter, a predetermined load is applied to one bump 3 from the back surface (the upper surface in FIG. 1) of the IC chip 2 by a heating head (not shown) made of tungsten (W), and the temperature of the heating head is reduced. 5-1 at 120-175 ° C
Hold for 0 seconds. That is, the solder bump 32 of the bump 3
At a temperature lower than the melting point of 183 ° C., the IC chip 2 and the glass substrate 1 are joined while plastically deforming the solder bumps 32 by applying pressure. At this time, since the heating temperature is equal to or lower than the melting point of the solder bump 32, the solder bump 32 is not melted but is soft, and the bonding portion is deformed to be in surface contact. As shown in (b), the original height Ho is reduced to H1.

【0017】ここでは、H1はHoの約75%の値とさ
れる。 (樹脂液注入工程)その後、ICチップ2とガラス基板
1との間の隙間にディスペンサのノズル5から樹脂液4
を注入する(図1(b)参照)。樹脂液4はエポキシ樹
脂を主材料とした液であって、ガラスなどからなるフィ
ラーすなわち小片を約40〜70wt%含有している。
もちろん、フィラーを含有しなくてもよい。 (後期接合工程)その後、タングステン(W)製の加熱
ヘッド(図示せず)にてICチップ2の裏面(図1の上
面)から1つのバンプ3当たり前期接合工程のときより
も大きな所定荷重をかけるとともに、加熱ヘッドの温度
を120〜175℃として5〜10秒間保持する。つま
り、バンプ3のはんだバンプ32の融点の183℃より
も低い温度で、ICチップ2とガラス基板1との間を加
圧してはんだバンプ32を塑性変形させながら接合す
る。これにより、はんだバンプ32が更に塑性変形して
ガラス基板1上の導電パターン10との接合が完了す
る。
Here, H1 is about 75% of Ho. (Resin liquid injecting step) Thereafter, the resin liquid 4 is injected into the gap between the IC chip 2 and the glass substrate 1 through the nozzle 5 of the dispenser.
(See FIG. 1B). The resin liquid 4 is a liquid containing an epoxy resin as a main material, and contains about 40 to 70% by weight of a filler made of glass or the like, that is, small pieces.
Of course, it is not necessary to contain a filler. (Late bonding step) Thereafter, a predetermined load greater than that in the previous bonding step is applied to one bump 3 from the back surface (upper surface in FIG. 1) of the IC chip 2 by a heating head (not shown) made of tungsten (W). At the same time, the temperature of the heating head is kept at 120 to 175 ° C. and kept for 5 to 10 seconds. That is, at a temperature lower than the melting point of the solder bump 32 of the bump 3 of 183 ° C., the IC chip 2 and the glass substrate 1 are pressurized and joined while plastically deforming the solder bump 32. Thereby, the solder bumps 32 are further plastically deformed, and the bonding with the conductive patterns 10 on the glass substrate 1 is completed.

【0018】この時、バンプ3の高さは図1(c)に示
すように高さH1からH2まで減る。ここでは、H2は
Hoの約50%の値とされる。また、この後期接合工程
により、ICチップ2とガラス基板1との間に充填され
ていた余分の樹脂液4は外部に押し出される。その後、
樹脂液4が重合又は熱で硬化し、作業を終了する。また
上記した加熱は、加熱ヘッドによらずに、レーザをバン
プ部分に照射することにより行ってもよい。
At this time, the height of the bump 3 is reduced from the height H1 to H2 as shown in FIG. Here, H2 is set to a value of about 50% of Ho. Further, in the latter bonding step, the excess resin liquid 4 filled between the IC chip 2 and the glass substrate 1 is pushed out. afterwards,
The resin liquid 4 is cured by polymerization or heat, and the operation is completed. Further, the above-mentioned heating may be performed by irradiating a laser to the bump portion without using the heating head.

【0019】ここで、接合条件について詳細に説明す
る。加熱時間(5〜10秒)は、加熱ヘッドから基板側
へ熱伝導が行われるに十分な時間であれば変更可能であ
る。また、この実施例では、バンプ1個当たりの荷重を
後期接合工程より増加することにより、バンプ3の高さ
を変えたが、その他、荷重印加時間又は加熱ヘッドの下
降速度を調節してバンプ3の高さを制御してもよい。す
なわち、前期接合工程において、バンプ3の高さがH1
となる時点で荷重印加を中止すればよい。
Here, the joining conditions will be described in detail. The heating time (5 to 10 seconds) can be changed as long as the time is sufficient for conducting heat from the heating head to the substrate side. Further, in this embodiment, the height of the bump 3 was changed by increasing the load per bump from the later bonding step, but the load application time or the descent speed of the heating head was adjusted to adjust the bump 3. May be controlled. That is, in the previous period bonding step, the height of the bump 3 is H1
At this point, the application of the load may be stopped.

【0020】また、接合工程すなわちはんだバンプ32
の塑性変形をゆっくりと行い、塑性変形が終了する前に
樹脂液4の注入を完了することも可能である。また、
接合工程である程度の塑性変形を実施後、そのまま加
熱ヘッドを押しつけてもっと低速で塑性変形を持続しつ
つ樹脂液注入工程を実施し、樹脂液注入完了後、後期接
合工程により塑性変形を高速で実施してもよい。
The bonding step, that is, the solder bump 32
It is also possible to perform plastic deformation slowly and to complete the injection of the resin liquid 4 before the plastic deformation is completed. Also before
After performing a certain amount of plastic deformation in the early joining process, press the heating head as it is, carry out the resin liquid injection process while maintaining the plastic deformation at a lower speed, and after the resin liquid injection is completed, perform the plastic deformation by the late joining process at high speed May be implemented.

【0021】また、加熱ヘッドは前期接合工程の開始
後、後期接合工程の終了まで荷重の変更は行うか又は荷
重も一定のままずっとICチップ2に接触させてもよ
く、その他、樹脂液注入工程時に加熱ヘッドは離脱させ
てもよい。
Further, after the start of heating heads year bonding step may or load do is change of the load until the end of the late joining process also brought into contact with the IC chip 2 much remains constant, other resin injection step At times, the heating head may be removed.

【0022】なお上記実施例では導電パタ−ン10(配
線材)をAu/Ni/ITOとしたが、Au,Ni,S
n,Ag,AgーPd,AgーPt,Cuなどはんだが
付くものであればよく、又、はんだバンプ32もPbー
63Sn以外の組成のはんだを使用してもよい。また、
前記実施例では銅バンプ31上にはんだバンプ32を設
けたが、銅バンプ31の省略も可能である。
Although the conductive pattern 10 (wiring material) is Au / Ni / ITO in the above embodiment, Au, Ni, S
Any solder such as n, Ag, Ag-Pd, Ag-Pt, and Cu may be used, and solder having a composition other than Pb-63Sn may be used for the solder bump 32. Also,
Although the solder bumps 32 are provided on the copper bumps 31 in the above embodiment, the copper bumps 31 may be omitted.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)は、バンプ3の接合開始の状態を示す模
式側面図である。(b)は、樹脂液注入工程を示す模式
側面図である。(c)は、後期接合工程(本発明でいう
接合工程)終了後を示す模式側面図である。
FIG. 1A is a schematic side view showing a state in which bonding of bumps 3 is started. (B) is a schematic side view showing a resin liquid injection step. (C) is a schematic side view showing a state after the completion of the latter bonding step (the bonding step in the present invention).

【図2】図1のバンプ3の拡大断面図である。FIG. 2 is an enlarged sectional view of a bump 3 of FIG.

【図3】図1のガラス基板1の拡大側面図である。FIG. 3 is an enlarged side view of the glass substrate 1 of FIG.

【符号の説明】 1 ガラス基板(配線基板) 2 IC(半導体)チップ 3 バンプ 10 導電パタ−ン(配線基板の接続電極)[Description of Signs] 1 Glass substrate (wiring substrate) 2 IC (semiconductor) chip 3 Bump 10 Conductive pattern (connection electrode of wiring substrate)

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/60 311 H01L 21/56 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/60 311 H01L 21/56

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体チップの接続電極表面に形成され
た軟質突起電極を配線基板の接続電極上に当接させるチ
ップ載置工程と、 その後、前記軟質突起電極をその融点未満の温度条件
て加熱して前記配線基板の接続電極に押し付けることに
より、前記軟質突起電極を塑性変形させ、高さを縮小さ
せ、前記配線基板の接続電極と接合させる前期接合工程
と、 その後、前記半導体チップ及び前記配線基板の間の隙間
に樹脂液を注入する樹脂液注入工程と、 その後、前記軟質突起電極をその融点未満の温度条件
て加熱して前記配線基板の接続電極に押し付けることに
より、前記軟質突起電極を更に塑性変形させ、高さを更
に縮小させ、前記配線基板の接続電極との前記接合を強
化させ、その後、前記樹脂液を熱で硬化させる後期接合
工程とを備えることを特徴とする半導体装置の実装方
法。
And 1. A chip-placing step of abutting the connecting electrodes formed on the surface was soft protruding electrodes of the semiconductor chip on the connection electrodes of the wiring board, then the soft protruding electrode temperature below its melting point
Heating and pressing against the connection electrode of the wiring board, the soft projection electrode is plastically deformed, the height is reduced, and the bonding step is performed with the connection electrode of the wiring board. a resin injection step of injecting a resin solution into the gap between the wiring board, then the soft protruding electrode temperature below its melting point
By heating and pressing against the connection electrode of the wiring board, the soft projection electrode is further plastically deformed, the height is further reduced, the bonding with the connection electrode of the wiring board is strengthened , and then the resin mounting method of a semiconductor device, characterized in that it comprises a later bonding step of the liquid Ru was cured by heat.
【請求項2】 前記前期接合工程の後から前記後期接合
工程の開始までの間に前記塑性変形を持続しつつ前記樹
脂液注入工程を実施する請求項1記載の半導体装置の実
装方法。
2. The method for mounting a semiconductor device according to claim 1, wherein the resin liquid injection step is performed while the plastic deformation is maintained between after the first bonding step and before the second bonding step is started.
JP6471094A 1994-04-01 1994-04-01 Semiconductor device mounting method Expired - Fee Related JP3351091B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6471094A JP3351091B2 (en) 1994-04-01 1994-04-01 Semiconductor device mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6471094A JP3351091B2 (en) 1994-04-01 1994-04-01 Semiconductor device mounting method

Publications (2)

Publication Number Publication Date
JPH07273147A JPH07273147A (en) 1995-10-20
JP3351091B2 true JP3351091B2 (en) 2002-11-25

Family

ID=13265985

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6471094A Expired - Fee Related JP3351091B2 (en) 1994-04-01 1994-04-01 Semiconductor device mounting method

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Country Link
JP (1) JP3351091B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007046416A1 (en) * 2005-10-20 2007-04-26 Matsushita Electric Industrial Co., Ltd. Electronic component mounting method
US10734350B2 (en) * 2016-05-09 2020-08-04 Hitachi Chemical Company, Ltd. Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JPH07273147A (en) 1995-10-20

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