JP3176028B2 - Flip chip mounting method and flip chip mounting structure - Google Patents
Flip chip mounting method and flip chip mounting structureInfo
- Publication number
- JP3176028B2 JP3176028B2 JP26601595A JP26601595A JP3176028B2 JP 3176028 B2 JP3176028 B2 JP 3176028B2 JP 26601595 A JP26601595 A JP 26601595A JP 26601595 A JP26601595 A JP 26601595A JP 3176028 B2 JP3176028 B2 JP 3176028B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- substrate
- multilayer substrate
- bump
- chip mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置の実装
方法及び実装構造に関するものであり、特にフリップチ
ップ実装方法及びフリップチップ実装構造に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting method and a mounting structure , and more particularly to a flip chip mounting method and a flip chip mounting structure .
【０００２】[0002]
【従来の技術】従来より、半導体装置の実装方法として
フリップチップ実装方法が広く知られており、このフリ
ップチップ実装方法を図４を用いて説明する。まず、図
４（ａ）に示すように、半導体装置５の下面に半田から
なるバンプ６を形成する。半導体装置５を実装する基板
１には、バンプ６と接合させるためのバンプ接合用電極
（図示せず）が予め形成されており、バンプ接合用電極
には半田が塗布されている。次に、図４（ｂ）に示すよ
うに、バンプ６とバンプ接合用電極上に塗布された半田
とを突接させて、半導体装置５を基板１上に載置し、リ
フローにより加熱して半田を溶融させ、バンプ６とバン
プ接合用電極とを接合させる。更に、図４（ｃ）に示す
ように、封止用樹脂７が、基板１と半導体装置５との間
隙に、端部からディスペンサー８を用いて注入され、毛
細管現象を利用して基板１と半導体装置５との接合面全
体に注入される。封止用樹脂７は熱又は紫外線によって
硬化収縮され、半導体装置５が基板１に実装される。2. Description of the Related Art Conventionally, a flip-chip mounting method has been widely known as a mounting method of a semiconductor device, and this flip-chip mounting method will be described with reference to FIG. First, as shown in FIG. 4A, a bump 6 made of solder is formed on the lower surface of the semiconductor device 5. On the substrate 1 on which the semiconductor device 5 is mounted, bump bonding electrodes (not shown) for bonding to the bumps 6 are formed in advance, and solder is applied to the bump bonding electrodes. Next, as shown in FIG. 4B, the bump 6 and the solder applied on the bump bonding electrode are brought into abutting contact with each other, the semiconductor device 5 is placed on the substrate 1, and heated by reflow. The solder is melted, and the bump 6 is bonded to the bump bonding electrode. Further, as shown in FIG. 4C, a sealing resin 7 is injected into the gap between the substrate 1 and the semiconductor device 5 from the end using a dispenser 8, and the sealing resin 7 is connected to the substrate 1 using the capillary phenomenon. It is implanted into the entire bonding surface with the semiconductor device 5. The sealing resin 7 is cured and shrunk by heat or ultraviolet rays, and the semiconductor device 5 is mounted on the substrate 1.
【０００３】[0003]
【発明が解決しようとする課題】上述のフリップチップ
実装方法では、ディスペンサーを用いて封止用樹脂を半
導体装置と基板との間隙に注入する際、封止用樹脂中に
気泡が発生し、この気泡によって半導体装置の信頼性が
悪化するという問題点があった。また、基板の反り等に
よって実装時の半導体装置の高さにバラツキが発生した
場合、バンプの変形以外に半導体装置の高さのバラツキ
を補償する手段がないので、歩留りが悪いという問題点
があった。In the above-described flip chip mounting method, when the sealing resin is injected into the gap between the semiconductor device and the substrate using a dispenser, bubbles are generated in the sealing resin. There is a problem that the reliability of the semiconductor device is deteriorated by the bubbles. Further, when the height of the semiconductor device at the time of mounting varies due to the warpage of the substrate or the like, there is no means for compensating the variation of the height of the semiconductor device other than the deformation of the bump, so that the yield is poor. Was.
【０００４】本発明は上記問題点に鑑みて為されたもの
であり、半導体装置の信頼性を向上させ、接合時の歩留
りを改善できるフリップチップ実装方法及びフリップチ
ップ実装構造を提供することを目的とするものである。[0004] The present invention has been made in view of the above problems, to improve the reliability of the semiconductor device, flip chip mounting method and Furippuchi can improve the yield at the time of bonding
It is intended to provide a top mounting structure .
【０００５】[0005]
【課題を解決するための手段】本発明では、上記目的を
達成するために、請求項１の発明は、下面にバンプが形
成された半導体装置を多層基板に実装する際、多層基板
の内層にバンプと接合する電極を形成し、多層基板の表
面から電極に達する凹部を形成し、電極上に半田を塗布
し、更に、多層基板表面の凹部以外の半導体装置接合部
位に封止用樹脂を予め塗布し、バンプを凹部に嵌合させ
て電極と突接させ、リフローにより電極上の半田を溶融
させてバンプと電極とを接合するとともに、封止用樹脂
を硬化させて半導体装置を多層基板に実装しているの
で、接合後の封止用樹脂の注入工程がなくなり、封止用
樹脂中の気泡の発生を解消することができる。また、凹
部に塗布された半田の厚みによって、バンプ実装部の高
さのバラツキを低減することができる。 In the present invention, there is provided a means for solving], in order to achieve the above object, the invention of claim 1, when mounting the semiconductor device on which the bumps are formed on the lower surface in the multilayer substrate, multilayer substrate
Forming an electrode for bonding the bump to the inner layer, the table of the multi-layer board
Forming a recess from the surface reaches the electrodes, the solder is coated on the electrode, and further, pre-coated with a sealing resin in the semiconductor device bonding sites other than the concave portion of the multi-layer substrate surface, fitting the bumps in the recess engaged
Is the electrode and突接Te, the solder on the electrodes is melted together to bond the bump and the electrode by reflowing, since by curing the sealing resin is mounting a semiconductor device on the multilayer substrate, sealing after joining The step of injecting the stopping resin is eliminated, and the generation of bubbles in the sealing resin can be eliminated. Also concave
The height of the bump mounting area depends on the thickness of the solder applied to the area.
It is possible to reduce the variation in the height.
【０００６】請求項２の発明は、表面に内層基板の一部
を露出させる凹部が形成された多層基板と、多層基板に
設けた凹部と対向する部位にバンプが設けられた半導体
装置と、凹部の底部に露出する内層基板の部位に設けら
れ半田によりバンプに接合される電極と、多層基板表面
の凹部以外の部位に塗布され、多層基板と半導体装置と
の間の隙間を封止する封止用樹脂とを備えているので、
接合後の封止用樹脂の注入工程がなくなり、封止用樹脂
中の気泡の発生を解消したフリップチップ実装構造を実
現することができる。また、凹部に塗布された半田の厚
みによって、バンプ実装部の高さのバラツキを低減する
こともできる。 According to a second aspect of the present invention, a part of the inner substrate is provided on the surface.
And a multilayer substrate with a concave portion that exposes
Semiconductor with bumps provided on the part facing the provided recess
Device and the inner substrate exposed at the bottom of the recess.
The electrodes that are joined to the bumps by soldering and the surface of the multilayer substrate
Of the multilayer substrate and the semiconductor device
And sealing resin for sealing the gap between
There is no need to inject the sealing resin after joining,
A flip-chip mounting structure that eliminates air bubbles inside
Can be manifested. The thickness of the solder applied to the recess
To reduce the variation in height of the bump mounting part
You can also.
【０００７】[0007]
【発明の実施の形態】本発明の実施の形態を図面を用い
て説明する。まず、本実施形態のフリップチップ実装方
法を用いて半導体装置を多層基板に実装する各工程を図
１を用いて説明する。まず、図１（ａ）に示すように、
６層から成る多層基板１に、基板表面から４層目に達す
る２ヵ所の凹部３をエッチングにより形成し、凹部３の
底部の４層目に電極２を夫々形成する。Embodiments of the present invention will be described with reference to the drawings. First, each step of mounting a semiconductor device on a multilayer substrate using the flip-chip mounting method of the present embodiment will be described with reference to FIG. First, as shown in FIG.
Two concave portions 3 reaching the fourth layer from the substrate surface are formed in the multilayer substrate 1 composed of six layers by etching, and the electrodes 2 are respectively formed in the fourth layer at the bottom of the concave portion 3.
【０００８】次に、図１（ｂ）に示すように、凹部３に
設けられた電極２の上方にクリーム半田４を印刷、又
は、ディスペンサー等で塗布する。更に、図１（ｃ）に
示すように、半導体装置５の接合部位で凹部３以外の多
層基板１の表面に、熱によって硬化する封止用樹脂７を
印刷、又は、ディスペンサー等で塗布する。Next, as shown in FIG. 1 (b), a cream solder 4 is printed or applied by a dispenser or the like above the electrode 2 provided in the concave portion 3. Further, as shown in FIG. 1C, a sealing resin 7 which is cured by heat is printed or applied with a dispenser or the like on the surface of the multilayer substrate 1 other than the concave portion 3 at the joint portion of the semiconductor device 5.
【０００９】一方、図１（ｄ）に示すように、多層基板
１に実装される半導体装置５の電極部（図示せず）には
バンプ６が形成されている。ここで、図２及び図３に示
すように、多層基板１に設けられた電極２の表面からの
深さは、半導体装置５に設けられたバンプ６の高さの半
分の深さとなっている。また更に、図１（ｅ）に示すよ
うに、半導体装置５は、バンプ６を凹部３に位置合わせ
して多層基板１上に載置され、半導体装置５を上方から
加圧して、バンプ６を凹部３に塗布されたクリーム半田
４に接触させている。On the other hand, as shown in FIG. 1D, bumps 6 are formed on electrode portions (not shown) of a semiconductor device 5 mounted on the multilayer substrate 1. Here, as shown in FIGS. 2 and 3, the depth from the surface of the electrode 2 provided on the multilayer substrate 1 is half the height of the bump 6 provided on the semiconductor device 5. . Further, as shown in FIG. 1 (e), the semiconductor device 5 is placed on the multilayer substrate 1 with the bumps 6 aligned with the concave portions 3, and the semiconductor device 5 is pressurized from above, and the bumps 6 are pressed. It is in contact with the cream solder 4 applied to the recess 3.
【００１０】図１（ｆ）に示すように、バンプ６を凹部
３に位置合わせして、半導体装置５を多層基板１に上方
から加圧し、バンプ６をクリーム半田４に接触させた状
態でリフロー炉に投入し、半田が溶融するのに十分な温
度に加熱し、クリーム半田４を溶融させて電極２とバン
プ６とを接合させるとともに、封止用樹脂７を硬化させ
て、半導体装置５を多層基板１に実装している。As shown in FIG. 1F, the bump 6 is aligned with the concave portion 3, the semiconductor device 5 is pressed from above on the multilayer substrate 1, and the bump 6 is brought into contact with the cream solder 4 to reflow. The semiconductor device 5 is put into a furnace, heated to a temperature sufficient to melt the solder, melts the cream solder 4 to join the electrodes 2 and the bumps 6, and cures the sealing resin 7. It is mounted on the multilayer substrate 1.
【００１１】また、本実施形態のフリップチップ実装方
法を用いて半導体装置５を多層基板１に接合した場合、
図３に示すように、半導体装置５に設けられたバンプ６
を多層基板１の凹部３に嵌合させて接合しているので、
基板表面でバンプ６を接合している場合と比較して、実
装時の半導体装置５の高さが低くなり、装置の小型化が
可能となる。When the semiconductor device 5 is bonded to the multilayer substrate 1 by using the flip chip mounting method of the present embodiment,
As shown in FIG. 3, the bump 6 provided on the semiconductor device 5
Is fitted to and joined to the concave portion 3 of the multilayer substrate 1,
The height of the semiconductor device 5 at the time of mounting is reduced as compared with the case where the bumps 6 are bonded on the substrate surface, and the device can be downsized.
【００１２】[0012]
【発明の効果】請求項１の発明は、上述のように、下面
にバンプが形成された半導体装置を多層基板に実装する
際、多層基板の内層にバンプと接合する電極を形成し、
多層基板の表面から電極に達する凹部を形成し、電極上
に半田を塗布し、更に、多層基板表面の凹部以外の半導
体装置接合部位に封止用樹脂を予め塗布し、バンプを凹
部に嵌合させて電極と突接させ、リフローにより電極上
の半田を溶融させてバンプと電極とを接合するととも
に、封止用樹脂を硬化させて半導体装置を多層基板に実
装しているので、封止用樹脂の注入工程がなくなり、封
止用樹脂内の気泡の発生を解消することができ、半導体
装置の信頼性が向上するという効果がある。また、凹部
に塗布された半田の厚みによって、実装時の半導体装置
の高さのバラツキを低減できるので、半導体装置の歩留
りが良くなるという効果もある。 According to the first aspect of the present invention, when a semiconductor device having a bump formed on a lower surface is mounted on a multilayer substrate as described above, an electrode is formed on an inner layer of the multilayer substrate so as to be bonded to the bump.
Forming a recess from the surface of the multilayer substrate reaching the electrode, the solder is coated on the electrodes, further, previously coated with a sealing resin in the semiconductor device bonding sites other than the concave portion of the multi-layer substrate surface, concave bumps
Since the semiconductor device is mounted on the multilayer board by fitting the bumps and the electrodes, making the solder on the electrodes melt by reflow, joining the bumps and the electrodes, and curing the sealing resin. In addition, the step of injecting the sealing resin is eliminated, and the generation of air bubbles in the sealing resin can be eliminated, which has the effect of improving the reliability of the semiconductor device. Also, concave
The semiconductor device at the time of mounting depends on the thickness of the solder applied to the
Semiconductor device yields can be reduced,
This also has the effect of improving the performance.
【００１３】請求項２の発明は、表面に内層基板の一部
を露出させる凹部が形成された多層基板と、多層基板に
設けた凹部と対向する部位にバンプが設けられた半導体
装置と、凹部の底部に露出する内層基板の部位に設けら
れ半田によりバンプに接合される電極と、多層基板表面
の凹部以外の部位に塗布され、多層基板と半導体装置と
の間の隙間を封止する封止用樹脂とを備えているので、
接合後の封止用樹脂の注入工程がなくなり、封止用樹脂
中の気泡の発生を解消したフリップチップ実装構造を実
現できるという効果がある。また、凹部に塗布された半
田の厚みによって、実装時の半導体装置の高さのバラツ
キを低減できるので、半導体装置の歩留りが良くなると
いう効果もある。 According to a second aspect of the present invention, a part of the inner substrate is provided on the surface.
And a multilayer substrate with a concave portion that exposes
Semiconductor with bumps provided on the part facing the provided recess
Device and the inner substrate exposed at the bottom of the recess.
The electrodes that are joined to the bumps by soldering and the surface of the multilayer substrate
Of the multilayer substrate and the semiconductor device
And sealing resin for sealing the gap between
There is no need to inject the sealing resin after joining,
A flip-chip mounting structure that eliminates air bubbles inside
It has the effect of being able to appear. Also, the half coated on the concave portion
Variations in height of the semiconductor device during mounting due to the thickness of the field
The yield of semiconductor devices can be improved.
There is also an effect.
【図１】（ａ）本発明の実施形態の多層基板を示す断面
図である。 （ｂ）同上の半田塗布工程を示す断面図である。 （ｃ）同上の封止用樹脂塗布工程を示す断面図である。 （ｄ）同上の半導体装置を示す断面図である。 （ｅ）同上のバンプ接合工程を示す断面図である。 （ｆ）同上のリフロー工程を示す断面図である。FIG. 1A is a cross-sectional view illustrating a multilayer substrate according to an embodiment of the present invention. (B) It is sectional drawing which shows the solder application process same as the above. (C) It is sectional drawing which shows the sealing resin application process same as the above. FIG. 3D is a cross-sectional view illustrating the same semiconductor device. (E) It is sectional drawing which shows the bump joining process same as the above. (F) It is sectional drawing which shows the reflow process same as the above.
【図２】同上の多層基板を示す断面図である。FIG. 2 is a cross-sectional view showing the multilayer substrate of the above.
【図３】同上の実装状態を示す断面図である。FIG. 3 is a cross-sectional view showing a mounting state of the same.
【図４】（ａ）従来例の半導体装置を示す断面図であ
る。 （ｂ）同上のバンプ接合工程を示す断面図である。 （ｃ）同上の封止用樹脂注入工程を示す断面図である。FIG. 4A is a cross-sectional view illustrating a conventional semiconductor device. (B) It is sectional drawing which shows the bump joining process same as the above. (C) is a sectional view showing a sealing resin injection step of the above.
１ 多層基板 ２ 電極 ３ 凹部 ４ クリーム半田 ５ 半導体装置 ６ バンプ ７ 封止用樹脂 REFERENCE SIGNS LIST 1 multilayer substrate 2 electrode 3 concave portion 4 cream solder 5 semiconductor device 6 bump 7 sealing resin
Claims (2)
層基板に実装する際、前記多層基板の内層に前記バンプ
と接合する電極を形成し、前記多層基板の表面から前記
電極に達する凹部を形成し、前記電極上に半田を塗布
し、更に、前記多層基板表面の前記凹部以外の前記半導
体装置接合部位に封止用樹脂を予め塗布し、前記バンプ
を前記凹部に嵌合させて前記電極と突接させ、リフロー
により前記電極上の前記半田を溶融させて前記バンプと
前記電極とを接合するとともに、前記封止用樹脂を硬化
させて前記半導体装置を前記多層基板に実装したことを
特徴とするフリップチップ実装方法。1. A multi-semiconductor device which bumps are formed on the lower surface
When implementing the layer substrate, wherein forming the electrode for bonding the bump to the inner layer of the multilayer substrate, wherein the surface of said multilayer substrate
A recess reaching the electrode, the solder is coated on the electrode, further, the pre-coated with a sealing resin in the semiconductor device bonding portion other than the concave portion of the multi-layer substrate surface, fitting the bumps in the recess The bumps and the electrodes are joined by melting the solder on the electrodes by reflow, and the sealing resin is cured so that the semiconductor device is bonded to the multilayer substrate. A flip chip mounting method characterized by being mounted.
形成された多層基板と、前記多層基板に設けた前記凹部
と対向する部位にバンプが設けられた半導体装置と、前
記凹部の底部に露出する前記内層基板の部位に設けられ
半田により前記バンプに接合される電極と、前記多層基
板表面の前記凹部以外の部位に塗布され、前記多層基板
と前記半導体装置との間の隙間を封止する封止用樹脂と
を備えて成ることを特徴とするフリップチップ実装構
造。2. A recess for exposing a part of the inner substrate on the surface.
The formed multilayer substrate and the concave portion provided in the multilayer substrate
A semiconductor device in which a bump is provided at a portion facing
Provided at a portion of the inner layer substrate exposed at the bottom of the recess.
An electrode joined to the bump by solder;
The multi-layer substrate is applied to a portion of the board surface other than the concave portion,
And a sealing resin for sealing a gap between the semiconductor device and
Flip-chip mounting structure characterized by comprising:
Build .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26601595A JP3176028B2 (en) | 1995-10-13 | 1995-10-13 | Flip chip mounting method and flip chip mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26601595A JP3176028B2 (en) | 1995-10-13 | 1995-10-13 | Flip chip mounting method and flip chip mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09115954A JPH09115954A (en) | 1997-05-02 |
| JP3176028B2 true JP3176028B2 (en) | 2001-06-11 |
Family
ID=17425198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26601595A Expired - Fee Related JP3176028B2 (en) | 1995-10-13 | 1995-10-13 | Flip chip mounting method and flip chip mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3176028B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11056423B2 (en) | 2018-05-22 | 2021-07-06 | Murata Manufacturing Co., Ltd. | Semiconductor device |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3733777B2 (en) * | 1999-03-15 | 2006-01-11 | セイコーエプソン株式会社 | IC chip mounting system and IC chip mounting method |
| KR100460048B1 (en) * | 2002-02-06 | 2004-12-04 | 주식회사 칩팩코리아 | Bump chip carrier package and method for fabricating the same |
| JP4489411B2 (en) | 2003-01-23 | 2010-06-23 | 新光電気工業株式会社 | Manufacturing method of electronic component mounting structure |
| KR100699874B1 (en) * | 2005-11-08 | 2007-03-28 | 삼성전자주식회사 | BGA package having embedded solder ball and method ofthe same and board mounted the same |
| JP2008124107A (en) * | 2006-11-09 | 2008-05-29 | Fujitsu Ltd | Wiring board, semiconductor part and manufacturing method for wiring board |
| JP2010103344A (en) * | 2008-10-24 | 2010-05-06 | Hakodate Electronics Co Ltd | Wiring board and method of manufacturing same |
| CN102922076B (en) * | 2012-11-05 | 2015-07-15 | 大恒新纪元科技股份有限公司 | Lens welding device and welding method for using same |
| CN111052584B (en) * | 2017-08-30 | 2023-07-11 | 日立安斯泰莫株式会社 | Power semiconductor device and method for manufacturing the same |
-
1995
- 1995-10-13 JP JP26601595A patent/JP3176028B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11056423B2 (en) | 2018-05-22 | 2021-07-06 | Murata Manufacturing Co., Ltd. | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09115954A (en) | 1997-05-02 |
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