JP3331304B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to SOI (Sili)
The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor element is formed on a substrate having a con-on-insulator (hereinafter, referred to as "SOI substrate").

[0002]

2. Description of the Related Art A process for forming a CMOS on a conventional SOI substrate shown in FIGS.

First, the surface silicon 101 for forming a transistor of an SOI substrate is oxidized, and the film thickness is adjusted to about 70 nm by etching or the like. The thickness of the buried oxide film 102 on the supporting substrate 103 is about 100 nm (FIG. 8).
(A)).

Next, the oxide film 104 is removed by thermal oxidation.
0 nm, a 100 nm thick SiN film (not shown) is formed by the LPCVD method, and the SiN film and the oxide film 1 in the element isolation region are formed by the photolithography method and the dry etching method.
04 is removed. Subsequently, thermal oxidation is performed at 160 nm to form a field oxide film 105 for element isolation, and the SiN film is removed with hot phosphoric acid (FIG. 8B).

Next, phosphorus is implanted into the PMOS active region by photolithography and ion implantation at an energy of 25 ke.
V ions are implanted at a dose of 5 × 10 ¹² ions / cm ² to determine the impurity concentration of the PMOS channel region 106. Subsequently, boron is implanted into the NMOS active region by photolithography and ion implantation at an energy of 30 k.
Ion implantation is performed at eV and a dose of 5 × 10 ¹² ions / cm ² to determine the impurity concentration of the NMOS channel region 107. Thereafter, the oxide film 104 is removed by 1% HF, and a gate oxide film 108 is formed to a thickness of 7 nm by a thermal oxidation method.

Next, a polysilicon film 109 is formed to a thickness of 150 nm by LPCVD, and phosphorus is implanted at an energy of 20 keV and a dose of 5 by ion implantation.
Ions are implanted into the polysilicon film 109 at × 10 ¹⁵ ions / cm ² , and the WSi film 110 is
0 nm is formed. Then, the WSi film 110 and the polysilicon film 10 are formed by photolithography and dry etching.
9 to form a gate electrode (FIG. 8
(C)).

BF ₂ is implanted into the PMOS active region by photolithography and ion implantation at an energy of 20 ke.
V ions are implanted at a dose of 5 × 10 ¹³ ions / cm ² to determine impurities in the drain buffer diffusion layer 111 of the PMOS. Subsequently, phosphorus is implanted into the NMOS active region by photolithography and ion implantation at an energy of 15 ke.
V ions are implanted at a dose of 5 × 10 ¹³ ions / cm ² to determine the impurity concentration of the drain buffer diffusion layer 112 of the NMOS. Subsequently, an oxide film (not shown) is formed by CVD.
Then, an oxide film is etched back by 140 nm by dry etching to form a sidewall 113 of the oxide film on the side wall of the gate electrode.

Next, BF ₂ is implanted into the PMOS active region by photolithography and ion implantation at an energy of 20 k.
Ion implantation is performed at eV and a dose of 5 × 10 ¹⁵ ions / cm ² to determine the impurity concentration of the source / drain diffusion layer 114 of the PMOS. Subsequently, phosphorus is implanted into the NMOS active region by photolithography and ion implantation at an energy of ¹⁵ keV and a dose of 5 × 10 ¹⁵ ions / cm ^2.
The source / drain diffusion layer 11 of the NMOS
5 is determined (FIG. 8D).

Next, the NSG film 116 is
Then, a BPSG film 117 is formed to a thickness of 750 nm by a CVD method. Thereafter, heat treatment is performed at 900 ° C. in a nitrogen atmosphere for 20 minutes to reflow the BPSG film 117 and activate the impurities implanted in the above steps. Thereafter, a resist 118 having an opening 119 serving as a contact hole for connecting the semiconductor element and the electrode wiring is formed by a photolithography method (FIG. 8E).

Next, contact holes 120 are formed in the BPSG film 117 and the NSG film 116 by dry etching using the resist 118 as a mask. The etching apparatus is an inductively coupled plasma etching apparatus, and a high frequency is also applied to a wafer holding electrode. Etching conditions are C ₂ F ₆
, A flow rate of 50 sccm, a degree of vacuum of 5 mTorr, a source applied power of 2500 W, and a wafer holding electrode applied power of 80
At 0 W, the overetch amount is 30% of the deepest source / drain contact portion (FIG. 9A).

Next, a Ti film is formed by sputtering to a thickness of 60 n.
m, and then a TiN film is formed to a thickness of 60 n by sputtering.
m, and a barrier metal film 121 is formed. Next, C
A tungsten film 122 is formed to a thickness of 500 nm by the VD method, and the tungsten film 122 is etched back by dry etching, leaving the tungsten 22 only in the contact hole 120.

Next, the barrier metal film 121 is etched back by dry etching to leave the barrier metal film 121 only in the contact hole 120. Next, by sputtering, the TiN film 123 is 80 nm, the AlCu film 124 (Cu concentration 0.5%) is 400 nm, and the TiN film 1 is formed.
25 is formed to a thickness of 80 nm. Thereafter, the TiN film 123, the AlCu film 124, and the TiN film 125 are etched by a photolithography method and a dry etching method to form an electrode wiring (FIG. 9B).

Next, P-Si is formed by plasma CVD.
An O ₂ film 126 is formed to a thickness of 2 μm.
The surface of the P-SiO ₂ film 126 is flattened. The thickness of the P-SiO ₂ film 126 after the CMP is set to 1 μm on the electrode wiring. A resist 127 having an opening in a region 128 serving as a via hole connecting the electrode wiring and the upper electrode wiring is formed by a photolithography method (FIG. 9C).

Next, via holes 129 are formed in the P-SiO ₂ film 126 by dry etching using the resist 127 as a mask. The etching apparatus is an inductively coupled plasma etching apparatus and applies a high frequency to a wafer holding electrode. The etching condition is such that the flow rate of C ₂ F ₆ is 50 scc.
m, the degree of vacuum is 5 mTorr, and the power applied to the source is 2500.
W, the power applied to the wafer holding electrode is 800 W, and the overetch amount is 50% (FIG. 10A).

A Ti film is formed to a thickness of 60 nm by sputtering, and a TiN film is formed to a thickness of 60 nm by sputtering to form a barrier metal film. Next, a tungsten film 131 is formed to a thickness of 500 nm by a CVD method, and the tungsten film 131 is etched back by a dry etch method.
Leave.

Next, the barrier metal film 130 is etched back by the dry etching method, and the barrier metal film 130 is left only in the via hole 129. Next, Ti
The N film 132 is formed to 80 nm, the AlCu film 133 (Cu concentration 0.5%) is formed to 800 nm, and the TiN film 134 is formed to 80 nm. Thereafter, the TiN film 134, the AlCu film 133, and the TiN film 132 are etched by a photolithography method and a dry etching method to form an upper electrode wiring. Thereafter, the passivation film Si is formed by plasma CVD.
An N film 135 is formed to a thickness of 600 nm. Thereafter, bonding pad connection holes (not shown) are opened in the P-SiN film 135 by a photolithography method and a dry etching method (FIG. 10B).

[0017]

In a method of manufacturing an LSI which is being miniaturized, a contact hole for connecting a semiconductor element and an electrode wiring and a via hole for connecting an upper electrode wiring and a lower electrode wiring are formed by dry etching. Process. In the dry etching, the positive and negative charges on the side wall of the hole become uneven, and as a result, the charge on the bottom of the contact hole also becomes uneven. The tendency becomes remarkable as miniaturization progresses. In the case of a device formed on an SOI substrate, when the bottom of the contact hole is charged, a potential is generated between the active region and the support substrate, and the embedded oxide film therebetween is deteriorated. LSI for deterioration of the buried oxide film
Reliability and yield are reduced.

[0018]

According to a method of manufacturing a semiconductor device of the present invention, there is provided a method of manufacturing a semiconductor device having a semiconductor element formed on an SOI substrate, wherein the semiconductor element is formed on the semiconductor element or on an electrode wiring connecting the semiconductor element. After forming an interlayer insulating film on the interlayer insulating film, and then forming a conductive film on the interlayer insulating film, dry etching is performed on the interlayer insulating film to form the semiconductor element or a contact used for electrical connection with an electrode wiring connecting the semiconductor element. to form a hole or via hole, the
Thereafter, the conductive film is removed, and then a conductive contact plug is buried in the contact hole or via hole via a barrier metal.

[0019]

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

FIGS. 1 to 3 are views showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention, and FIGS.
FIG. 9 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention. 1 to 7, 1 is a surface silicon layer, 2 is a buried oxide film, 3 is a support substrate, 4 is an oxide film, 5 is a field oxide film, 6 is a PMOS channel region, 7 is an NMOS channel region, 8 Is the gate oxide film,
9 is a polysilicon film, 10 is a WSi film, 11 is a PMOS film
, A drain buffer diffusion layer 12 of an NMOS, a sidewall 13, a source / drain diffusion layer 14 of a PMOS, an NMOS source / drain diffusion layer 15, an NSG film 16, a BPSG film 17, 18,
27 is a resist, 19 is a region to be a contact hole, 20 is a contact hole, 21, 30 is a barrier metal film, 22, 31 is a tungsten film, 23, 25, 3
2, 34 are TiN films, 24, 33 are AlCu films, 26 is a P-SiO ₂ film, 28 is a region to be a via hole, 29
Is a via hole, 35 is a SiN film, 36, 37, 3
Reference numerals 8 and 39 denote conductive films for reducing charge-up generated in the contact holes by dry etching used when forming the contact holes.

The conductive films 36, 37, 38 and 39 are made of Ti.
The conductive film is not limited to N, and may be any conductive film that can be removed in a later step. For example, Ti, TiW, W, WSi,
WSi ₄ , Al, Al alloy, polysilicon and the like are applicable. The formation method is not limited to the sputtering method, but may be a CVD method, a vapor deposition method, or the like. The thickness is not particularly limited, but is preferably 10 to 300 nm, particularly preferably 15 to 150 nm, in consideration of removal in a later step, stability of a formed film, and the like.

The manufacturing process of the semiconductor device according to the first embodiment of the present invention will be described below with reference to FIGS.

First, the surface silicon layer 1 for forming the transistor of the SOI substrate is oxidized, and its thickness is adjusted to about 70 nm by etching or the like. The thickness of the buried oxide film 2 on the support substrate 3 is about 100 nm (FIG. 1A).

Next, the oxide film 4 is formed to a thickness of 10 n by a thermal oxidation method.
m, and a SiN film (not shown) by the LPCVD method.
Is formed to a thickness of 100 nm, and the SiN film in the element isolation region and the natural oxide film formed on the surface are removed by photolithography and dry etching. Subsequently, thermal oxidation was performed for 160 n.
Then, a field oxide film 5 for element isolation is formed, and the SiN film is removed by hot phosphoric acid (FIG. 1B).

Next, phosphorus is implanted into the PMOS active region by photolithography and ion implantation at an energy of 25 ke.
V ions are implanted at a dose of 5 × 10 ¹² ions / cm ² to determine the impurity concentration of the PMOS channel region 6. Subsequently, boron is implanted into the NMOS active region by photolithography and ion implantation at an energy of 30 ke.
V ions are implanted at a dose of 5 × 10 ¹² ions / cm ² to determine the impurity concentration of the NMOS channel region 6. Thereafter, the oxide film 4 is removed by 1% HF, and a gate oxide film 8 is formed to a thickness of 7 nm by a thermal oxidation method.

Next, a polysilicon film 9 is formed to a thickness of 150 nm by LPCVD, phosphorus is implanted at an energy of 20 keV and a dose is 5 × 10 5 by ion implantation.
Ions are implanted into the polysilicon film 9 at ¹⁵ ions / cm ² , and a WSi film 10 is formed to a thickness of 100 nm by a CVD method. Thereafter, the WSi film 10 and the polysilicon film 9 are etched by a photolithography method and a dry etching method to form a gate electrode (FIG. 1C).

BF ₂ is implanted into the PMOS active region by photolithography and ion implantation at an energy of 20 ke.
V ions are implanted at a dose of 5 × 10 ¹³ ions / cm ² to determine impurities in the drain buffer diffusion layer 11 of the PMOS. Subsequently, phosphorus is implanted into the NMOS active region by photolithography and ion implantation at an energy of 15 ke.
V ions are implanted at a dose of 5 × 10 ¹³ ions / cm ² to determine the impurity concentration of the NMOS drain buffer diffusion layer 12.

Subsequently, an oxide film (not shown) is formed to a thickness of 150 nm by a CVD method, and is formed by a dry etching method.
The oxide film is etched back by 140 nm to form a sidewall 13 of the oxide film on the side wall of the gate electrode. Next, PMO
BF in the S active region by photolithography and ion implantation
₂ with an implantation energy of 20 keV and a dose of 5 × 10
Ions are implanted at ¹⁵ ions / cm ² to determine the impurity concentration of the source / drain diffusion layers 14 of the PMOS. Subsequently, phosphorus is ion-implanted into the NMOS active region by photolithography and ion implantation at an energy of ¹⁵ keV and a dose of 5 × 10 ¹⁵ ions / cm ^2.
The impurity concentration of the source / drain diffusion layer 15 is determined (FIG. 1D).

Next, an NSG film 16 is formed
Then, a BPSG film 17 is formed to a thickness of 750 nm by the CVD method. Thereafter, at 900 ° C. in a nitrogen atmosphere,
A heat treatment for 20 minutes is performed to reflow the BPSG film 17 and activate the impurities implanted in the above steps.

Thereafter, a 25 nm thick TiN film is formed as a charge-up reducing conductive film 36 by a sputtering method.
After that, a resist 18 is formed by photolithography with an opening in a region 19 serving as a contact hole for connecting the semiconductor element and the electrode wiring (FIG. 1E).

Next, the TiN film 36 is etched by dry etching using the resist 18 as a mask. The etching apparatus was a parallel plate type plasma etching apparatus. The etching conditions were as follows: SF ₆ flow rate was 50 sccm, and the degree of vacuum was 1
50 mTorr, the power applied to the electrode is 300 W, and the overetch amount is 30% with respect to the TiN film thickness.

Thereafter, contact holes 20 are formed in the BPSG film 17 and the NSG film 16 by dry etching using the resist 18 as a mask. The etching apparatus is an inductively coupled plasma etching apparatus, and a high frequency is also applied to a wafer holding electrode. The etching conditions were a flow rate of C ₂ F ₆ of 50 sccm, a degree of vacuum of 5 mTorr, a power applied to the source of 2500 W, and a power applied to the wafer holding electrode at 800 W.
The overetch amount is set to 30% with respect to the deepest source / drain contact portion (FIG. 2A).

Thereafter, the resist 18 is removed by a plasma ashing method, and the TiN film 36 is entirely removed by immersion in a mixed solution of sulfuric acid and hydrogen peroxide at 150 ° C. If the TiN film 36 does not remain between the wiring layers, that is, if the wiring is not conducted, it is not necessary to remove all of the TiN film 36, but removing the TiN film 36 can reduce the aspect ratio. This is the same in the second embodiment.

Thereafter, a Ti film is formed by sputtering to a thickness of 60
Next, a TiN film is formed by sputtering to a thickness of 60 nm.
The barrier metal film 21 is formed. Note that the barrier metal film 21 is not limited to the two-layer structure,
It is possible to use only the Ti film or only the TiN film.

Next, the tungsten film 22 is formed by the CVD method.
The tungsten film 22 is etched back by dry etching to form a contact hole 20.
Only the tungsten film 22 is left. Next, the barrier metal film 21 is etched back by a dry etching method,
The barrier metal 21 is left only in the contact hole 20. Next, 80n of the TiN film 23 is formed by a sputtering method.
m, the AlCu film 24 (Cu concentration 0.5%) is 400 n
An 80 nm thick TiN film 25 is formed. After that, the TiN film 23,
The AlCu film 24 and the TiN film 25 are etched to form an electrode wiring (FIG. 2B).

Next, P-Si is formed by plasma CVD.
An O ₂ film 26 is formed to a thickness of 2 μm.
To flatten the surface of the -SiO ₂ film 26. P- after CMP
The thickness of the SiO ₂ film 26 is 1 μm on the electrode wiring.

Next, a 25 nm-thick TiN film is formed as the charge-up reducing conductive film 37 by a sputtering method. Thereafter, a resist 27 having an opening in a region 28 serving as a via hole connecting the electrode wiring and the upper electrode wiring is formed by a photolithography method (FIG. 2C).

Next, using the resist 27 as a mask, the TiN film 37 is etched by dry etching. The etching apparatus is a parallel plate type plasma etching apparatus, and the etching conditions are SF ₆ flow rate 50 sccm, vacuum degree 150 m.
At Torr, the electrode applied power is 300 W, and the overetch amount is 30% with respect to the TiN film thickness. Thereafter, P-SiO _{2 is formed} by dry etching using the resist 27 as a mask.
A via hole 29 is opened in 26. The etching apparatus is an inductively coupled plasma etching apparatus and applies a high frequency to a wafer holding electrode. The etching conditions were a flow rate of C ₂ F ₆ of 50 sccm, a degree of vacuum of 5 mTorr, a power applied to the source of 2500 W, and a power applied to the wafer holding electrode of 800 W.
And the overetch amount is 50% (FIG. 3
(A)).

Next, a Ti film was formed to a thickness of 60 nm by sputtering.
Then, a TiN film is formed to a thickness of 60 nm by a sputtering method, and a barrier metal film 30 is formed. Next, a tungsten film 31 is formed to a thickness of 500 nm by the CVD method, and the tungsten film 31 is etched back by the dry etching method, leaving the tungsten film 31 only in the via hole 29.

Next, the TiN film 37 is formed by dry etching.
Then, the barrier metal film 30 is etched back to leave the barrier metal film 30 only in the via hole portion 29. Next, the TiN film 32 is formed to a thickness of 80 nm, the AlCu 33 (Cu concentration: 0.5%) is formed to a thickness of 800 nm, and the TiN film is formed to a thickness of 80 nm by sputtering. Thereafter, the TiN film 34, the AlCu film 33, and the TiN film 32 are formed by photolithography and dry etching.
Is etched to form an upper electrode wiring. Thereafter, a SiN film 3 as a passivation film is formed by a plasma CVD method.
5 is formed to a thickness of 600 nm. Then, the bonding pad connection hole is formed by P-lithography and dry etching.
An opening is formed in the SiN film 35 (FIG. 3B).

Next, a method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS.

First, the surface silicon 1 for forming the transistor of the SOI substrate is oxidized, and the film thickness is adjusted to about 70 nm by etching or the like. The thickness of the buried oxide film 2 on the support substrate 3 is about 100 nm (FIG. 4A).

Next, the oxide film 4 is formed to a thickness of 10 n by a thermal oxidation method.
m, an SiN film is formed to a thickness of 100 nm by LPCVD, and the SiN film and oxide film in the element isolation region are removed by photolithography and dry etching. Subsequently, thermal oxidation is performed at 160 nm to form an oxide film 5 for element isolation, and the SiN film is removed with hot phosphoric acid (FIG. 4).
(B)).

Next, phosphorus is implanted into the PMOS active region by photolithography and ion implantation at an energy of 25 ke.
V ions are implanted at a dose of 5 × 10 ¹² ions / cm ² to determine the impurity concentration of the PMOS channel region 6. Subsequently, boron is implanted into the NMOS active region by photolithography and ion implantation at an energy of 30 ke.
V ions are implanted at a dose of 5 × 10 ¹² ions / cm ² to determine the impurity concentration of the NMOS channel region 6. Thereafter, the oxide film 4 is removed by 1% HF, and a gate oxide film 8 is formed to a thickness of 7 nm by a thermal oxidation method.

Next, a polysilicon film 9 having a thickness of 150 nm is formed by the LPCVD method, and the polysilicon film 9 is formed by the ion implantation method.
Phosphorus implantation energy 20 keV, dose 5 × 1
Ions are implanted into the polysilicon film 9 at 0 ¹⁵ ions / cm ² , and a WSi film 10 is formed to a thickness of 100 nm by a CVD method. Thereafter, the WSi film 10 and the polysilicon film 9 are etched by a photolithography method and a dry etching method to form a gate electrode (FIG. 4C).

BF ₂ is implanted into the PMOS active region by photolithography and ion implantation at an energy of 20 ke.
V ions are implanted at a dose of 5 × 10 ¹³ ions / cm ² to determine impurities in the drain buffer diffusion layer 11 of the PMOS. Subsequently, phosphorus is implanted into the NMOS active region by photolithography and ion implantation at an energy of 15 ke.
V ions are implanted at a dose of 5 × 10 ¹³ ions / cm ² to determine the impurity concentration of the NMOS drain buffer diffusion layer 12. Subsequently, an oxide film (not shown) is formed to a thickness of 150 nm by a CVD method, and is formed by a dry etching method.
The oxide film is etched back by 140 nm to form a sidewall 13 of the oxide film on the side wall of the gate electrode.

Subsequently, BF ₂ is implanted into the PMOS active region by photolithography and ion implantation at an energy of 20.
Ion implantation is performed at a keV and a dose of 5 × 10 ¹⁵ ions / cm ² to determine the impurity concentration of the source / drain diffusion layer 14 of the PMOS. Subsequently, phosphorus is ion-implanted into the NMOS active region by photolithography and ion implantation at an implantation energy of ¹⁵ keV and a dose of 5 × 10 ¹⁵ ions / cm ² to determine the impurity concentration of the source / drain diffusion layer 15 of the NMOS ( FIG. 4D).

Next, the NSG film 16 is
Then, a BPSG film 17 is formed to a thickness of 750 nm by the CVD method. Thereafter, at 900 ° C. in a nitrogen atmosphere,
A heat treatment for 20 minutes is performed to reflow BPSG and activate the impurities implanted in the above steps. Thereafter, TiN is used as the charge-up reducing conductive film 38 by sputtering.
A film is formed to a thickness of 25 nm. Thereafter, a resist 18 is formed by photolithography with an opening in a region 19 serving as a contact hole for connecting the semiconductor element and the electrode wiring (FIG. 4).
(E)).

Next, using the resist 18 as a mask, the TiN film 38 is etched by dry etching. The etching apparatus is a parallel plate type plasma etching apparatus, and the etching conditions are SF ₆ flow rate 50 sccm, vacuum degree 150 m.
At Torr, the electrode applied power is 300 W, and the overetch amount is 30% with respect to the TiN film thickness.

After that, the resist 18 is removed by a plasma ashing method. Thereafter, the BPSG film 17 and the NSG film 16 are dry-etched using the TiN film 38 as a mask.
Then, a contact hole portion 20 is formed. The etching apparatus is an inductively coupled plasma etching apparatus, and a high frequency is also applied to a wafer holding electrode. Etching conditions are C ₂ F ₆
, A flow rate of 50 sccm, a degree of vacuum of 5 mTorr, a source applied power of 2500 W, and a wafer holding electrode applied power of 80
At 0 W, the overetch amount is 30% of the deepest source / drain contact portion (FIG. 5A).

Thereafter, the TiN film 38 is entirely removed by immersion in a mixed solution of sulfuric acid and hydrogen peroxide at 150 ° C. Incidentally, it is not necessary to remove all of them like the TiN film 36 described above.

Thereafter, a Ti film is formed by sputtering to a thickness of 60
Next, a TiN film is formed by sputtering to a thickness of 60 nm.
The barrier metal film 21 is formed. Next, C
A tungsten film 22 is formed to a thickness of 500 nm by a VD method,
The tungsten film 22 is etched back by dry etching, leaving the tungsten film 22 only in the contact hole portion 20. Next, the barrier metal film 21 is etched back by a dry etching
The barrier metal film 21 is left only at 0 (FIG. 5B).

Next, the TiN film 23 was formed to 80 nm, and the AlCu film 24 (Cu concentration 0.5%) was formed to 40 nm by sputtering.
A TiN film 25 is formed to a thickness of 0 nm and a thickness of 80 nm. Thereafter, the TiN film 2 is formed by photolithography and dry etching.
3. The AlCu film 24 and the TiN film 25 are etched to form an electrode wiring (FIG. 5C).

Next, P-Si is formed by plasma CVD.
An O ₂ film 26 is formed to a thickness of 2 μm.
To flatten the surface of the -SiO ₂ film 26. P- after CMP
The thickness of the SiO ₂ film 26 is 1 μm on the electrode wiring.

Next, a 25 nm-thick TiN film is formed as a charge-up reducing conductive film 39 by a sputtering method.
Thereafter, a resist 27 having an opening in a region 28 serving as a via hole connecting the electrode wiring and the upper electrode wiring is formed by a photolithography method (FIG. 6A).

Next, using the resist 27 as a mask, the TiN film 39 is etched by dry etching. The etching apparatus was a parallel plate type plasma etching apparatus, and the etching conditions were SF ₆ flow rate 50 sccm, and the degree of vacuum was 150.
mTorr, the power applied to the electrode is 300 W, and the overetch amount is 30% with respect to the TiN film thickness. Thereafter, the resist 27 is removed by a plasma ashing method, and subsequently, the PN is removed by dry etching using the TiN film 39 as a mask.
Opening a via hole 29 in the SiO ₂ film 26; The etching apparatus is an inductively coupled plasma etching apparatus and applies a high frequency to a wafer holding electrode. The etching conditions were as follows: the flow rate of C ₂ F ₆ was 50 sccm, and the vacuum degree was 5 mTorr.
r, the power applied to the source is 2500 W, the power applied to the wafer holding electrode is 800 W, and the overetch amount is 50% (FIG. 6B).

Next, 60 nm of Ti is formed by a sputtering method, and then 60 nm of TiN is formed by a sputtering method to form a barrier metal 30. Next, tungsten 31 is formed to a thickness of 500 nm by the CVD method, and the tungsten 31 is etched back by the dry etching method, leaving the tungsten 31 only in the via hole 29 (FIG. 7).
(A)).

Next, a TiN film 39 is formed by dry etching.
Then, the barrier metal film 30 is etched back to leave the barrier metal film 30 only in the via hole portion 29. Next, 80 nm of TiN film 32 and AlCu film 33 (Cu
(Concentration 0.5%) 800 nm, TiN film 34 80 nm
Form. Thereafter, the TiN film 34, the AlCu film 33, and the TiN film 3 are formed by photolithography and dry etching.
2 is etched to form an upper electrode wiring. Thereafter, a SiN film 35 as a passivation film is formed to a thickness of 600 nm by a plasma CVD method. Then, the bonding pad connection hole is formed by photolithography and dry etching.
An opening is formed in the SiN film 35 (FIG. 7B).

Further, as shown in FIGS. 11 to 13, the initial breakdown of the buried oxide film at a breakdown voltage of 1 MV / cm or less is 52% in the conventional manufacturing method, whereas in the first embodiment, The method using the manufacturing method shown in FIG. 8 is greatly reduced to 8%, and the method using the manufacturing method shown in the second embodiment is greatly reduced to 10%. By using the present invention, the deterioration of the buried oxide film is reduced. Has been reduced.

FIG. 11 is a diagram showing the breakdown voltage distribution of the buried oxide film when the manufacturing method shown in the first embodiment is used, and FIG. 12 is a diagram showing the use of the manufacturing method shown in the second embodiment. FIG. 4 is a diagram showing a breakdown voltage distribution of a buried oxide film when the
FIG. 13 is a diagram showing the breakdown voltage distribution of the buried oxide film when the manufacturing method according to the prior art is used.

[0062]

As described above in detail, by using the present invention, it is possible to form a conductive layer on an interlayer insulating film by causing a charge generated on a side wall of a contact hole during dry etching for forming a contact hole. Can be alleviated. As a result, the charge in the active region at the bottom of the contact hole is also reduced, the potential between the active region and the support substrate is reduced, and the deterioration of the buried oxide film can be prevented.

When the charge-up reducing conductive film and the barrier metal are made of the same material, or when there are a plurality of barrier metals, if the conductive film is one of them, the barrier metal is etched back or the wiring is formed. Since the conductive film can be removed at the same time as the etching, the number of steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a manufacturing process diagram of the semiconductor device according to the second embodiment of the present invention;

FIG. 5 is a manufacturing process diagram of the semiconductor device according to the second embodiment of the present invention.

FIG. 6 is a manufacturing process diagram of the semiconductor device according to the second embodiment of the present invention.

FIG. 7 is a manufacturing process diagram of the semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a view showing a step of forming a semiconductor element on an SOI substrate in a conventional technique.

FIG. 9 is a view showing a step of forming a semiconductor element on an SOI substrate in a conventional technique.

FIG. 10 is a view showing a step of forming a semiconductor element on an SOI substrate in a conventional technique.

FIG. 11 is a diagram showing a breakdown voltage distribution of a buried oxide film when the manufacturing method shown in the first embodiment is used.

FIG. 12 is a diagram showing a breakdown voltage distribution of a buried oxide film when the manufacturing method described in the second embodiment is used.

FIG. 13 is a diagram showing a breakdown voltage distribution of a buried oxide film when a manufacturing method according to a conventional technique is used.

[Explanation of symbols]

Reference Signs List 1 surface silicon layer 2 buried oxide film 3 support substrate 4 oxide film 5 field oxide film 6 PMOS channel region 7 NMOS channel region 8 gate oxide film 9 polysilicon film 10 WSi film 11 PMOS drain buffer diffusion layer 12 NMOS drain Buffer diffusion layer 13 Side wall 14 PMOS source / drain diffusion layer 15 NMOS source / drain diffusion layer 16 NSG film 17 BPSG film 18, 27 Resist 19 Contact hole portion region 20 Contact hole portion 21, 30 Barrier metal film 22 , 31 tungsten film 23,25,32,34 TiN film 24 and 33 AlCu film 26 P-SiO ₂ film 28 becomes the via hole region 29 via hole portion 35 SiN film 36, 37, 38, 39 charge-up reduction conductive

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-182927 (JP, A) JP-A-7-254574 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/28 H01L 21/336 H01L 21/768

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor device in which a semiconductor element is formed on an SOI substrate, wherein an interlayer insulating film is formed on the semiconductor element or on an electrode wiring connecting the semiconductor element, and then on the interlayer insulating film. After a conductive film is formed, a contact hole or a via hole used for electrical connection with the semiconductor element or the electrode wiring connecting the semiconductor element is formed in the interlayer insulating film by dry etching, and then the conductive film is formed. A method of manufacturing a semiconductor device, comprising: removing a conductive contact plug in a contact hole or a via hole via a barrier metal;