JP3277855B2 - Method for forming wiring of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring of a semiconductor device and a semiconductor device, and more particularly to a wiring forming method for connecting a lower conductive region and an upper wiring through a contact hole formed in an interlayer insulating film. The present invention relates to a method and a semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, a barrier metal layer is interposed at a contact portion between a semiconductor substrate and a wiring layer.
A technique for preventing a reaction between the two and obtaining stable electrical contact is known. As the barrier metal layer, a Ti layer and Ti
A technique using lamination with an ON layer has been proposed (see Japanese Patent Application Laid-Open No. 4-214653). The Ti layer reduces the contact resistance between the semiconductor substrate and the wiring layer, and the TiON layer prevents a reaction between the wiring layer and the semiconductor substrate.

Further, a Ti layer, a T layer,
TiO formed by oxidizing the surface of iN layer and TiN layer
A technique using an N-layer three-layer structure has been proposed (see JP-A-5-6865 and JP-A-5-121356).

[0004] In this specification, "TiON"
Does not mean that the composition ratio of “O” and “N” is 1: 1. Usually, TiON used as a barrier metal layer is TiO _x N _1-x (x is about 0.1)
It is. When the TiON layer is deposited by sputtering, x changes by changing the amount of O ₂ added during sputtering.

[0005]

When a two-layer structure of a Ti layer and a TiON layer is used as a barrier metal layer, Ti
Deposit a TiON layer on top of the layer. According to an experiment conducted by the inventors of the present application, it was difficult to stably obtain good electrical connection by this method.

SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring forming method and a semiconductor device in which a barrier metal layer and a buried plug are formed in a contact hole and a stable electric connection can be obtained.

[0007]

According to one aspect of the present invention, a step of depositing an interlayer insulating film on a semiconductor substrate and forming a contact hole in the interlayer insulating film; And depositing a Ti layer on the inner surface of the contact hole by sputtering in a first chamber, and transferring the semiconductor substrate on which the Ti layer is formed from the first chamber to the second chamber. Transferring, and depositing a first TiN layer in a substantially oxygen-free atmosphere on the surface of the Ti layer including the inside of the contact hole in the second chamber; Depositing a TiON layer on the first TiN layer; depositing a second TiN layer on the TiON layer;
Forming a buried plug on the surface of the second TiN layer in the contact hole; and forming a wiring connected to the buried plug on the interlayer insulating film A method for forming a wiring of a device is provided.

Since the atmosphere for depositing the first TiN layer on the surface of the Ti layer does not contain oxygen, oxidation of the surface of the Ti layer can be prevented. At the start of the deposition of the TiON layer, since the Ti layer is not exposed, oxidation of the surface of the Ti layer by an oxidizing atmosphere during deposition of the TiON layer is prevented.

When the embedded plug is formed, the surface of the TiON layer is covered with the second TiN layer. For this reason, TiO
Release of oxygen from the N layer is prevented, and adverse effects due to oxygen can be suppressed.

[0010]

[0011]

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing embodiments of the present invention,
The following describes the results of an experiment for evaluating the contact resistance of a wiring structure using a TiON layer as a barrier metal layer.

The n-type and p-type impurity diffusion regions and the wiring layer were connected to the surface of the silicon substrate via contact holes having a diameter of 0.45 μm and an aspect ratio of 1.8. P ⁺ ions are implanted into the n-type region so as to have a dose of 5 × 10 ¹⁵ cm ⁻² , and BF ₂ ⁺ ions are implanted into the p-type region so as to have a dose of 2 × 10 ¹⁵ cm ^−2. Then about 950 ° C
And heat treatment for activation was performed. On the bottom of the contact hole, a 20-nm thick Ti layer and a 100-nm thick T
An iON layer is laminated. The TiON layer was deposited by depositing a Ti layer by sputtering and then performing reactive sputtering by mixing O ₂ and N ₂ in a sputtering gas.

The contact resistance between the n-type region and the wiring layer is 55
Ω, the contact resistance between the p-type region and the wiring layer was 157 Ω, and both were non-ohmic contacts where the current was not proportional to the voltage.

The inventor of the present application failed to obtain good electrical contact because the interface between the Ti layer and the TiON layer was TiO 2.
It was considered that the layer was formed. In the example below,
The formation of the TiO layer can be prevented.

Furthermore, it has been found that when a TiON layer is used as a barrier metal layer and a contact hole is filled with a tungsten (W) plug, the following inconveniences are likely to occur.

FIG. 4 is a cross-sectional view of a W plug portion in a state where the inside of the contact hole is filled with the W plug. An interlayer insulating film 110 is formed on the surface of the silicon substrate 100,
A contact hole 111 is provided in the interlayer insulating film 110. A Ti layer 112 and a TiON layer 113 are formed on the surface of the interlayer insulating film 110 and the inner surface of the contact hole 111.
Are stacked in this order.

A W layer covering the entire region on the surface of the TiON layer 113 is deposited, and the W layer is etched back to leave a W plug 114b in the contact hole 111. FIG. 4 shows a portion 11 of the W layer 11 on a region other than the contact hole 111.
4a shows a state where a thin layer remains.

During the etch back of the W layer, the upper surface of the W plug 114b in the contact hole 111
In some cases, the plug loss becomes lower than the upper surface of the W layer 114a deposited on the O layer. In addition, in the region near the opening on the inner peripheral surface of the contact hole 111, T
A trench 116 that exposes the surface of the iON layer 113 is generated, or a seam 1 is formed at the center of the contact hole 111.
17 may also occur.

The generation of the plug loss 115, the trench 116, and the seam 117 is considered to be due to the rapid increase in the etching rate of the W layer due to the influence of oxygen released from the TiON layer 113. Plug loss 115, trench 11
6 and the seam 117 cause a rise in contact resistance. In the following embodiment, such a problem can be prevented from occurring.

Referring to FIGS. 1 to 3, a method for forming a wiring according to an embodiment of the present invention will be described in the case where a source / drain region of a metal-oxide-semiconductor field effect transistor (MOSFET) is connected to an upper wiring. Will be described as an example.

As shown in FIG. 1A, a silicon substrate 1
An active region is defined on the surface of the silicon substrate 1 by the field oxide film 2 formed on the surface of the substrate. In this active region, a MOSFET including a source region 3S, a drain region 3D, a gate insulating film 3I, and a gate electrode 3G is provided.
Are formed. Sidewall insulators 3W are formed on the sidewalls on both sides of the gate electrode 3G. The side wall insulator 3W is used as a mask at the time of ion implantation for forming a low concentration drain (LDD) structure.

As shown in FIG. 1B, chemical vapor deposition (CVD) is performed on the entire surface of the substrate so as to cover the MOSFET.
An approximately 0.8 μm thick interlayer insulating film 4 having a laminated structure of phosphosilicate glass (PSG) and borophosphosilicate glass (BPSG) is deposited. Contact holes 5S and 5D having a diameter of about 0.45 μm are formed in the interlayer insulating film 4, and a source region 3S and a drain region 3D are formed on the bottom surfaces of the contact holes 5S and 5D, respectively.
Expose part of the surface of the

As shown in FIG. 1C, a Ti layer 6a having a thickness of about 20 nm and a first T layer having a thickness of about 25 nm are formed on the surface of the interlayer insulating film 4 and on the inner surfaces of the contact holes 5S and 5D.
An iN layer 6b, a TiON layer 6c having a thickness of 50 to 75 nm, and a second TiN layer 6d having a thickness of about 25 nm are stacked in this order.

The Ti layer 6a is deposited by using Ar as a sputtering gas at a substrate temperature of 150 ° C. and an atmospheric pressure of 4 mT.
The sputtering is performed under the conditions of orr, a sputter gas flow rate of 15 sccm, and a film formation rate of about 100 nm / min. The first TiN layer 6b is deposited by using T
i, using a mixed gas of N ₂ and Ar as a sputtering gas,
Substrate temperature 150 ° C., atmospheric pressure 4 mTorr, Ar
Gas flow rate 40 sccm, N ₂ gas flow rate 85 scc
m, and a reactive sputtering is performed under the conditions of a film forming rate of about 75 nm / min. The deposition of the TiON layer 6c is performed in the first
After the TiN layer 6b is deposited, the Ar gas flow rate is set to 30 sccm.
To a mixed gas of Ar and N _{2 at} a flow rate of 10 sccm.
O ₂ gas is newly introduced, and reactive sputtering is performed using the same Ti target. Second TiN layer 6
The deposition of d is performed under the same conditions as the deposition conditions of the first TiN layer 6b by stopping the introduction of the O ₂ gas.

Although it is possible to continuously deposit the TiN layer 6a to the second TiN layer 6d in the same chamber, it is possible to deposit the Ti layer 6a and the first TiN layer 6b to the second TiN layer 6d. It is preferable to perform the deposition up to and including the deposition in a different chamber. By depositing the Ti layer 6a and the other three layers 6b to 6d in different chambers, the Ti layer 6a
Oxidation or nitridation of the surface of a Ti target for depositing GaN can be prevented. The transfer of the substrate from the chamber for depositing the Ti layer 6a to the chamber for depositing the first TiN layer 6b and the second TiN layer 6d is performed in a vacuum atmosphere or a non-oxidizing atmosphere without exposure to the air. It is preferable to carry out in. Thereby, surface oxidation of the Ti layer 6a can be prevented.

As shown in FIG. 2A, after a growth nucleus is formed on the surface of the second TiN layer 6d, a thickness, for example, 550 nm, sufficient to fill the insides of the contact holes 5S and 5D is formed. A W layer 7 is deposited by CVD. The growth nuclei are formed, for example, under the conditions of a pressure of 4 Torr and a substrate temperature of 430 ° C., SiH ₄ having a flow rate of 4 sccm and 7 to 20 scc.
m WF ₆ is supplied to the substrate surface for about 35 seconds. The W layer 7 is deposited, for example, at a flow rate of 80 as a source gas.
sccm WF ₆ , flow rate 720 sccm as reducing gas
Of H ₂ , a growth temperature of 450 ° C. and a pressure of 50 to 80
It is performed under the conditions of Torr and a deposition rate of 0.3 to 0.5 μm / min. The inside of the contact holes 5S and 5D is W
Filled by layer 7.

As shown in FIG. 2B, the W layer 7 is etched.
Back to areas other than contact holes 5S and 5D
All the deposited W layers 7 are removed. Etch back of W layer 7
For example, a plastic using electron cyclotron resonance
Zuma etching equipment (ECR plasma etching equipment)
And SF as an etching gas₆Using SF ₆
Gas flow rate 140 sccm, pressure 270 Pa, high frequency
About 200 W of applied power for EAS and 30 ° C substrate temperature
Perform for 140 seconds. Inside contact holes 5S and 5D
And W plugs 7S and 7D remain, respectively,
In regions other than the holes 5S and 5D, the second TiN layer 6
The surface of d is exposed.

At this time, contact holes 5S and 5D
In order to prevent the unnecessary W film 7 from remaining in a region other than the region, it is preferable to slightly overetch the film. When over-etching, the upper surfaces of the W plugs 7S and 7D are slightly lower than the upper surface of the second TiN layer 6d, and shallow depressions are formed in the regions where the contact holes 5S and 5D are formed.

In FIG. 3A, W plugs 7S and 7
A thickness of about 15 nm made of Ti on the entire surface of the substrate including the upper surface of D
Is deposited. The underlayer 8 is deposited, for example, as shown in FIG.
This is performed by the same method as that for the Ti layer 6a described in (C).

On the underlayer 8, a wiring layer 9 having a thickness of about 400 nm and made of an Al alloy containing 1% by weight of Si and 0.5% by weight of Cu is deposited by sputtering. The wiring layer 9 is deposited by using, for example, an Al alloy as a target and Ar as a sputtering gas at a substrate temperature of 150 ° C. and a pressure of 2 m.
Torr, a sputtering gas flow rate of 20 sccm, and a film forming speed of about 1 μm / min.

After the formation of the wiring layer 9,
Heat treatment is performed at a temperature of about 450 to 500 ° C. for about 120 seconds. By this heat treatment, the Al alloy reflows, and the coverage ratio of the dent formed in the openings of the contact holes 5S and 5D is improved.

As shown in FIG. 3B, the wiring layer 9 is patterned and connected to the wiring 9S connected to the source region 3S via the W plug 7S and to the drain region 3D via the W plug 7D. The wiring 9D is formed. An interlayer insulating film 10 made of an insulating material such as PSG is deposited on the entire surface of the substrate by CVD or the like so as to cover the wirings 9S and 9D.

In the above embodiment, before depositing the W layer 7 in the step shown in FIG.
It is covered with the layer 6d, and the TiON layer 6c is not exposed. Further, in the step of etching back the W layer 7 shown in FIG. 2B, since the second TiN layer 6d acts as an etching stop layer, the TiON layer 6c does not appear on the substrate surface during the etch back. Therefore, release of oxygen from the TiON layer 6c can be prevented, and a local increase in the etching rate of the W layer 7 due to oxygen can be prevented. Therefore, substantially uniform etching is performed over the entire surface of the substrate, and the generation of the plug loss 115, the trench 116, and the seam 117 shown in FIG. 4 can be prevented.

According to the above embodiment, the W plugs 7S and 7
D and the source / drain regions 3S and 3D between the Ti layer 6a, the first TiN layer 6b, the TiON layer 6c, and the second
The four TiN layers 6d are interposed. The TiON layer 6c functions as a barrier metal layer and suppresses a reaction between the W plug and the surface of the silicon substrate.

In the above embodiment, the first TiN layer 6b is temporarily deposited instead of depositing the TiON layer 6c directly on the Ti layer 6a. The surface of the Ti layer 6a is TiON
Since it is not exposed to the oxidizing atmosphere at the time of depositing the layer 6c, formation of the TiO layer due to oxidation of the Ti layer 6a can be prevented. For this reason, it is possible to stably obtain a good electrical connection.

Ti layer 6a, first TiN layer 6b, TiO
The thickness of each of the N layer 6c and the second TiN layer 6d is 2
The connection between the impurity diffusion region on the surface of the silicon substrate and the wiring layer was performed in the same manner as in the above-described evaluation experiment, except that 0 nm, 25 nm, 50 nm, and 25 nm were used. As a result, the contact resistance between the n-type region and the wiring layer was 18Ω, and the contact resistance between the p-type region and the wiring layer was 110Ω, and both were ohmic contacts. Thus, before depositing the TiON layer, the first TiN layer is deposited to cover the surface of the Ti layer, and before depositing the W layer, the surface of the TiON layer is deposited on the second TiN layer.
Covering with a layer makes it possible to obtain a good electrical connection.

In the above embodiment, since the TiON layer is deposited by reactive sputtering, a thick film can be easily formed as compared with the case where the surface of the TiN layer is formed by oxidation.

[0039] In the above embodiment, a case has been described using W as a material of the embedded plug, other conductive material, for example Mo, the same effect even by using a WSi _x or the like is expected.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0041]

As described above, according to the present invention,
After depositing a Ti layer in the contact hole, the surface of the Ti layer is covered with a first TiN layer before depositing a TiON layer acting as a barrier metal layer. For this reason, the Ti layer
No longer exposed to the oxidizing atmosphere during the deposition of the iON layer,
Oxidation of the layer surface can be prevented. After depositing the TiON layer and before forming the buried plug, the surface of the TiON layer is covered with a second TiN layer. Therefore, the release of oxygen from the TiON layer during the formation of the buried plug can be prevented, and the adverse effect of the oxygen on the formation of the buried plug can be prevented. In this manner, it is possible to stably obtain the electrical connection between the semiconductor substrate surface and the wiring layer.

[Brief description of the drawings]

FIG. 1 is a sectional view (part 1) of a semiconductor substrate for describing a wiring forming method according to an embodiment of the present invention.

FIG. 2 is a sectional view (part 2) of a semiconductor substrate for describing a wiring forming method according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view (part 3) of a semiconductor substrate for describing a wiring forming method according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view of a W plug formed by an experiment performed by the present inventors.

[Explanation of symbols]

1, 100: silicon substrate, 2: field oxide film, 3
S: source region, 3D: drain region, 3G: gate electrode, 3W: sidewall insulator, 3I: gate insulating film, 4, 110: interlayer insulating film, 5S, 5D, 111: contact hole, 6a, 112: Ti Layers, 6b, 6d ...
TiN layer, 6c, 113 ... TiON layer, 7, 114a ...
W layer, 7S, 7D, 114b W plug, 8 base layer,
9 wiring layer, 9S, 9D wiring, 10 interlayer insulating film, 1
15: plug loss, 116: trench, 117: seam

Continuation of the front page (56) References JP-A-6-244185 (JP, A) JP-A-4-80917 (JP, A) JP-A-7-29851 (JP, A) JP-A-9-176851 (JP) JP-A-6-188216 (JP, A) JP-A-5-299376 (JP, A) JP-A-4-79218 (JP, A) JP-A-7-118833 (JP, A) JP-A-9-261596 (JP, A) JP-A-7-74168 (JP, A) JP-A-6-132248 (JP, A) JP-A-6-53332 (JP, A) A) JP-A-6-37033 (JP, A) JP-A-6-20994 (JP, A) JP-A-6-13380 (JP, A) JP-A-6-5599 (JP, A) JP-A-5 JP-A-5-182926 (JP, A) JP-A-5-121356 (JP, A) JP-A-5-67792 (JP, A) JP-A-4-214653 (JP, A) JP-A-4-65823 (JP, A) JP-A-4-27163 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/285 301 H01L 21/768

Claims (6)

(57) [Claims] An interlayer insulating film is deposited on a semiconductor substrate,
Forming a contact hole in the interlayer insulating film; depositing a Ti layer by sputtering in a first chamber on a surface of the interlayer insulating film and on an inner surface of the contact hole; Transferring the semiconductor substrate formed in the first chamber from the first chamber to the second chamber; and in the second chamber, substantially on the surface of the Ti layer including the inside of the contact hole. Depositing a first TiN layer in an oxygen-free atmosphere, depositing a TiON layer on the first TiN layer, and depositing a second 25 nm thick second layer on the TiON layer. Depositing a TiN layer; depositing a conductive layer made of a conductive material on a surface of the second TiN layer so as to fill the contact hole; surface A step of forming a buried plug in the contact hole by etching back until it is exposed; and a step of forming a wiring connected to the buried plug on the interlayer insulating film. Forming method. 2. An interlayer insulating film is deposited on a semiconductor substrate,
Forming a contact hole in the interlayer insulating film; depositing a Ti layer on the surface of the interlayer insulating film and on the inner surface of the contact hole; and forming a contact layer on the surface of the Ti layer including the inside of the contact hole. ,
The first Ti is formed by reactive sputtering in which a Ti target is sputtered in a nitrogen atmosphere substantially free of oxygen.
Depositing an N layer; depositing a TiON layer on the first TiN layer by reactive oxygen sputtering by additionally introducing oxygen into a nitrogen atmosphere; and forming a 25 nm thick layer on the TiON layer. Depositing a conductive layer made of a conductive material on the surface of the second TiN layer so as to fill the contact hole, and depositing the conductive layer on the second TiN layer. Etching back until the surface of the TiN layer is exposed to form a buried plug in the contact hole; and forming a wiring connected to the buried plug on the interlayer insulating film. A wiring forming method for a semiconductor device, comprising: 3. An interlayer insulating film is deposited on a semiconductor substrate,
Forming a contact hole in the interlayer insulating film; depositing a Ti layer on the surface of the interlayer insulating film and on the inner surface of the contact hole; and forming a contact layer on the surface of the Ti layer including the inside of the contact hole. ,
Depositing a first TiN layer in an atmosphere substantially free of oxygen; depositing a TiON layer on the first TiN layer; and depositing a 25 nm thick second layer on the TiON layer. Depositing a W layer on the surface of the second TiN layer including the inside of the contact hole; and depositing the W layer on the surface of the second TiN layer until the surface of the second TiN layer is exposed. A semiconductor device comprising: a step of etching back to leave a buried plug made of a part of a W layer in the contact hole; and a step of forming a wiring connected to the buried plug on the interlayer insulating film Wiring formation method. 4. An interlayer insulating film is deposited on a semiconductor substrate,
Forming a contact hole in the interlayer insulating film; depositing a Ti layer by sputtering in a first chamber on a surface of the interlayer insulating film and on an inner surface of the contact hole; Transferring the semiconductor substrate formed in the first chamber from the first chamber to the second chamber; and in the second chamber, substantially on the surface of the Ti layer including the inside of the contact hole. Depositing a 25 nm thick first TiN layer in an atmosphere containing no oxygen, depositing a TiON layer on the first TiN layer, and depositing a second TiON layer on the TiON layer. Depositing a conductive layer made of a conductive material on the surface of the second TiN layer so as to fill the contact hole, and forming the conductive layer on the second TiN layer. Table Forming a buried plug in the contact hole by etching back until the semiconductor device is exposed, and forming a wiring connected to the buried plug on the interlayer insulating film. Wiring formation method. 5. An interlayer insulating film is deposited on a semiconductor substrate,
Forming a contact hole in the interlayer insulating film; depositing a Ti layer on the surface of the interlayer insulating film and on the inner surface of the contact hole; and forming a contact layer on the surface of the Ti layer including the inside of the contact hole. ,
Reactive sputtering for sputtering a Ti target in a nitrogen atmosphere substantially free of oxygen has a thickness of 25
depositing a TiON layer on the first TiN layer by reactive sputtering, additionally introducing oxygen into a nitrogen atmosphere, and depositing a TiON layer on the first TiN layer. Depositing a second TiN layer, and depositing a conductive layer made of a conductive material on the surface of the second TiN layer so as to fill the contact hole. Forming a buried plug in the contact hole by etching back until the surface of the second TiN layer is exposed; and forming a wiring connected to the buried plug on the interlayer insulating film. A wiring forming method for a semiconductor device, comprising: 6. An interlayer insulating film is deposited on a semiconductor substrate,
Forming a contact hole in the interlayer insulating film; depositing a Ti layer on the surface of the interlayer insulating film and on the inner surface of the contact hole; and forming a contact layer on the surface of the Ti layer including the inside of the contact hole. ,
Depositing a 25 nm thick first TiN layer in an atmosphere substantially free of oxygen; depositing a TiON layer on the first TiN layer; Depositing a second TiN layer; depositing a W layer on the surface of the second TiN layer including the inside of the contact hole; exposing the W layer to the surface of the second TiN layer A semiconductor having a step of leaving an embedded plug made of a part of the W layer in the contact hole, and a step of forming a wiring connected to the embedded plug on the interlayer insulating film Method of forming wiring of device.