JP3294721B2 - Semiconductor device manufacturing method and bump manufacturing method - Google Patents

Semiconductor device manufacturing method and bump manufacturing method

Info

Publication number
JP3294721B2
JP3294721B2 JP21929494A JP21929494A JP3294721B2 JP 3294721 B2 JP3294721 B2 JP 3294721B2 JP 21929494 A JP21929494 A JP 21929494A JP 21929494 A JP21929494 A JP 21929494A JP 3294721 B2 JP3294721 B2 JP 3294721B2
Authority
JP
Japan
Prior art keywords
bump
semiconductor device
forming
manufacturing
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP21929494A
Other languages
Japanese (ja)
Other versions
JPH0883801A (en
Inventor
彰一 田中
正栄 南澤
清治 上野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
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Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21929494A priority Critical patent/JP3294721B2/en
Publication of JPH0883801A publication Critical patent/JPH0883801A/en
Application granted granted Critical
Publication of JP3294721B2 publication Critical patent/JP3294721B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
及びバンプの製造方法に係り、特に転写方式によってバ
ンプを接合する半導体装置の製造方法と、転写方式によ
って製造されるバンプの製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device.
And it relates to a method of manufacturing a bump, and a method of manufacturing a semiconductor device for joining the bumps in particular by transfer method relates to the manufacturing method of the bumps that are produced by a transfer method.

【0002】近年、半導体素子を用いた電子部品の高速
化、小型化とそれに伴う実装密度の高密化、及び低消費
電力化への要求は高まる一方である。
In recent years, there has been an increasing demand for higher speed, smaller size, higher packing density, and lower power consumption of electronic components using semiconductor elements.

【0003】上記の要求を満たすに当たって様々な手段
が考えられるが、半導体チップを搭載した半導体装置を
実装基板に低抵抗で接続することはその有効な手段の一
つである。
Various means are conceivable for satisfying the above-mentioned requirements, and connecting a semiconductor device mounted with a semiconductor chip to a mounting substrate with low resistance is one of the effective means.

【0004】即ち、半導体装置が低抵抗で基板に実装さ
れていれば半導体装置間を伝播する電気的信号の速度が
速くなり、半導体装置によって作動する電子機器全体の
高速化を図れる上に消費電力も小さくなる。更に半導体
素子が作動するに当たって発生する熱も少なくなるの
で、半導体装置間の配設距離を小さくし、高密度実装が
可能になると共に電子機器の小型化にも好都合である。
That is, if a semiconductor device is mounted on a substrate with a low resistance, the speed of an electric signal propagating between the semiconductor devices is increased, so that the speed of an entire electronic device operated by the semiconductor device can be increased and power consumption can be increased. Is also smaller. Further, since heat generated when the semiconductor element operates is reduced, the distance between the semiconductor devices is reduced, which enables high-density mounting, and is also advantageous for miniaturization of electronic equipment.

【0005】半導体装置と実装基板を低抵抗で接続する
ためには、半導体装置自身に取り付けられて、実装基板
と接続するのに用いられる端子の抵抗を小さくすれば良
い。
In order to connect the semiconductor device and the mounting board with a low resistance, the resistance of the terminal attached to the semiconductor device itself and used for connecting to the mounting board may be reduced.

【従来の技術】表面実装用の端子であるバンプを低抵抗
にすることは、電子機器の高速化、及小型化、省消費電
力化に寄与することが可能である。
2. Description of the Related Art Reducing the resistance of bumps, which are terminals for surface mounting, can contribute to speeding up, miniaturization, and power saving of electronic equipment.

【0006】バンプの製造方法の一つに、半導体チップ
に対して汎用性があり、製造コストも安価である転写バ
ンプ方式がある。
As one of the bump manufacturing methods, there is a transfer bump method which is versatile for semiconductor chips and has a low manufacturing cost.

【0007】従来の転写方式によるバンプの製造方法の
構成を以下に簡単に述べる。
The configuration of a conventional method of manufacturing a bump by a transfer method will be briefly described below.

【0008】バンプを形成するには、先ず形成基板を用
意する。このバンプ形成基板は、通常ガラス材や、Al
N等でできている。バンプ形成基板に対してITO膜
(Indium Tin Oxide)を成膜する。I
TO膜は転写金属膜として使用するもので、成型された
バンプを後の工程で形成基板から外す際に重要な役割を
果たすものである。 次にITO膜上からレジストを塗
布し、フォトリソグラフィー工程によってパターニング
を行いバンプ成形用の型を作る。この成型用の型に対し
てバンプとなる金属部材をメッキ、蒸着、スパッタリン
グ等の方法で堆積する。現在、一般的にバンプの金属材
料としては金(Au)が用いられている。
To form a bump, first, a formation substrate is prepared. This bump forming substrate is usually made of a glass material or Al.
It is made of N. An ITO film (Indium Tin Oxide) is formed on the bump forming substrate. I
The TO film is used as a transfer metal film and plays an important role when the formed bump is removed from the formation substrate in a later step. Next, a resist is applied from above the ITO film, and is patterned by a photolithography process to form a mold for forming a bump. A metal member to be a bump is deposited on the molding die by plating, vapor deposition, sputtering, or the like. At present, gold (Au) is generally used as a metal material for bumps.

【0009】次にバンプを半導体装置の然るべき接続部
分に接続するのであるが、半導体装置の電極、リード等
の接続部分がSnメッキの場合は、Au・Sn共晶合
金、Auメッキの場合はAu・Au熱圧着で接合する。
この時にバンプが形成基板から速やかに外れることが必
要である。よって、バンプ形成基板とバンプとの接着力
が半導体装置側の接続部分とバンプとの接合力より小さ
くなくてはならない。先に成膜しておいたITO膜とA
uとの接合力は比較的弱く、この形成基板からバンプを
剥離する工程で、速やかにバンプを形成基板から離す機
能を有するものである。
Next, the bumps are connected to appropriate connection portions of the semiconductor device. When the connection portions of the electrodes and leads of the semiconductor device are plated with Sn, an Au-Sn eutectic alloy is used. -Joining by Au thermocompression bonding.
At this time, it is necessary that the bumps come off the formation substrate quickly. Therefore, the adhesive force between the bump forming substrate and the bump must be smaller than the bonding force between the connection portion on the semiconductor device side and the bump. A and ITO film formed earlier
The bonding force with u is relatively weak, and has a function of quickly separating the bump from the formation substrate in the step of separating the bump from the formation substrate.

【0010】この部材間の接着力は、被接着部材と、着
部材の分子構造、及び分子の大きさが近似しているほど
大きくなる。
[0010] The adhesive force between the members increases as the molecular structure and the molecular size of the member to be bonded and the attaching member are closer to each other.

【0011】[0011]

【発明が解決しようとする課題】電子機器の高速化、高
密化への要求は高まる一方であり、Au製のバンプを用
いた半導体装置の実装の際の抵抗は、この要求に答える
にはまだ高い。その上Auは高価な貴金属であり、半導
体装置の製造コストを上げる。
The demand for higher speed and higher density of electronic equipment is increasing, and the resistance when mounting a semiconductor device using a bump made of Au is not yet enough to meet this demand. high. In addition, Au is an expensive noble metal, which increases the manufacturing cost of the semiconductor device.

【0012】本発明は以上の点を鑑みてなされたもので
あり、電気特性の向上を図ると共に低コストを実現でき
る半導体装置の製造方法、及びバンプの製造方法を提供
することを目的とするものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to provide a method of manufacturing a semiconductor device and a method of manufacturing a bump capable of improving electrical characteristics and realizing low cost. It is.

【0013】[0013]

【課題を解決するための手段】上記目的を達成するため
に、請求項1の半導体装置の製造方法では、電極を有す
る半導体装置本体を構成する工程と、形成基板上に、バ
ナジウム(V)からなる転写金属膜を設ける工程と、該
転写金属膜上にバンプ形成材を成型する成型用型を設
け、続いて銅(Cu)からなる低抵抗金属を該バンプ形
成材として、該成型用型を用いて該形成基板上の該転写
金属膜上に被着し、バンプを形成する工程と、該バンプ
を該形成基板から該電極に転写する工程とよりなること
を特徴とするものである。
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a semiconductor device body having electrodes ;
A step of providing a transfer metal film made of vanadium (V), the mold for molding the bump forming material on the transfer metal layer is provided, followed made of copper (Cu) with low resistance metals as the bump forming material Forming a bump on the transfer metal film on the formation substrate using the molding die, and forming the bump; and transferring the bump from the formation substrate to the electrode. Is what you do .

【0014】請求項2の半導体装置の製造方法では、低
抵抗金属を形成基板に蒸着、スパッタリング、或いはメ
ッキの成膜方法によって形成することを特徴とするもの
ある。
According to a second aspect of the invention, there is provided a method of manufacturing a semiconductor device, wherein a low-resistance metal is formed on a formation substrate by a deposition, sputtering, or plating method .

【0015】請求項3のバンプの製造方法では、半導体
装置本体に設けられた電極に接合されるバンプの製造方
法において、形成基板上に、バナジウム(V)からなる
転写金属膜を設ける工程と、該転写金属膜上にバンプ
成材を成型する成型用型を設け、続いて銅(Cu)から
なる低抵抗金属を該バンプ形成材として、該形成基板上
の該転写金属膜に接着するように被着し、かつ成型用型
を用いて成型してバンプとする工程よりなることを特徴
とするものである。
According to a third aspect of the present invention , in the method of manufacturing a bump to be joined to an electrode provided on a semiconductor device body, a transfer metal film made of vanadium (V) is formed on a formation substrate. Providing a forming mold for forming a bump forming material on the transfer metal film, and then forming a mold from copper (Cu).
It becomes a low resistance metals as the bump forming material, and characterized by comprising the step of the bump by molding using a deposited to adhere to the transfer metal film on the formation substrate, and molding die Is what you do .

【0016】請求項4のバンプの製造方法では、低抵抗
属を形成基板に蒸着、スパッタリング、或いはメッキ
の成膜方法によって形成することを特徴とするもので
る。
[0016] In the production method of the bumps according to claim 4, Oh characterized in forming deposited forming substrate resistance <br/> metals, sputtering, or by a film forming method of plating
You.

【0017】[0017]

【作用】請求項1記載の発明により、バンプの部材をA
uよりも電気抵抗の低いCuからなる低抵抗金属にした
ことにより、半体装置を電子機器へ接続する際の電気抵
抗を更に低くすることができる。また、Cuの低抵抗金
属に対してVを転写用金属としたことにより、成型され
たバンプを形成基板から速やかに剥離することができ
る。
According to the first aspect of the present invention, the bump member is made of A
By using a low-resistance metal made of Cu having a lower electric resistance than u, the electric resistance when connecting the half device to the electronic apparatus can be further reduced . In addition, low resistance gold of Cu
By using V as the transfer metal for the genus,
Bumps can be quickly removed from the substrate
You.

【0018】請求項2記載の発明により、低抵抗金属を
形成基板に被着する方法を、蒸着、スパッタリング、或
いはメッキの成膜方法によって形成することにより、低
抵抗金属の膜厚の均一性が高くなり、半導体装置の信頼
性を向上することができる。
According to the second aspect of the present invention, the method of depositing the low-resistance metal on the formation substrate is performed by a deposition, sputtering, or plating method, so that the low-resistance metal has a uniform thickness. And the reliability of the semiconductor device can be improved .

【0019】請求項3記載の発明により、従来の半導体
装置のAu製バンプを更に電気抵抗の低いCu部材に代
えることにより、半導体装置本体の構成を変えず、半導
体装置を更に低い抵抗で実装可能にする。また、Cuの
低抵抗金属に対してVを転写用金属としたことにより、
成型されたバンプを形成基板から速やかに剥離すること
ができる。
According to the third aspect of the present invention, by replacing the Au bump of the conventional semiconductor device with a Cu member having a lower electric resistance, the semiconductor device can be mounted with a lower resistance without changing the configuration of the semiconductor device body. to. In addition, Cu
By using V as a transfer metal for low-resistance metals,
Promptly peel off molded bumps from forming substrate
Can be.

【0020】請求項4記載の発明により、低抵抗金属を
形成基板に被着する方法を、蒸着、スパッタリング、或
いはメッキの成膜方法によって形成することにより、低
抵抗金属の膜厚の均一性が高くなる。従って半導体装置
本体の構成を変えずに、半導体装置の信頼性を向上する
ことができる。
According to the fourth aspect of the present invention, the method of depositing the low-resistance metal on the formation substrate is performed by a deposition, sputtering, or plating method, so that the low-resistance metal has a uniform thickness. Get higher. Therefore, the reliability of the semiconductor device can be improved without changing the configuration of the semiconductor device body.

【0021】[0021]

【実施例】先ず、本発明の一実施例である半導体装置1
の概略構成を図3に示す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a semiconductor device 1 according to an embodiment of the present invention will be described.
FIG. 3 shows a schematic configuration of.

【0022】図3中、7は半導体装置1の半導体装置本
体7である。本実施例はバンプを接合する構成のいかな
る半導体装置本体に対しても適用できるが、ここではB
GA(ball grid array)と呼ばれる表
面実装型LSIパッケージを用いている。
In FIG. 3, reference numeral 7 denotes a semiconductor device body 7 of the semiconductor device 1. This embodiment can be applied to any semiconductor device body having a configuration in which bumps are joined.
A surface mount type LSI package called a GA (ball grid array) is used.

【0023】本実施例で構成した半導体装置本体7は、
ガラスエポキシ樹脂製の基板1b上に半導体チップ1a
をダイボンデイ ングエポキシ1dで固定した。半導体チ
ップ1a上に形成されたチップ電極1eと電極8とをワ
イヤー1cで接続し、更にモールド樹脂1fを基板1b
の上面に例えばポッテイ ングすることにより、半導体チ
ップ1a及びワイヤー1c等を封止した構成となってい
る。半導体装置1は半導体装置7に請求項6乃至7に記
載の発明によるCu製バンプ6を、半導体装置本体7に
形成されている電極8に接合して完成した状態のCu製
バンプ6を有する半導体装置1である。
The semiconductor device body 7 constructed in this embodiment is
Semiconductor chip 1a on substrate 1b made of glass epoxy resin
Was fixed with die bonding epoxy 1d. The chip electrode 1e formed on the semiconductor chip 1a and the electrode 8 are connected with the wire 1c, and the mold resin 1f is connected to the substrate 1b.
The semiconductor chip 1a, the wire 1c, and the like are sealed by, for example, potting on the upper surface of the semiconductor chip 1a. The semiconductor device 1 includes a semiconductor device 7 having a completed Cu bump 6 by bonding the Cu bump 6 according to the invention of claim 6 to an electrode 8 formed on the semiconductor device body 7. The device 1.

【0024】バンプは従来Auを材料として製造されて
いたが、これをCu製バンプ6としたことによって、電
極8との電気的抵抗が従来より低くなる。よって、半導
体装置1を実装する際の電気的抵抗が低くなる。
Conventionally, the bumps have been manufactured using Au as a material. However, by using the Cu bumps 6, the electrical resistance with the electrodes 8 becomes lower than before. Therefore, the electrical resistance when mounting the semiconductor device 1 is reduced.

【0025】図1を用いて本発明の一実施例である半導
体装置の製造方法、及びバンプ6aの製造方法を説明す
る。また、図2に実施例で使用した工程をまとめて示
す。
Referring to FIG. 1, a method of manufacturing a semiconductor device and a method of manufacturing a bump 6a according to an embodiment of the present invention will be described. FIG. 2 collectively shows the steps used in the examples.

【0026】尚、上記の半導体装置1の製造方法とバン
プ6の製造方法は共通する工程が多いため、各製造方法
をまとめて説明することとする。
Since the method for manufacturing the semiconductor device 1 and the method for manufacturing the bump 6 have many common steps, the respective manufacturing methods will be described together.

【0027】図1(a)中、2はバンプ形成基板でガラ
ス材より成っている。このバンプ形成基板2上には、先
ず電極3となるCrが成膜される。この電極3は後述す
る電界メッキを用いてバンプを形成する際の電極として
機能するものである。さらに電極3の上に転写金属膜4
としてVをスパッタリングで1μmの厚さに成膜する。
尚、転写金属膜4の材質としてはVに限定されず、例え
ばCr、Ti等の適用も考えられる。これらの金属は後
述するバンプ材料(Cu)に対して適宣な接合力を有し
たものである。
In FIG. 1A, reference numeral 2 denotes a bump forming substrate made of a glass material. First, a Cr film to be the electrode 3 is formed on the bump forming substrate 2. The electrode 3 functions as an electrode when a bump is formed using electroplating described later. Further, a transfer metal film 4 is formed on the electrode 3.
Is formed to a thickness of 1 μm by sputtering.
Incidentally, the material of the transfer metal film 4 is not limited to V, and for example, application of Cr, Ti, or the like can be considered. These metals have proper bonding strength to a bump material (Cu) described later.

【0028】以上が図2においてステップ1(以下ステ
ップをsと略称する)及びs2として示した工程であ
る。次に図1(b)のように図1(a)で示した状態の
形成基板2、及びその上の転写金属膜4上にバンプ成型
用の型5をネガレジスト、或いは感光樹脂を用いたフォ
トリソグラフィーのプロセスによって形成する。この工
程は図2のs3に相当するものである。
The above is the process shown as step 1 (hereinafter, step is abbreviated as s) and s2 in FIG. Next, as shown in FIG. 1 (b), a mold 5 for bump molding is formed on the formation substrate 2 in the state shown in FIG. 1 (a) and the transfer metal film 4 thereon using a negative resist or a photosensitive resin. It is formed by a photolithography process. This step corresponds to s3 in FIG.

【0029】次に図1(c)に示すようにメッキ法によ
って低抵抗金属6aであるCuを成型用型5を通して形
成基板2に設けられた転写金属膜4上に堆積させる。低
抵抗金属6aは成型用型5より露出した転写金属膜4上
にのみ堆積されるので、成型用型5にそって低抵抗金属
6aがバンプの形状に成型される。本実施例においては
低抵抗金属6aの材質としてCuを用いる。前記したよ
うに、CuはAuよりも電気抵抗が低い部材である。
Next, as shown in FIG. 1C, Cu, which is a low-resistance metal 6a, is deposited on the transfer metal film 4 provided on the formation substrate 2 through a molding die 5 by plating. Since the low-resistance metal 6a is deposited only on the transfer metal film 4 exposed from the molding die 5, the low-resistance metal 6a is molded into a bump shape along the molding die 5. In this embodiment, Cu is used as the material of the low-resistance metal 6a. As described above, Cu is a member having lower electric resistance than Au.

【0030】また、メッキ法は膜の堆積厚さの制御性、
及び精度の高い方法であるので形成されるバンプの高さ
が均一に揃い、工程の歩留りを向上させる。以上の工程
が図2におけるs4に相当するものである。
In addition, the plating method controls the deposition thickness of the film,
In addition, since the method is highly accurate, the heights of the bumps to be formed are uniform, and the yield of the process is improved. The above steps correspond to s4 in FIG.

【0031】尚、本実施例ではメッキ法により低抵抗金
属6aを形成しているが、メッキ法に代えて蒸着法、ス
パッタリング法を用いて形成する方法を用いて良い。こ
の各方法のいずれを用いた場合においても成膜される低
抵抗金属6aの均一性は保証される。続いて図1(d)
のように成形用型5からメッキによって形成されたCu
製バンプ6を除去する。この時に、成形用型5はドラ
イ、或いはウェットのいずれの方法のレジスト剥離のプ
ロセスを用いて除去しても良いし、そのまま残して再利
用しても良い。図1(d)では除去した状態を示してい
るが、成型用型5を繰り返し使用すれば、更に工程数を
減らして、マスク作成にかかる時間、及びコストの低減
が可能となる。
Although the low-resistance metal 6a is formed by plating in this embodiment, a method of forming the low-resistance metal 6a by vapor deposition or sputtering instead of plating may be used. Even when any of these methods is used, the uniformity of the low-resistance metal 6a formed is ensured. Subsequently, FIG. 1 (d)
Cu formed by plating from the molding die 5 as shown in FIG.
The bump 6 made is removed. At this time, the molding die 5 may be removed by using a dry or wet resist stripping process, or may be left as it is for reuse. FIG. 1D shows the removed state. However, if the mold 5 is used repeatedly, the number of steps can be further reduced, and the time and cost required for mask production can be reduced.

【0032】本実施例においてCu製バンプ6と接合さ
れる被接合物との接合力は充分強固であり、かつCu製
バンプ6と転写金属膜4であるVとの接合力が充分小さ
い条件が満たされているために成型用型5を除去せずに
Cu製バンプ6を成型用型から外すことも実施可能であ
る。また、Cr、TiもVと同様にCuとの接合力が小
さい条件を満たす部材であるためにCu製バンプ6の転
写金属膜として使用することが可能である。この工程は
図2のs5に当たる。
In this embodiment, it is required that the bonding strength between the Cu bump 6 and the object to be bonded is sufficiently strong, and that the bonding strength between the Cu bump 6 and the V as the transfer metal film 4 is sufficiently small. It is also possible to remove the Cu bump 6 from the molding die without removing the molding die 5 because it is filled. Further, since Cr and Ti are members that satisfy the condition that the bonding force with Cu is small similarly to V, they can be used as the transfer metal film of the bump 6 made of Cu. This step corresponds to s5 in FIG.

【0033】最後に図1(e)の様に位置を合わせてC
u製バンプ6を半導体装置7の電極8に熱圧着によって
Au・Al合金を形成して接合した。これはCuをその
まま露出して大気に触れたままの状態にすると表面が酸
化されて電伝導度が低下してしまうため、表面にAuメ
ッキを施し、熱圧着の手段を用いたものである。これは
図2においては、s6に相当する。
Finally, the position is adjusted as shown in FIG.
The u bump 6 was bonded to the electrode 8 of the semiconductor device 7 by forming an Au.Al alloy by thermocompression bonding. This is because the surface is oxidized and the electrical conductivity is reduced if Cu is exposed as it is and is kept in contact with the atmosphere, so the surface is plated with Au and thermocompression bonding is used. This corresponds to s6 in FIG.

【0034】尚、本実施例では形成基板2にガラス材を
用いたが、形成基板2自身を金属製にすることで電極3
を設ける工程を省くことができる。
In this embodiment, a glass material is used for the formation substrate 2. However, the formation of the electrodes 3
Can be omitted.

【0035】一般に半導体装置はガラス材を基にして構
成される、よってそれに関するプロセスもガラス材を中
心にして設計してある。このために本実施例でも形成基
板にガラス材を用いたのであるが、プロセス上の整合性
が要求されるのは熱による膨張、変形の特性の違いによ
るものが多い。よって金属であってもSi等の物質に熱
膨張係数、及び融点の近い部材(例えばMo)を使用す
れば金属基板を使用する方法も可能である。
In general, a semiconductor device is constructed on the basis of a glass material. Therefore, a process relating to the semiconductor device is designed mainly on the glass material. For this reason, a glass material is used for the formation substrate in this embodiment as well. However, consistency in the process is often required due to differences in expansion and deformation characteristics due to heat. Therefore, even if it is a metal, a method using a metal substrate is also possible if a member having a similar thermal expansion coefficient and melting point (for example, Mo) is used for a substance such as Si.

【0036】Auの電気抵抗は、体積抵抗率で2.4×
10-8Ω・mと比較的低い部材であるが、Cuの体積抵
抗率は1.72×10-8Ω・mと更に低い。よってAu
に代えてCuでバンプを形成すれば、半導体装置1は更
に低抵抗で電子機器に実装されることになる。
The electric resistance of Au is 2.4 × in volume resistivity.
Although the member is relatively low at 10 −8 Ω · m, the volume resistivity of Cu is even lower at 1.72 × 10 −8 Ω · m. Therefore Au
If the bump is formed of Cu instead of the semiconductor device 1, the semiconductor device 1 will be mounted on the electronic device with a lower resistance.

【0037】また、Auに比べてCuは価格の低い部材
であるから、バンプ6によって半導体装置本体7の構成
等の変更すること無く、従来から使用されてきた半導体
装置本体7、或いは汎用品等を適用して半導体装置1の
製造コストの低価格化が実現できる。
Further, since Cu is a low-priced member as compared with Au, the semiconductor device body 7 conventionally used or a general-purpose product can be used without changing the configuration of the semiconductor device body 7 by the bumps 6. By applying the method described above, the manufacturing cost of the semiconductor device 1 can be reduced.

【0038】上記したように、Cuはバンプを形成する
上でAuよりも有利な点を有する部材である。
As described above, Cu is a member having advantages over Au in forming bumps.

【0039】以上述べた構成としたによって、半導体装
置1を回路基板に実装する際の電気的抗が小さくなり、
電気的信号の伝播速度を大きくすると共に、半導体装置
が作動する際に発生する熱が少なくなって電子機器の高
速化、及び小型化、実装密度の高密化を図ることができ
る。
With the configuration described above, the electrical resistance when mounting the semiconductor device 1 on a circuit board is reduced.
In addition to increasing the propagation speed of an electric signal, heat generated when the semiconductor device operates is reduced, so that the speed, size, and density of the electronic device can be increased.

【0040】更にAuに比べて安価であるCuをバンプ
に用いたことによって半導体装置の製造コストの低減も
可能となった。
Further, the use of Cu, which is inexpensive as compared with Au, for the bump makes it possible to reduce the manufacturing cost of the semiconductor device.

【0041】本来、転写方式で形成されるバンプは半導
体装置の端子数を増やし、かつコストを上げないように
するため、比較的高価であったピンに代えて開発された
ものである。よってバンプを低価格の材料に変えること
はバンプの開発目的に沿う効果を有するものである。
Originally, the bumps formed by the transfer method were developed to replace the relatively expensive pins in order to increase the number of terminals of the semiconductor device and not to increase the cost. Therefore, changing the bump to a low-cost material has an effect in accordance with the purpose of developing the bump.

【0042】[0042]

【発明の効果】以上述べたように、本発明の半導体装置
の製造方法及び半導体装置、及びバンプの製造方法及び
バンプは、請求項1記載の発明により、体装置を電子
機器へ接続する際の電気抵抗を更に低くすることによ
り、半導体装置間の電気的信号の伝播速度が速くなり、
特に高速を要求される半導体装置への適用が可能とな
る。また、半導体装置の作動に伴って発生する熱量も抑
制されて半導体装置の実装密度の高密化、それに伴う小
型化、更には熱による誤動作の抑制も可能となる。ま
た、従来のAu製バンプを有する半導体装置と比較
て、半導体装置の製造コストの低減も可能である。よっ
て、半導体装置を多数搭載する電子機器を安価で提供す
ることができる。また、成型されたバンプを形成基板か
ら速やかに剥離することができる。よって形成したバン
プの変形等のトラブルを無くして工程の歩留りの向上を
図ることができる。
As described above, according to the present invention, a method of manufacturing a semiconductor device and, and a manufacturing method and a bump of bumps of the semiconductor device of the present invention, the invention of claim 1, wherein, when connecting the halves device to the electronic device By further reducing the electrical resistance of the semiconductor device, the speed of propagation of electrical signals between the semiconductor devices is increased,
In particular, it can be applied to a semiconductor device requiring a high speed. In addition, the amount of heat generated due to the operation of the semiconductor device is suppressed, so that the mounting density of the semiconductor device can be increased, the size can be reduced, and malfunction due to heat can be suppressed . Ma
It was, compared to a conventional semiconductor device having an Au-made bumps
Te, it is possible reduce the manufacturing cost of semiconductors devices. Therefore, an electronic device on which a large number of semiconductor devices are mounted can be provided at low cost. In addition, the molded bumps
Can be quickly peeled off. Thus the formed van
Eliminate troubles such as deformation of the pump and improve process yield
Can be planned.

【0043】請求項記載の発明により、低抵抗金属を
形成基板に被着する方法を、蒸着、スパッタリング、或
いはメッキの成膜方法によって形成することにより、低
抵抗金属の膜厚を均一化して、形成されるバンプの高さ
を均一にすることができる。
According to the second aspect of the present invention, the method of depositing the low-resistance metal on the formation substrate is performed by vapor deposition, sputtering, or plating to form a uniform film thickness of the low-resistance metal. In addition, the height of the formed bump can be made uniform.

【0044】従ってバンプを用いる半導体装置の信頼性
を向上することができる。
Therefore, the reliability of the semiconductor device using the bump can be improved .

【0045】請求項3記載の発明により、従来の半導体
装置のAu製バンプを更に電気抵抗の低いCu部材に代
えることにより、半導体装置本体の構成を変える必要が
無く、汎用品の半導体装置を使用して更に低い抵抗で実
装することができる。また、半導体装置の製造コストの
低減も可能である。よって、半導体装置本体の構成を変
える必要が無く、汎用品の半導体装置を使用して半導体
装置を多数搭載する電子機器を安価で提供することがで
きる。また、成型されたバンプを形成基板から速やかに
剥離することができる。よって形成したバンプの変形等
のトラブルを無くして工程の歩留りの向上を図ることが
できる。
According to the third aspect of the present invention, it is not necessary to change the configuration of the semiconductor device body by replacing the Au bump of the conventional semiconductor device with a Cu member having a lower electric resistance, so that a general-purpose semiconductor device can be used. As a result, it can be mounted with a lower resistance . Further, the manufacturing cost of the semiconductor device can be reduced. Therefore, there is no need to change the configuration of the semiconductor device main body, and an electronic device in which a large number of semiconductor devices are mounted using general-purpose semiconductor devices can be provided at low cost. Also, the molded bumps can be quickly removed from the forming substrate.
Can be peeled. Deformation of the formed bumps
To improve process yield by eliminating problems
it can.

【0046】請求項4記載の発明により、低抵抗金属を
形成基板に被着する方法を、蒸着、スパッタリング、或
いはメッキの成膜方法によって形成することにより、低
抵抗金属の膜厚を均一化して、形成されるバンプの高さ
を均一にすることができる。
According to the fourth aspect of the present invention, the method of depositing the low-resistance metal on the formation substrate is performed by forming the film by vapor deposition, sputtering, or plating so that the film thickness of the low-resistance metal is made uniform. In addition, the height of the formed bump can be made uniform.

【0047】従って半導体装置本体の構成を変える必要
が無く、汎用品の半導体装置を使用してバンプを用いる
半導体装置の信頼性を向上することができる。
Therefore, there is no need to change the configuration of the semiconductor device main body, and the reliability of a semiconductor device using bumps using a general-purpose semiconductor device can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例の工程を追って示す概略構成
図である。
FIG. 1 is a schematic configuration diagram showing steps of an embodiment of the present invention.

【図2】本発明の一実施例の工程を追って示す図であ
る。
FIG. 2 is a diagram illustrating a process of an embodiment of the present invention.

【図3】本発明の一実施例で構成した半導体装置の概略
構成図である。
FIG. 3 is a schematic configuration diagram of a semiconductor device configured in one embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 Cu製バンプを有する半導体装置。 2 バンプ形成基板 3 電極 4 転写金属膜(V) 5 バンプ成形用型(レジスト) 6a 低抵抗金属 6 Cu製バンプ 7 半導体装置本体 8 半導体装置本体の電極 1 A semiconductor device having a Cu bump. Reference Signs List 2 bump forming substrate 3 electrode 4 transfer metal film (V) 5 bump forming die (resist) 6a low resistance metal 6 Cu bump 7 semiconductor device body 8 electrode of semiconductor device body

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭63−291428(JP,A) 特開 平6−120228(JP,A) 特開 平4−269834(JP,A) 特開 平2−248066(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/60 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-63-291428 (JP, A) JP-A-6-120228 (JP, A) JP-A-4-269834 (JP, A) JP-A-2- 248066 (JP, A) (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/60

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 電極を有する半導体装置本体を構成する
工程と、 形成基板上に、バナジウム(V)からなる転写金属膜を
設ける工程と、 該転写金属膜上にバンプ形成材を成型する成型用型を設
け、続いて銅(Cu)からなる低抵抗金属を該バンプ形
成材として、該成型用型を用いて該形成基板上の該転写
金属膜上に被着し、バンプを形成する工程と、 該バンプを該形成基板から該電極に転写する工程とより
なることを特徴とする半導体装置の製造方法。
A step of forming a semiconductor device main body having electrodes; a step of providing a transfer metal film made of vanadium (V) on a formation substrate; and forming a bump forming material on the transfer metal film. step mold provided, followed made of copper (Cu) with low resistance metals as the bump forming material, using a molded-type mold and deposited on the transfer metal film on the formed substrate to form a bump Transferring the bump from the formation substrate to the electrode.
【請求項2】 該低抵抗金属を該形成基板に蒸着、スパ
ッタリング、或いはメッキの成膜方法によって形成する
ことを特徴とする請求項1記載の半導体装置の製造方
法。
2. The method according to claim 1 , wherein the low-resistance metal is formed on the formation substrate by a deposition, sputtering, or plating method.
【請求項3】 半導体装置本体に設けられた電極に接合
されるバンプの製造方法において、 形成基板上に、バナジウム(V)からなる転写金属膜を
設ける工程と、 該転写金属膜上にバンプ形成材を成型する成型用型を設
け、続いて銅(Cu)からなる低抵抗金属を該バンプ形
成材として、該形成基板上の該転写金属膜に接着するよ
うに被着し、かつ成型用型を用いて成型してバンプとす
る工程よりなることを特徴とするバンプの製造方法。
3. A method for manufacturing a bump is bonded to the electrode provided on the semiconductor device main body, on the formation substrate, a step of providing a transfer metal film made of vanadium (V), the bump formed on the transfer metal layer provided mold for molding the timber, followed by a low resistance metals made of copper (Cu) as the bump forming material, deposited to adhere to the transfer metal film on the formation substrate, and a molding A method for producing a bump, comprising a step of forming a bump by molding using a mold.
【請求項4】 該低抵抗金属を該形成基板に蒸着、スパ
ッタリング、或いはメッキの成膜方法によって形成する
ことを特徴とする請求項3記載のバンプの製造方法。
4. The method according to claim 1 , wherein said low-resistance metal is deposited on said forming substrate,
Forming by filming method of sputtering or plating
4. The method for manufacturing a bump according to claim 3, wherein:
JP21929494A 1994-09-13 1994-09-13 Semiconductor device manufacturing method and bump manufacturing method Expired - Fee Related JP3294721B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21929494A JP3294721B2 (en) 1994-09-13 1994-09-13 Semiconductor device manufacturing method and bump manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21929494A JP3294721B2 (en) 1994-09-13 1994-09-13 Semiconductor device manufacturing method and bump manufacturing method

Publications (2)

Publication Number Publication Date
JPH0883801A JPH0883801A (en) 1996-03-26
JP3294721B2 true JP3294721B2 (en) 2002-06-24

Family

ID=16733249

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21929494A Expired - Fee Related JP3294721B2 (en) 1994-09-13 1994-09-13 Semiconductor device manufacturing method and bump manufacturing method

Country Status (1)

Country Link
JP (1) JP3294721B2 (en)

Also Published As

Publication number Publication date
JPH0883801A (en) 1996-03-26

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