JP3283891B2 - Clamp circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clamp circuit for clamping a pedestal level of a video signal in, for example, a color television receiver.

[0002]

2. Description of the Related Art Conventionally, in a color television receiver, a pedestal clamp circuit used for direct current reproduction of a luminance signal or the like is configured as shown in FIG.

In FIG. 6, transistors Q3, Q4, transistor Q1 and constant current source I0 forming a differential pair constitute a differential comparison circuit for comparing a predetermined DC voltage V1 with a pedestal voltage of a video signal. The base of the transistor Q3 is connected to a DC power supply V1 for applying a predetermined voltage, and the collector of the transistor Q3 is connected to the transistor Q5 and the resistor R1.
Are connected in series to a DC power supply line Vcc. The collector and the base of the transistor Q5 are commonly connected. The collector of the transistor Q4 is connected to the DC power supply line Vcc via the transistor Q6 and the resistor R2 in series. The collector and the base of the transistor Q6 are commonly connected. The emitters of the transistors Q3 and Q4 are commonly connected, and the common emitter is connected to the reference potential point via the transistor Q1 and the current source I0 in series. The base of the transistor Q1 is connected to a DC power supply V2 for applying a predetermined voltage. Transistor Q1
A transistor Q2 is connected between the emitter and the DC power supply line Vcc, and a negative clamp pulse is supplied from a terminal 2 to the base of Q2.

On the other hand, the base of the transistor Q6 is commonly connected to the base of the transistor Q8. The emitter of the transistor Q8 is connected to the DC power supply line Vcc via the resistor R3. The transistors Q6 and Q8 constitute a current mirror circuit. The collector of the transistor Q8 is connected to the reference potential point via the transistor Q9 and the resistor R5 in series. Further, the transistor Q5
Is commonly connected to the base of transistor Q7. The emitter of the transistor Q7 is connected to the DC power supply line Vcc via the resistor R4. Transistor Q5
, Q7 constitute a current mirror circuit. The collector of the transistor Q7 is connected to the reference potential point via the transistor Q10 and the resistor R6 in series. The collector and emitter of the transistor Q10 are commonly connected, and the base of Q9 and the base of Q10 are commonly connected.

The collector of the transistor Q8 is connected to the external connection terminal T, while being connected to the non-inverting input terminal of a voltage follower having a common connection between the output terminal and the non-inverting input terminal of the operational amplifier OP2. An external capacitor Cx for holding a clamp potential is connected between the external connection terminal T and a reference potential point. Non-inverting amplifier circuit according to the voltage follower and operational amplifier OP1 by the operational amplifier OP2 is to level-shift the video signal input on the basis of the voltage of the external capacitor Cx, the level shifting circuit for supplying to the Q4 base of the differential comparator circuit Make up. An output terminal of the voltage follower is connected to an inverting input terminal of an operational amplifier OP1 via a resistor R8, and a video signal is input from a terminal 4 to a non-inverting input terminal of the operational amplifier OP1. The operational amplifier OP1 and the resistors R8 and R7 form a non-inverting amplifier circuit, the output of which is supplied (feedback) to the base of the transistor Q4 of the front differential comparison circuit, and is derived from the terminal 5 as a video signal output. It has become.

In the above circuit, the operational amplifier OP1
When a video signal is input to the non-inverting input terminal of the non-inverting amplifier circuit, and a negative clamp pulse is input to the base of the transistor Q2 during the pedestal period of the video signal, the transistor Q2 is turned off during that period. The differential comparison circuit is turned on, Q1, Q3 to Q6 and Q8 are turned on, a comparison current flows through Q4, and a current equivalent thereto is Q2.
8, the capacitor Cx is charged. During the video period of the video signal, the transistor Q2 is turned on and the base potential of Q4 is clamped at V1, so that Q3 and Q4 are balanced and no comparison current flows through Q4.
The capacitor Cx holds the potential during the pedestal period. The pedestal potential of the video signal output from the operational amplifier OP1 is the potential supplied to the inverting input terminal of the operational amplifier OP1 (that is, the voltage charged in the capacitor Cx).
, And Q4 of the differential comparison circuit
Feedback to the base. Therefore, the transistors Q3 and Q4 compare the predetermined potential V1 with the pedestal potential of the video signal and supply a comparison current to Cx so that the pedestal potential of the video signal becomes the potential V1. In this way, the clamp operation of the feedback system is performed.

[0007] In the above configuration, the capacitor Cx for holding the clamp potential is an external component of the integrated circuit. When viewed as an integrated circuit, the connection pin T is necessary and the peripheral components are not required. The capacitor Cx was present outside. Clamp current 100μA ~
For several hundred μA, the capacitor Cx for clamping is 0.0
It was 1 μF to several μF.

In recent years, in order to reduce connection pins and external components, attempts have been made to incorporate a clamping capacitor Cx into an integrated circuit to reduce the number of pins and peripheral components.

However, since the capacitance of a capacitor that can be produced by an integrated circuit is at most several tens of pF, in order to obtain a time constant comparable to that of a conventional circuit, the clamp current must be reduced to a very small current (to several μA or less). The need to come up.

However, the capacitor C in the circuit of FIG.
If x is set to several tens of pF and the constant current source I0 is set to several μA, a problem occurs.

That is, when the video signal is a trapezoidal waveform signal, there is a problem that the output of the video signal is sag due to the influence of the collector / sub capacitance of the transistor Q1 and the leakage current.

This will be described with reference to FIG.

FIG. 7 shows transistors Q3 and Q3 of the circuit of FIG.
4 shows an equivalent circuit in a video period of a differential comparison circuit composed of Q1, I0.

During the video period, Q2 is turned on and the base potential of Q4 is clamped at V1, so that Q3 and Q4 are balanced and no comparison current flows through Q4, but the leakage current flows through transistor Q1. Flows. Transistor Q1
If the leak current of the transistor Q1 is I1 and the sum of the collector-sub capacitance and the base-collector capacitance of the transistor Q1 is C0, the differential comparison circuit of FIG. 6 can be expressed as shown in FIG.

FIG. 8 shows signal waveforms at various parts of the circuit when a rectangular wave video signal is input. (a) is the waveform of the video signal input supplied to the terminal 4, and (b) is the transistors Q3 and Q3.
(C) is the waveform of the collector current I4c of the transistor Q4, (d) is the voltage waveform of the capacitor Cx, and (e) is the base voltage waveform of the transistor Q4 (terminal 5).
Of the video signal output of FIG.

The value of the capacitance C0 in the integrated circuit is 0.1
pF-0. Several pF. If the clamping capacitor Cx in the integrated circuit is selected to be 20 pF, the collector current I4c of Q4 flows as shown in FIG. 8 by the capacitance C0 (the current of emitter peaking due to C0 flows), and Cx is the rectangle of FIG. 8 (e). When the wave rises, charging is performed by the collector current I4c, and a step Vcx occurs in the voltage waveform of Cx as shown in FIG. 8D.

The value of Vcx is determined by the capacitances C0 and Cx, and the peak value Vin of Q4, and Vcx becomes approximately Vcx = Vin. (C0 / Cx). Therefore, based on the step Vcx, the operational amplifier O
At the output terminal of the amplifier circuit by P1 (that is, the base of Q4), a sag of .DELTA.V0 occurs after the rise of the rectangular wave pulse as shown in FIG. 8 (e). At this time, ΔV0 becomes approximately ΔV0 = − (R7 / R8) · Vcx = − (R7 / R8) · Vin · (C0 / Cx). Now, let Vin be 3 Vp-p, R7 = R8, and C0 be.
If 1 pF and Cx are 20 pF, then .DELTA.V0 = -15 mVp-p.

[0018]

As described above, in the conventional circuit configuration, when a rectangular wave is input during a video period,
It is not preferable because sag occurs in the video signal output after the rise of the rectangular wave pulse.

Therefore, the present invention is to solve the above-mentioned problem, and it is desirable to perform pedestal clamping without producing sag in a video signal output even when a capacitor formed in an integrated circuit is used as a clamping capacitor. It is an object of the present invention to provide a clamp circuit that can perform the above operation.

[0020]

According to the present invention, there is provided a clamp circuit comprising first and second transistors having emitters connected in common.
A video signal on the base of the first transistor.
And a predetermined voltage is applied to the base of the second transistor.
Voltage to adjust the pedestal potential of the video signal to a predetermined voltage.
And a differential comparison circuit that outputs a comparison current .
A third transistor coupled to the emitter of the second transistor;
It has a transistor and a clamp pulse input terminal.
In response to the clamp pulse, the third transistor is turned on.
Switch means for conducting and turning on the differential comparison circuit; and a capacitor charged by a comparison output current from the differential comparison circuit and holding a clamp potential
If, based on the potential before Symbol capacitor, and the level shifting pedestal potential of the video signal supplied as an input, while the feedback to the first transistor of the differential comparator circuit, the output of the pedestal clamp video signal
From the differential comparison circuit
Current path for transmitting the comparison current of
The emitter-collector current path is located at
A resistor is connected between the emitters to reduce the base-emitter voltage.
VBE and the resistance value R, the comparison current
Is higher than VBE / R and the comparison voltage is higher than a predetermined value.
A transistor for transmitting only the current to the capacitor.
And a current offset means .

[0021]

According to the present invention, a predetermined potential is compared with a pedestal potential of a video signal by the differential comparison circuit, and a circuit for supplying a comparison current to the capacitor is provided with a current offset function so that the video signal is offset. Even if a rectangular wave-shaped pulse is input, if the value of the current offset is selected to be larger than the peak value of the current generated in the differential comparison circuit by the pulse, the current based on the pulse may be supplied to the capacitor. As a result, no step occurs in the voltage waveform of the capacitor. Therefore, even if the capacitor Cx is provided in the integrated circuit, sag does not occur in the video signal output due to the influence of the collector / sub capacitance of the transistor Q1 and the leak current.

[0022]

An embodiment will be described with reference to the drawings. FIG. 1 is a circuit diagram schematically showing a clamp circuit according to one embodiment of the present invention. In FIG. 1, the same parts as those in FIG.

In FIG. 1, the transistors Q3 and Q4 forming a differential pair, the transistor Q1 connected to the common emitter thereof, and the constant current source I0 are used to compare a predetermined voltage V1 with a pedestal potential of a video signal. A comparison circuit is formed, and a transistor Q2 paired with the transistor Q1 turns on and off the differential comparison circuit depending on the presence or absence of a clamp pulse input supplied to its base. A negative clamp pulse is input from the terminal 2 to the base of the transistor Q2. Conventionally, when a rectangular pulse is supplied to the base of the transistor Q4 while the transistor Q2 is turned on (that is, during the video signal period), a collector current due to the pulse flows through the transistor Q4 and a step difference occurs in the voltage of the capacitor Cx. There was a problem that it occurred. Therefore, FIG. 1 shows that the circuit 1 for transmitting the comparison current of the differential comparison circuit to the capacitor Cx has a current offset characteristic so that only the comparison current having a predetermined current value or more is transmitted to the capacitor. It is a feature.

The comparison current output of the transistors Q3 and Q4 is output to the collectors of the transistors Q9 and Q10 forming a current mirror circuit through the current offset circuit 1 and supplied to the capacitor Cx. The level shift circuit 3 receives a video signal from a terminal 4 and level-shifts the video signal based on the voltage of a capacitor Cx to supply the video signal to the base of a transistor Q4 of the differential comparison circuit. Output as a video signal.

FIG. 2 shows the input / output characteristics of the current offset circuit 1. In FIG. 2, the current flowing through the collectors of the transistors Q4 and Q3 is the input current, and the current flowing through the transistors Q8 and Q7 (see FIGS. 3, 4 and 5) is the output current. As shown in the input / output characteristics, as long as the input current does not exceed a preset current offset value,
The output current cannot be obtained. In other words,
No current is supplied to the capacitor Cx with a comparison current of a certain current value or less.

In the above arrangement, the predetermined potential is compared with the pedestal potential of the video signal by the differential comparison circuit.
When the comparison current is supplied to the capacitor Cx, by passing through the current offset circuit 1,
Even when a rectangular pulse is input to the video signal, if the value of the current offset is selected to be larger than the peak value of the collector current (comparison current) of the transistor Q4 due to the pulse, the comparison current based on the pulse is supplied to the capacitor Cx. Since no voltage is supplied, no step occurs in the voltage waveform of the capacitor Cx. Therefore, even when the capacitor Cx is provided in the integrated circuit, sag does not occur in the video signal output due to the influence of the collector / sub capacitance of the transistor Q1 and the leak current.

FIG. 3 is a circuit diagram showing one embodiment of the clamp circuit configuration of FIG.

In FIG. 3, the same parts as those in FIG. The difference from FIG. 6 is that the transistor Q
5, a resistor R9 is connected between the base and the emitter, and a resistor R10 is connected between the base and the emitter of the transistor Q6. The portion indicated by the broken line frame is a portion having a current offset characteristic. Other configurations are the same as those in FIG. According to FIG. 1, transistors Q5 and Q6
, Q7, Q8 and resistors R1 to R4, R9, R10 correspond to the current offset circuit 1, and the operational amplifiers OP1, OP2
The resistors R7 and R8 correspond to the level shift circuit 3.

In the above clamp circuit, the resistors R9,
In order for the transistors Q7 and Q8 to be turned on by R10, the collector currents I3c and I4c of the transistors Q3 and Q4 are determined by setting the base-emitter voltages of the transistors Q5 and Q6 to VBE and the resistance values of the resistors R9 and R10. Are R9 and R10, I3c≥VBE / R9, I4c
.Gtoreq.VBE / R10. Therefore, conversely, V
By setting BE / R9 and VBE / R10 higher than the peak values of the collector currents I3c and I4c (see FIG. 8C), it is possible to prevent the sag from being generated in the video signal output.

Specifically, I0 is set to 100 μA, and R9 = R
10 = 50 kΩ, R1 = R2 = 1 kΩ, R3 = R4 = 10
This can be achieved by selecting 0 kΩ.

FIG. 4 is a circuit diagram showing another embodiment of the clamp circuit configuration of FIG. In FIG. 4, the same parts as those in FIG. 6 is different from the collectors of the transistors Q3 and Q4 and the transistors Q5 and Q5.
A circuit having a current offset characteristic comprising transistors Q11 and Q12 and resistors R9 and R10 is inserted between each collector of Q6. The resistor R9 is connected between the base and the emitter of the transistor Q11, the resistor R10 is connected between the base and the emitter of the transistor Q12, and both bases of the transistors Q11 and Q12 are connected to the DC voltage source V3.

The other structure is the same as that of FIG. According to FIG. 1, transistors Q5, Q6, Q7, Q8,
Q11, Q12, DC power supply V3 and resistors R1 to R4, R9,
R10 corresponds to the current offset circuit 1, and the operational amplifier OP
1, OP2 and resistors R7, R8 correspond to the level shift circuit 3.

In the above circuit, assuming that each base-emitter voltage of the transistors Q11 and Q12 is VBE, VBE / R9,
If VBE / R10 is set to be larger than the peak values of the collector currents I3c and I4c (see FIG. 8C), no current is supplied to the capacitor Cx during the video period, and no sag occurs in the video signal output. .

FIG. 5 is a circuit diagram showing another embodiment of the clamp circuit configuration of FIG. In FIG. 5, FIG.
The same parts as those described above are denoted by the same reference numerals and described. 6 is different from the transistor Q5 on the output current side of the current mirror circuit formed by the transistors Q5 and Q7, and the transistor Q5.
6, a circuit having a current offset characteristic is inserted in the transistor Q8 on the output current side of the current mirror circuit formed by Q8. That is, a circuit having current offset characteristics including transistors Q11 and Q12 and resistors R9 and R10 is inserted between the collectors of the transistors Q7 and Q10 and the collectors of the transistors Q8 and Q9. As in the case of FIG. 4, the resistor R9 is connected between the base and the emitter of the transistor Q11, the resistor R10 is connected between the base and the emitter of the transistor Q12, and the bases of the transistors Q11 and Q12 are both connected to the DC voltage source V3. I have. Other configurations are the same as those in FIG. 1, the transistors Q5, Q6, Q7, Q8, Q11, Q12, the DC power supply V3 and the resistors R1 to R4, R9, R10 correspond to the current offset circuit 1, and the operational amplifiers OP1, OP2, R7, R8 corresponds to the level shift circuit 3.

In the above circuit, when the base-emitter voltage of each of the transistors Q11 and Q12 is VBE, VBE / R9,
If VBE / R10 is set to be larger than the peak values of the collector currents I3c and I4c (see FIG. 8C), no current is supplied to the capacitor Cx during the video period, and no sag occurs in the video signal output. .

[0036]

As described above, according to the present invention, even if a capacitor formed in an integrated circuit is used as a capacitor for clamping a pedestal potential, sag does not occur depending on the contents of a video signal. Since a clamping capacitor can be formed in the integrated circuit, the number of pins of the integrated circuit can be reduced, and external components around the integrated circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a schematic configuration of a clamp circuit according to the present invention.

FIG. 2 shows input / output characteristics of the current offset circuit of FIG .
Characteristic diagram.

FIG. 3 is a circuit diagram showing one embodiment of the configuration of FIG . 1;

FIG. 4 is a circuit diagram showing another embodiment of the configuration of FIG. 1;

FIG. 5 is a circuit diagram showing another embodiment of the configuration of FIG. 1;

FIG. 6 is a circuit diagram showing a conventional clamp circuit.

FIG. 7 is an equivalent circuit diagram of the differential comparison circuit in FIG. 6 during a video period.

8 is a signal waveform diagram of each section of the circuit when a rectangular pulse is input to the circuit of FIG. 6 during a video period.

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-279674 (JP, A) JP-A-2-82873 (JP, A) JP-A-3-117180 (JP, A)

Claims (1)

(57) [Claims] 1. A first and a second transistor having commonly connected emitters.
A transistor and a base of the first transistor
Supply a video signal to the base of the second transistor
Supply a predetermined voltage to adjust the pedestal potential of the video signal.
A differential comparison circuit for comparing the voltage with a constant voltage and outputting a comparison current; and a differential comparison circuit coupled to the emitters of the first and second transistors.
3 transistors and clamp pulse input terminals
And the third transistor responds to the clamp pulse.
To conduct static, switch means for turning on the operation of the differential comparator circuit, is charged by a comparison output current from the differential comparator circuit, a capacitor for holding the clamp potential, based on the potential before Symbol capacitor, Level shift means for level-shifting a pedestal potential of a video signal supplied as an input and feeding back the pedestal-clamped video signal to the first transistor of the differential comparison circuit , and And transmitting the comparison current from the differential comparison circuit to the capacitor.
The emitter / collector current path is
And a resistor is connected between the base and the emitter.
The source-emitter voltage is VBE, and the value of the resistor is R.
When the comparison current is VBE / R or more,
Only the comparison current of a predetermined value or more is transmitted to the capacitor.
And a current offset means having a transistor to perform the operation.