JP3065459B2 - Offset removal circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an offset removing circuit in a video signal processing circuit, and more particularly to an output offset removing circuit in a video signal processing circuit for a liquid crystal display device.

[0002]

2. Description of the Related Art When a liquid crystal display device is driven, a DC voltage cannot be applied to a liquid crystal for a long time.
The video signal shown in FIG. 2 is inverted and used every horizontal period as shown in FIG. At this time, by applying a voltage corresponding to the average voltage E of the video signal indicated by the broken line 65 to the opposite electrode of the liquid crystal, the application of DC is prevented. Therefore, it is necessary to prevent the offset of the output of the video signal so as not to cause a difference between the average voltage of the output video signal and the voltage of the counter electrode.

For this reason, as shown in FIG. 10, the output side of a level shift circuit 61 connected to the output side of an inverting amplifier 60 for inverting an input video signal every horizontal period, and a low-pass circuit comprising a capacitor C10 and a resistor R10. Filter 6
3 to generate an average voltage of the output video signal, compare the average voltage with the reference voltage _VREF by the comparator 64, and control the level shift circuit 61 based on the comparison result to shift the DC level of the output. The average voltage E of the video signal is equal to the reference voltage V
_It was controlled to match _REF .

[0004]

However, this conventional circuit requires a resistor R10 of the low-pass filter 63 having a large value of several hundred KΩ and a capacitor C10 having a large value of several μF in order to reduce the AC component. This low-pass filter 63 could not be formed in an integrated circuit. For this reason, external terminals were provided on the integrated circuit, and discrete resistors and capacitors were externally formed to form a low-pass filter.Therefore, the number of components increased and the connection work was also required. there were.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide an offset removing circuit capable of removing an offset without using external components.

[0006]

In order to achieve the above object, according to the present invention, the intermediate level of the video signal is controlled such that the intermediate level of the video signal inverted every horizontal period becomes a predetermined value. In the offset removing circuit, a pulse superimposing circuit for superimposing a pulse on the pedestal portion of the video signal before inversion every horizontal period, and inverting the video signal on which the pulse is superimposed every horizontal period around the leading edge level of the pulse An inverting circuit, a means for leading the output of the inverting circuit to an output terminal, a sample and hold circuit for sampling and holding the leading edge level of the pulse from the output of the inverting circuit, and comparing the output of the sample and hold circuit with a reference voltage. The output of the inverting circuit is displayed by the comparison output.
Means for controlling the DC output level of the image signal to a predetermined value.

In the present invention, the pedestal of the video signal is clamped in the offset removing circuit for controlling the intermediate level of the video signal so that the intermediate level of the video signal inverted every horizontal period becomes a predetermined value. A pedestal clamp circuit, a pulse superimposition circuit for superimposing a pulse having a peak value according to a brightness control voltage on each pedestal portion of the pedestal-clamped video signal, and a brightness control of the video signal on which the pulse is superimposed. An inverting amplifier circuit that differentially amplifies the voltage and inverts every horizontal period to make the peak of the pulse an intermediate level of the video signal; and a level shifter that shifts the intermediate level of the output of the inverting amplifier circuit. A circuit for deriving an output video signal of the level shift circuit to an output terminal; A sample and hold circuit that samples and holds the pulse portion of the video signal output from the video signal circuit, and a comparator that compares the output of the sample and hold circuit with a reference voltage and applies the comparison output to the level shift circuit as a control voltage Is provided.

Further, according to the present invention, in the offset removing circuit for controlling the intermediate level of the video signal so that the intermediate level of the video signal inverted every horizontal period becomes a predetermined value, the pedestal of the video signal is reduced. A pedestal clamp circuit for clamping, a pulse superimposing circuit for superimposing a pulse of a predetermined peak value in each horizontal period on a pedestal portion of the pedestal-clamped video signal, and a video signal on which the pulse is superimposed every horizontal period An inverting circuit for inverting, a level shift circuit for shifting a DC level of an output of the inverting circuit, means for leading an output video signal of the level shift circuit to an output terminal, and a video signal output from the level shift circuit. A first sample-and-hold circuit that samples and holds the pulse portion of the inversion period; A second sample-and-hold circuit for sampling and holding the pulse portion of the non-inverting period of the video signal output from the device, means for extracting an intermediate voltage of the outputs of the first and second sample-and-hold circuits, And a comparator for applying the comparison output as a control voltage to the level shift circuit.

Further, according to the present invention, in the offset removing circuit for controlling the intermediate level of the video signal so that the intermediate level of the video signal inverted every one horizontal period becomes a predetermined value, the pedestal of the video signal is reduced. A pedestal clamp circuit for clamping, a pulse superimposing circuit for superimposing a pulse on the pedestal portion of the pedestal-clamped video signal every horizontal period, and a differentially amplifying the video signal on which the pulse is superimposed and at every one horizontal period An inverting amplifier circuit that inverts and outputs the inverted signal; a level shift circuit that shifts an intermediate level of the output of the inverting amplifier circuit; A sample hold circuit and a non-inversion period of a video signal output from the level shift circuit A second sample-and-hold circuit that samples and holds the pulse portion is compared with the outputs of the first and second sample-and-hold circuits, and the peak value of the pulse is set to an intermediate level of the video signal by the comparison output. Means for controlling the differential amplification in the inverting amplifier circuit, and comparing the output of the first or second sample and hold circuit with a reference voltage, the intermediate output level of the inverting amplifier circuit being set to a predetermined value by the comparison output Means for controlling the level shift circuit.

The peak value of the pulse superimposed by the pulse superimposing circuit is varied to adjust the brightness. Further, a white peak limiter circuit for limiting a white peak level of a video signal pedestal clamped by the pedestal clamp circuit is provided, and a peak value of a pulse superimposed by the pulse superimposition circuit is determined by a pedestal clamp voltage and a white peak. The intermediate voltage of the limiter voltage is set. Further, a pedestal clamp voltage in the pedestal clamp circuit,
Means is provided for setting the peak value of the pulse superimposed by the pulse superimposing circuit so that the potential difference therebetween becomes independent of the fluctuation of the power supply voltage.

[0011]

According to this structure, the signal to be compared with the reference voltage to generate a signal for controlling the intermediate level (DC) of the video signal is the peak value (DC voltage) of the pulse. A low-pass filter is not required to supply the capacitor, and only a holding capacitor is needed.If the leakage current during holding is kept small, the capacitance value will be small. Good. Therefore, it can be easily formed in an integrated circuit.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the embodiments shown in the drawings. First, in FIG. 1 showing the first embodiment, 1
Is a pedestal clamp circuit for fixing the pedestal of the video signal shown in FIG. 2A to a predetermined DC voltage value, and the pedestal clamped video signal is supplied to the contact (a) of the switch circuit 2 by this circuit. Switch circuit 2
Is driven by a switching signal Sa shown in FIG. 2B. The low level period of the switching signal Sa is set to the contact (a) side, and the high level period is set to the contact (b) side.

[0013] 3 is a voltage generating circuit for generating a predetermined DC voltage V _P corresponding to the brightness control voltage V _B. It is assumed that V _P = V _B to simplify the description. Since the switch circuit 2 switches to the contact (b) side during the pedestal period of the video signal, the voltage V _{P is} applied to the pedestal portion as shown in FIG.
Are superimposed in a pulsed manner. In other words, the switch circuit 2 and the voltage generation circuit 3 constitute a circuit for superimposing a pulse on a pedestal portion of a video signal. As described above, the video signal in which the pulse is superimposed on the pedestal portion is transmitted to the inverting amplifier 4 at the next stage.

The inverting amplifier 4 inverts the video signal every horizontal period according to the inversion control signal Sb shown in FIG. Inverting amplifier 4 also operates to control the black level (Vc) of the video signal by the brightness control voltage V _B obtained by the variable voltage source 5. Black level (V
When c) is raised by the brightness control, the luminance signal portion is also raised. Conversely, when the black level (Vc) decreases, the luminance signal portion also decreases.

[0015] In the inverting amplifier 4, the difference between the signal voltage and brightness control voltage V _B is amplified, the output is the difference between the intermediate voltage V _M and the black level. In other words, the signal output when the V _B and the signal voltage is the same voltage is an intermediate voltage V _M becomes,
Away from the intermediate voltage V _M as the V _B increases. This is because they are matched to V _P to V _B in this embodiment, the tip of the output video signal is a pulse as shown in FIG. 2 (d) is an intermediate voltage V _M, be inverted, that The relationship does not change. In addition, the V _P also by changing the brightness control voltage V _B V
If That raise to the same change is _B, pulse tip is always intermediate voltage V _M. These are described in FIG.
Is V _B is applied to the differential pair to the base of the transistor Q14 constituting the, 2 to the base of the other transistor Q13
It will be easy to understand when considering the output of the differential circuit when a video signal is input as shown in FIG.

Reference numeral 6 denotes a level shift circuit for shifting the DC level of the video signal output from the inverting amplifier 4, and its output is supplied to an output terminal 7 and supplied to a sample and hold circuit 8. The sample and hold circuit 8 samples the peak value (intermediate voltage V _M ) of the pulse added to the video signal based on the sampling signal S _C shown in FIG. 2F, and holds the sampled signal. The hold output is supplied to the comparator 9 by the reference voltage V.
It is compared with _REF, and controls so that the comparison output becomes an intermediate voltage V _M of the video signal applied to the level shift circuit 6 to a reference voltage V _REF.

Next, FIGS. 3 to 6 showing specific circuit configurations of the respective parts in FIG. 1 will be described. FIG. 3 shows a pedestal clamp circuit 1 and a switch circuit 2. In FIG. 3, reference numeral 10 denotes an input terminal to which a video signal is applied, and 11 denotes an amplifier having a non-inverting input terminal connected to the input terminal 10. 12 is a PNP transistor Q forming a differential pair.
2, a differential amplifier circuit comprising a constant current source 13 and a load circuit 14, and the load circuit 14 is composed of NPN transistors Q4 and Q5 connected in a current mirror. The video signal is applied to the base of one transistor Q2 forming a differential pair from the amplifier 11 at the preceding stage, and the constant voltage V _C is applied to the other transistor Q3.

The emitters of the transistors Q2 and Q3 are connected to the emitter of a PNP transistor Q6, and the base of the transistor Q6 is supplied with a switching signal Sa. The collector of the transistor Q6 is connected to the ground. The capacitor C1 and the base of the transistor Q1 are connected to the output point of the differential amplifier circuit 12 (the collector connection point of the transistors Q3 and Q5). The collector of the transistor Q1 is connected to the DC power supply V _CC , and the constant current source 15 is connected to the emitter. The emitter is connected to the inverting input terminal of the amplifier 11.

The operation of the pedestal clamp circuit 1 will be described. First, the video signal amplified by the amplifier 11 is applied to the base of the transistor Q2 in the differential amplifier circuit 12, and is compared with the base voltage V _C of the transistor Q3. Video signal is higher than V _C decreases the collector current Ia of the transistor Q2 (the collector current of the ≒ Q5) is the collector current Ib of the transistor Q3 increases. Ib-
Since the capacitor C1 is charged with the current Ia, the base of the transistor Q1 rises, the inverting input of the amplifier 11 rises, and the output voltage of the amplifier 11 tries to decrease. Thus, to match the output of the amplifier 11 to V _C. The circuit composed of the transistors Q2 to Q5 corresponds to the switching signal S shown in FIG.
In the other period, the transistor I6 is turned on and the transistors Q2 and Q3 are turned off, so that the currents Ia and Ib do not flow, and the capacitor C1 keeps the voltage until the next switching signal goes high. Hold.

As described above, the pedestal portion has the voltage V
_The video signal clamped at _C enters the switch circuit 2.
The switch circuit 2 includes transistors Q7 to Q12 and the like. PNP transistors Q7 and Q8 have emitters and collectors connected to each other. The collector is connected to ground, and the emitter is a constant current source 16.
And the base of the transistor Q9. A circuit having the same configuration as the circuit including the transistors Q7 and Q8 and the constant current source 16 is also provided on the right side. This is the circuit composed of the transistors Q11 and Q12 and the constant current source 17.

The emitters and collectors of NPN-type transistors Q10 and Q9 whose bases are connected to the emitters of transistors Q11 and Q12 are also connected. Their collectors are connected to a power supply line 18 and their emitters are connected to a constant current source 19 and to an inverting amplifier 4 of FIG.
The base of the transistor Q7 is supplied with the video signal pedestal clamp with pedestal clamp circuit 1 described above, although the base of the transistor Q12 is given a DC voltage V _P, the switching circuit 2 is DC voltage and the video signal one of V _P performs the switching operation to derive the alternatively output line 20. Transistors Q8, Q11
Through terminals 21 and 22, respectively.
2, the relationship between these voltages VS1, VS2 and the switching signal Sa is as follows. That is,
When Sa is at a high level, VS1 is at a low level and VS2
Becomes high level (first mode), and when Sa is low level, VS1 becomes high level and VS2 becomes low level (second mode).

[0022] First, in a first mode transistor Q7 is OFF, the transistors Q10, Q12 because the ON, V _P from the emitter of the transistor Q10 is outputted to the output line 20. At this time, since the base-emitter voltage V _BE of the transistors Q12 and Q10 cancel each other, V _P to the emitter (hence the output line 20) is the base voltage of the transistor Q12 of the transistor Q10, that the output as it Become. In the second mode, the transistors Q7 and Q9 are ON and the transistor Q1
Since 0 and Q12 are OFF, the output of the amplifier 11 is led to the output line 20. Although V _P is shown as a fixed voltage, as described in FIG. 1, changes according to the V _P is brightness control voltage change of V _B, VP
= VB.

FIG. 4 shows an inverting amplifier 4 and a level shift circuit 6.
Is shown. Referring to FIG.
3 and a switch unit 24. The amplifying unit 23 is configured as a differential amplifier, and a differential pair transistor Q
13, Q14 and a resistor R connected between their emitters
1. Consisting of constant current sources 26 to 29, a video signal is supplied to the base of the transistor Q13 through the output line 20 from the switch circuit 2 in FIG.
The 4 base brightness control voltage V _B is applied.

The switch unit 24 is connected as shown in FIG.
The switching signals VS3 and VS4 are supplied to terminals 30 and 31, respectively. Assuming that I ₆ = 1 ₇ , I ₈ = I ₉ , I ₆ > I ₈ , and I ₇ > I ₉ , then Ic = I ₇ −I ₉ and Id = I ₆ −I ₈ . Also,
V _B is set to be higher than the base voltage of the transistor Q13. In this case, a current flows from the transistor Q14 to the emitter of the transistor Q13 through the resistor R1, so that Ic decreases and Id increases. The transistors Q15 to Q18 work to flow one of Ic and Id to the level shift circuit 6 side.

The level shift circuit 6 has a DC voltage V
_1, a transistor Q19 to which ₁ is given, a current mirror-connected current source circuit 25 connected to the emitter of the transistor Q19, a resistor R2 connected to the collector, and a base connected to the collector and the resistor R2 of the transistor Q19. The emitter has a constant current source 26A and an output terminal 27A.
Is connected to the transistor Q22. The current source circuit 25 includes a transistor Q21 to which a control current I _IN is supplied, and a transistor Q20 having a base connected in common with the transistor Q21. The collector of the transistor Q20 is connected to the transistor Q19.
Connected to the emitter. The output of the inverting amplifier circuit 4 flows to the point K.

During the non-inversion period of the video signal, VS3 is at the high level and VS4 is at the low level, the transistors Q15 and Q18 of the switch section 24 are turned on, and Ic flows to the point K. Since Ic is decreasing, If (Ie-Ic) increases, and the output of the terminal 27A decreases. Conversely, during the inversion period of the video signal, VS3 goes low and VS4 goes high, turning on the transistors Q16 and Q17, so that Id flows to the point K, If (Ie-Id) decreases, and the terminal The output of 27A rises. The voltage at the terminal 27A becomes the inverted / non-inverted black level. The above operation is reversed when a signal enters the transistor Q13 and rises. The output at the time of inversion falls in accordance with the signal and rises at the time of non-inversion. Since such inversion / non-inversion is performed every horizontal period, FIG.
(D). Control current I _IN to current source circuit 25
When Ie increases, Ie increases and the output decreases, and when it decreases, the output voltage increases. Intermediate voltage V _M of the thus output terminal 27A is adjusted.

FIG. 5 shows the sample and hold circuit 8. This circuit includes transistors Q24 and Q2 forming a differential pair.
5 and transistors Q2 connected to their collectors
2A, Q23, resistors R3, R4, transistor Q26 connected to the emitters of transistors Q24 and Q25,
A voltage source 33 for applying a DC voltage V2 to the base of the transistor Q26, a transistor Q27 forming a differential pair with the transistor Q26, a constant current source 34, a transistor Q28 connected to the base of the transistor Q27, and a collector and an emitter of the transistor Q28. It comprises resistors R5 and R6 connected to each other, a hold capacitor C2 connected to the base and collector of the transistor Q25, and a voltage follower 36.

The transistors Q22A and Q23
Is a current mirror connection. The collector of the transistor Q27 is connected to the collector of the transistor Q23. The terminal 32 is supplied with a video signal from the above-described level shift circuit 6, and the terminal 35 is supplied with a sampling signal Sc.

First, when the sampling signal Sc is input to the terminal 35, the transistor Q28 is turned on and the base voltage of the transistor Q27 is reduced.
7 is turned off, and the transistor Q26 is turned on. As a result, the transistors Q22A to Q25
N, and the same voltage as the input of the terminal 32 is applied to the transistor Q25.
Obtained at the base of. Thereby, the capacitor C2 is charged.

When the sampling signal disappears, the transistor Q28 is turned off, and the voltage V ₃ (> V ₂ ) is applied to the base of the transistor Q27, so that the transistor Q27 is turned on. Therefore, the transistor Q26 is turned off, and the transistors Q22A to Q25 are also turned off.
Becomes Therefore, in this state, the input of the terminal 32 is cut by turning off the transistors Q22A to Q25, and has no effect on the capacitor C2. The capacitor C2 stores the previously charged voltage until the next sampling signal is input. Since the holding capacitor C2 has a small leakage current at the time of holding, the capacitance value may be small.

The voltage held in the capacitor C2 is led out to the output terminal 37 via the voltage follower 36 and supplied to the comparator 9 shown in FIG. The comparator 9 includes a pair of PNP transistors Q29 and Q30 and the constant current source 3
8 and a reference voltage source 39 for applying a reference voltage V _REF to the base of the transistor Q30. The DC voltage from the sample and hold circuit 8 is received at the base of the transistor Q29, and this is compared with the reference voltage V _REF. Then, the current I _IN as a result of the comparison is supplied to the transistor Q21 in FIG.

Next, a second embodiment shown in FIG. 7 will be described. In FIG. 7, the same parts as those in FIG. 1 are denoted by the same reference numerals, and redundant description will be avoided. In the second embodiment, the pulse V _P superimposed on the pedestal portion of the video signal
Is independent of the brightness control voltage V _B ,
Brightness is not interlocked with the change in the control voltage V _B. Accordingly, in the waveform of FIG. 8D obtained by inverting the video signal on which the pulse _VP is superimposed by the inverting amplifier 4,
The positions of the pulse peak value (level 1) of the inverted waveform and the pulse peak value (level 2) of the non-inverted waveform do not always match. Therefore, two sample hold circuits 8a and 8b are provided after the level shift circuit 6, and their outputs are given to the comparator 9 from the connection middle point (c) of the two resistors R having the same value. . The voltage at the middle point (c) is shown in FIG.
This is an intermediate voltage between level 1 and level 2 in (d). This voltage is compared with a reference voltage _VREF, and the level shift circuit 6 is controlled by the comparison output. Sampling pulses shown in FIGS. 8F and 8G are applied to the sample hold circuits 8a and 8b, respectively. 7 is also specifically configured according to the circuits of FIGS. 3 to 6. However, V _P is set independently to V _B.

In the first and second embodiments, since the pulse is superimposed on the pedestal portion, when the brightness is reduced by the inverting amplifier 4, even if the upper and lower portions of the video signal are limited as shown in FIG. , the pulse V _P remains, there is no hindrance to offset removal operation.

Next, a third embodiment shown in FIG. 12 will be described. In FIG. 12, the same parts as those in FIGS. 1 and 7 are denoted by the same reference numerals, and redundant description will be avoided. In the third embodiment, instead of the brightness control voltage V _B, 2 single sample and hold circuit 8a provided after the level shift circuit 6, the comparison output 8b, to perform control of the differential amplifier of the inverting amplifier 4 Like that. for that reason,
Two comparators 9a and 9b are provided, and the comparator 9 compares the outputs of the two sample and hold circuits 8a and 8b.
The output of “a” is given to the inverting amplifier 4. Then, inverted by the comparison output, so that the pulse peak value of the non-inverted waveform (voltage V _P) is an intermediate voltage V _M of the video signal to match,
The differential amplification in the inverting amplifier 4 is controlled.

On the other hand, the output of the comparator 9b for comparing the output of the sample hold circuit 8a with the reference voltage V _REF is given to the level shift circuit 6. The intermediate voltage V _M is the reference voltage V _REF at the output of inverting amplifier 4 according to the comparison output
The level shift circuit 6 is controlled so that Here, the comparator 9b is reversed, since the pulse peak value of the non-inverted waveform is in the intermediate voltage V _M coincide, one of the sample-and-hold circuits 8a, 8b (in this case, 8a)
_Is compared with the reference voltage V _REF .
In addition, these sample and hold circuits 8a and 8b have
As in (f) and (g), the sampling pulses shown in FIGS. 13 (f) and (g) are applied, respectively.

The circuits of the respective parts shown in FIG. 12 are configured specifically according to the circuits shown in FIGS. 3 to 6. For example, the inverting amplifier 4 and the level shift circuit 6 in the third embodiment are The configuration is as shown in FIG. In the figure, the pedestal of the video signal shown in FIG.
And a switch circuit 2 on the pedestal.
In the video signal as shown in FIG. 13 obtained by superimposing the voltage V _P in pulses (c) is supplied through the output line 20. The sample and hold circuit 8a is provided at the base of the transistor Q14,
Output voltage V _R from the comparator 9a which compares the DC voltage output from 8b is supplied.

For example, when the DC voltage from the sample and hold circuit 8b is larger, the voltage V _R supplied to the base of the transistor Q14 by the comparator 9a becomes smaller, and the pedestal level (V _C) of the output video signal is reduced. ) becomes closer to the intermediate voltage V _M. Conversely, when the DC voltage from the sample and hold circuit 8a is higher, the voltage V _R supplied to the base of the transistor Q14 from the comparator 9a is higher, and the pedestal level of the output video signal ( V _C ) will _deviate from its intermediate voltage V _M. As a result, the output video signal from the inverting amplifier 4 is inverted, the tip of the non-inverting pulse is a waveform as shown in FIG. 13 which was an intermediate voltage V _M (e) to coincide. here,
Switching signals VS3 and VS4 applied to terminals 30 and 31
FIG. 13D shows that the inversion control signal Sb is at a high level.
VS3 <VS4, and VS3> VS4 when Sb is at the low level. Thereby, the transistor Q
15 to the transistor Q18 function to flow one of Ic and Id to the level shift circuit 6 side.

In the same figure, a current I _IN as a result of the comparison is supplied from a comparator 9b to the collector side of a transistor Q21 of the level shift circuit 6, and for example, a DC voltage from a sample hold circuit 8a is applied to a reference voltage V _REF
As I _IN increases, Ie increases and the output at terminal 27A decreases. Here, reference numeral 40 denotes a buffer circuit comprising a transistor Q22 and a constant current source 26A connected to its emitter as shown in FIG.

[0039] Although in the third embodiment is shown as a voltage of a fixed voltage V _P which is pulsed manner superimposed on the pedestal portion of the video signal may be made to perform the brightness adjustment in the variable. That is, by increasing the voltage V _P to be superimposed, inverted became vertically symmetrical with respect to the intermediate voltage V _M, the potential difference between both the pedestal level of the noninverting output is increased (see FIG. 15 (a)), the brightness Becomes lower. Conversely, reducing the voltage V _P to be superimposed, the potential difference between the pedestals is decreased (see FIG. 15 (b)), the brightness is high, the offset removing operation by the pulse voltage V _P in any case It can be performed without hindrance.

In the third embodiment, the brightness of the output video signal is fixed, that is, the pedestal level of the inverted and non-inverted output is fixed, and the white peak limiter voltage of the inverted output is set to the pedestal level of the non-inverted output. If the white peak limiter voltage of the non-inverted output matches the pedestal level of the inverted output,
The output voltage can be reduced while the amplitude between the pedestal levels of the non-inverted output is as large as possible and the video signal is as large as possible for high contrast. Specifically, as shown in FIG. 16, a white peak limiter circuit 41 for limiting the white peak level of the pedestal clamped video signal is provided between the pedestal clamp circuit 1 and the switch circuit 2, and is superposed by the switch circuit 2. pulse peak value (voltage V _P), it may be a pedestal clamp voltage V _C and the intermediate voltage of white peak limiter voltage _{V W (V C + V W} ) / 2.

Here, the pedestal clamp circuit 1 compares the output of the amplifier 42 with the video signal input to the non-inverting input terminal with the pedestal clamp voltage V _C ,
A comparator 44 that supplies the comparison output to the inverting input terminal of the amplifier 42 via the capacitor C3 and the buffer circuit 43.
And a switch circuit 45 that supplies the output of the amplifier 42 to the comparator 44 only during the back porch period, which is the pedestal portion of the video signal. The white peak limiter circuit 41 includes transistors Q31 and Q32 whose emitters and collectors are connected to each other and whose collectors are connected to the ground side and whose emitters are connected to the constant current source 46, and whose bases are the emitters of the transistors Q31 and Q32 and the constant current source. 46, a transistor Q33 having an emitter connected to the constant current source 47 and the contact (a) side of the switch circuit 2 connected thereto. Then, the base of the transistor Q31 is supplied with the video signal pedestal clamp with pedestal clamp circuit 1, the base of the transistor Q32 is given peak white limiter voltage V _W.

In this manner, the pedestal level of the input video signal is compared with the pedestal clamp voltage V _C by the comparator 44, and the voltage of the capacitor C3 charged and discharged by the comparison output is inverted by the amplifier 42 through the buffer circuit 43. by being fed back to the input terminal, it is to be pedestal clamped to the voltage V _C. Then, if a video signal pedestal part is clamped to the voltage V _C is supplied to the base of the transistor Q31, the signal level is less than the white peak limiter voltage V _W, the transistor Q
33 is supplied to the contact (a) side of the switch circuit 2 from the emitter side. Conversely, when the signal level exceeds the voltage V _W , the transistor Q32 is turned on, and the voltage V _W is supplied as it is from the emitter side of the transistor Q33 to the contact (a) side of the switch circuit 2, and the white peak level becomes the voltage V _W Will be limited to And the switch circuit 2
When in _{(V C + V W) /} 2 since the voltage V _P is superposed in a pulsed manner, so that the output video signal as shown in FIG. 17 (a) is obtained. This is further combined with the inverting amplifier 4 of FIG.
17B, the white peak limiter level of the inverted output is made to match the pedestal level of the non-inverted output, and the white peak limiter level of the non-inverted output is made to match the pedestal level of the inverted output. An output video signal as shown in FIG.

In the first, second and third embodiments, in order that the brightness does not fluctuate with respect to the fluctuation of the power supply voltage,
The magnitude of the pulse superimposed on the pedestal portion, that is, the potential difference between the pedestal clamp voltage V _C and the peak value (voltage V _P ) of the superimposed pulse may be kept constant. Specifically, the voltages V _C and V _P are set using a bandgap type constant voltage circuit 48 and operational amplifiers 49 and 50 as shown in FIG. Here, the band gap type constant voltage circuit 4
8 is a transistor Q _A1 , Q _A2 connected in a current mirror.
, A constant current source 51, and a transistor Q _A3 for temperature compensation. Here, the resistance values of the resistors R _{A1 to} R _A7 are R
_{a1 to Ra7} .

The output voltage V _O from the band-gap type constant voltage circuit 48 becomes V _O = V _BE3 + V _a2 , and V _a2 = V
In I _a3 · R _a2, is _{I a3 = (V BE1 -V BE2} ) / R a3.
Temperature variations △ V _O of the output voltage V _{O is, △ V O = △ V BE3} + (△ V BE1 - △ BE2) R a2 / R a3 _{becomes, R a1: R a2 = 1} : When N, I _a2 : I _a3 =
N: In _{1, (△ V BE1 - △} V BE2) will have _{R a2 / R a3 = kT ·} 1 / q · l n N · R a2 / R a3 , and the positive temperature coefficient. On the other hand, V _BE3
Has a negative temperature coefficient, so that R _a2 / R _a3
By selecting such that the temperature coefficient of the voltage between both ends of _A2 cancels the temperature coefficient of the base-emitter voltage V _BE3 of the transistor Q _a3 , the output voltage V _O becomes a voltage without temperature fluctuation.
This voltage V _O is _converted by the operational amplifier 49 into (R _a4 + R _a5 ) / R _a5
If the voltage V _P and V _C are respectively multiplied by (R _a6 + R _a7 ) / R _a7 by the operational amplifier 50, the potential difference V _P −V _C is not affected by the fluctuation of the power supply voltage.

[0045]

According to the present invention as described above, according to the present invention, Bae
The video signal in which the pulse is superimposed on the
Inversion 1 every horizontal period centering on the tip level of Luss
The signal is inverted every horizontal period, and the signal to be compared with the reference voltage to create a signal for controlling the intermediate level (DC) of the video signal is based on the peak value (DC voltage) of the pulse. A low-pass filter is not required to supply the signal to the comparator, and only a holding capacitor is necessary.If the holding capacitor reduces the leakage current during holding, its capacitance value Can be easily formed in an integrated circuit because it can be small.
Also, offset detection and detection are performed in both the inversion period and the non-inversion period.
Since removal is performed, only one of the inversion period and the non-inversion period
Offset compared to one that removes offset by detection
Can be removed sufficiently and quickly. Moreover, the inversion period and
Offset detection / removal without distinguishing the inversion period
Can leave.

In the present invention, since the pulse is superimposed on the pedestal portion, when the brightness is reduced by the inverting amplifier 4, even if the pedestal level of the video signal is limited, the pulse for the sample hold remains. Therefore, there is an effect that the offset removing operation is not hindered.

Further, in the present invention, the peak value of the pulse superimposed on the pedestal portion and serving as an intermediate level of the video signal is set to an intermediate voltage between the pedestal clamp voltage and the white peak limiter voltage, so that the inverted and non-inverted output is obtained. The output voltage can be reduced by increasing the amplitude between the pedestal levels as much as possible and keeping the video signal as large as possible for high contrast. By keeping the potential difference between the pedestal level and the peak value of the pulse constant with respect to the fluctuation of the power supply voltage, the brightness can be prevented from being affected by the fluctuation of the power supply voltage.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a first embodiment of an offset removing circuit according to the present invention.

FIG. 2 is a signal waveform diagram for explaining the operation.

FIG. 3 is a specific circuit diagram of a pedestal clamp circuit and a switch circuit of FIG. 1;

FIG. 4 is a specific circuit diagram of the inverting amplifier and the level shift circuit of FIG. 1;

FIG. 5 is a specific circuit diagram of the sample and hold circuit of FIG. 1;

FIG. 6 is a specific circuit diagram of the comparator of FIG. 1;

FIG. 7 is a block circuit diagram of a second embodiment of the offset removing circuit according to the present invention.

FIG. 8 is a signal waveform diagram for explaining the operation.

FIG. 9 is a waveform chart showing advantages of the first and second embodiments.

FIG. 10 is a block circuit diagram of a conventional example.

FIG. 11 is a signal waveform diagram for explaining the operation.

FIG. 12 is a block circuit diagram of a third embodiment of the offset removing circuit according to the present invention.

FIG. 13 is a signal waveform diagram for explaining the operation.

FIG. 14 is a specific circuit diagram of the inverting amplifier and the level shift circuit of FIG. 12;

FIG. 15 is a waveform diagram of the brightness adjustment.

FIG. 16 is a specific circuit diagram obtained by adding a white peak limiter circuit to FIG.

FIG. 17 is a signal waveform diagram for explaining the operation.

FIG. 18 is a specific circuit diagram for setting the voltage.

[Explanation of symbols]

 Reference Signs List 1 pedestal clamp circuit 2 switch circuit 3 voltage generating circuit 4 inverting amplifier 6 level shift circuit 7 output terminal 8, 8a, 8b sample hold circuit 9, 9a, 9b comparator 41 white peak limiter circuit 48 constant voltage circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 3/36 G09G 3/20 H04N 5/16 H04N 5/66

Claims (7)

(57) [Claims] A pulse superimposing circuit for superimposing a pulse on a pedestal portion of a video signal before inversion every horizontal period ;
An inverting circuit that inverts every horizontal period around the center, means for leading the output of the inverting circuit to an output terminal, a sample and hold circuit that samples and holds the leading edge level of the pulse from the output of the inverting circuit, Compare the output of the sample and hold circuit with the reference voltage,
Means for controlling the direct output level of the output video signal of the inverting circuit to a predetermined value based on the comparison output. 2. An offset removing circuit for controlling an intermediate level of a video signal inverted every one horizontal period so that the intermediate level of the video signal becomes a predetermined value, wherein a pedestal clamp circuit for clamping a pedestal of the video signal. A pulse superimposition circuit that superimposes a pulse having a peak value according to a brightness control voltage on each pedestal portion of the pedestal-clamped video signal in each horizontal period, and a video signal on which the pulses are superimposed based on the brightness control voltage. An inverting amplifier circuit that differentially amplifies and inverts every one horizontal period to make the peak of the pulse an intermediate level of a video signal; a level shift circuit that shifts an intermediate level of an output of the inverting amplifier circuit; Means for leading an output video signal of the level shift circuit to an output terminal; A sample hold circuit for sampling and holding the pulse portion of the video signal, the output of the sample-and-hold circuit with a reference voltage,
And a comparator for applying the comparison output to the level shift circuit as a control voltage. 3. A pedestal clamp circuit for clamping a pedestal of a video signal in an offset removing circuit for controlling an intermediate level of the video signal so that the intermediate level of the video signal inverted every horizontal period becomes a predetermined value. A pulse superimposing circuit for superimposing a pulse having a predetermined peak value in each horizontal period on a pedestal portion of the pedestal-clamped video signal; and an inverting circuit for inverting the video signal on which the pulse is superimposed every horizontal period. A level shift circuit that shifts a DC level of an output of the inversion circuit; a unit that derives an output video signal of the level shift circuit to an output terminal; and the pulse in an inversion period of the video signal output from the level shift circuit. A first sample and hold circuit for sampling and holding a portion, and a video output from the level shift circuit. A second sample-and-hold circuit that samples and holds the pulse portion during the non-inversion period of the signal; a unit that extracts an intermediate voltage of the output of the first and second sample-and-hold circuits; comparing the intermediate voltage with a reference voltage; And a comparator for applying a comparison output to the level shift circuit as a control voltage. 4. An offset removing circuit for controlling an intermediate level of a video signal inverted every one horizontal period so that the intermediate level of the video signal becomes a predetermined value. A pedestal clamp circuit for clamping a pedestal of the video signal. A pulse superimposing circuit that superimposes a pulse on the pedestal portion of the pedestal-clamped video signal every horizontal period, differentially amplifies the video signal on which the pulse is superimposed, and inverts and outputs the signal every horizontal period. An inverting amplifier circuit, a level shift circuit that shifts an intermediate level of an output of the inverting amplifier circuit, a first sample and hold circuit that samples and holds the pulse portion during an inversion period of a video signal output from the level shift circuit, The pulse portion in the non-inversion period of the video signal output from the level shift circuit is supported. Compares the second sample and hold circuit to pull holding the output of said first, second sample-and-hold circuit,
Means for controlling the differential amplification in the inverting amplifier circuit so that the peak value of the pulse becomes the intermediate level of the video signal by the comparison output; and the output of the first or second sample and hold circuit is a reference voltage. And means for controlling the level shift circuit so that the intermediate level of the output of the inverting amplifier circuit becomes a predetermined value based on the comparison output. 5. The offset removing circuit according to claim 4, wherein the peak value of the pulse superimposed by said pulse superimposing circuit is varied to perform brightness adjustment. 6. A white peak limiter circuit for limiting a white peak level of a video signal pedestal clamped by the pedestal clamp circuit, wherein a peak value of a pulse superimposed by the pulse superimposition circuit is determined by
5. The offset removing circuit according to claim 4, wherein the voltage is set to an intermediate voltage between the pedestal clamp voltage and the white peak limiter voltage. 7. A means for setting a pedestal clamp voltage in the pedestal clamp circuit and a peak value of a pulse superimposed in the pulse superimposition circuit so that a potential difference therebetween becomes independent of a fluctuation in a power supply voltage. 5. The offset removing circuit according to claim 4, further comprising: