JP2000174601A - Driving circuit for capacitive load - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify constitution and to reduce loss in a driving circuit for driving the load capacity of the common electrode or the like of a liquid crystal panel. SOLUTION: Control circuits 25 and 26 supply the base currents I1 and I2 of output transistors Q1 and Q2, and when the potential of the load capacity CL reaches a prescribed upper limit or lower limit, a limiter circuit 27 or 28 respectively bypasses a charging or discharging current. Also, in response to the operation of the limiter circuit 27 or 28, the control circuit 25 or 26 respectively suppresses the base current I1 or I2 of the output transistor Q1 or Q2. Thus, since just the changeover of the base current by the control circuits 25 and 26 is performed by the limiter circuits 27 and 28, the need of a countermeasure against oscillation or the like is eliminated and the constitution is simplified. Also, since the large charging/discharging current does not keep flowing, the loss is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a circuit for driving a capacitive load driven by charging and discharging.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing the electrical configuration of a typical prior art capacitive load driving circuit 1. As shown in FIG. The drive circuit 1 includes a reference differential amplifier circuit 2 for defining a charge / discharge current, a switch sw1 functioning as a control circuit for switching the charge / discharge current in response to an input signal, The control circuit includes a control differential amplifier circuit 3 for controlling and an output circuit 4, and is driven by charging and discharging a load capacitance cl connected to the output terminal 5.

The differential amplifier circuit 2 includes reference current sources f1 to f1.
f4, reference voltage sources b1, b2, and transistors q1,
q2 and a resistor r1. The bases of a pair of transistors q1 and q2 forming a differential pair include:
Reference voltages v1 and v2 are provided from reference voltage sources b1 and b2, respectively. In the following description, v1> v
Explanation is made as 2. The high level Vcc is connected to the collectors of the transistors q1 and q2 via the constant current sources f1 and f2.
Are supplied with constant currents i1 and i2, respectively.
The emitters of the transistors q1 and q2 are grounded via constant current sources f3 and f4, respectively, and are connected to each other by a resistor r1. Constant current sources f1, f2, f
The currents i1, i2, i3, and i4 flowing through f3 and f4 are set to be equal to each other.

The collector of the transistor q1 is connected to one individual contact a of the switch sw1, and the collector of the transistor q2 is connected to the other individual contact b.
As described above, since v1> v2, the contact a is at a low level and the contact b is at a high level. The common contact c of the switch sw1 is connected to the inverting input terminal of the differential amplifier 6 in the differential amplifier circuit 3, and the non-inverting input terminal of the differential amplifier 6 receives the reference voltage v3 from the reference voltage source b3. Have been.

On the other hand, the output circuit 4 has a PNP type output transistor q3 whose emitter is connected to the power supply line on the high level Vcc side and whose collector is connected to the output terminal 5.
And an NPN-type output transistor q4 whose emitter is grounded and whose collector is connected to the output terminal 5. The positive-phase output of the differential amplifier 6 is provided to the base of the output transistor q3. An opposite-phase output is applied to the base of the transistor q4. The output terminal 5 is connected to an inverting input terminal of the differential amplifier 6 via a feedback resistor r2.

FIG. 5 is an electric circuit diagram showing the differential amplifier 6 in detail. The differential amplifier 6 includes a reference current generation circuit 6
0, an amplifier 61 on the discharging side, an amplifier 62 on the charging side,
The reference voltage source b3 and the feedback resistor r2 are provided. The reference current generation circuit 60 includes a resistor r31,
A series circuit including a diode-connected transistor q31, a transistor q33 whose base is supplied with a reference voltage v31 from a reference voltage source b31, a resistor r33, a diode-connected transistor q32, and a resistor r32 has the high level. It is connected between a power supply line 7 of Vcc and a ground potential. Therefore, a reference current i0 determined by the reference voltage v31 flows through this series circuit.

On the amplifier 61 side, the current from the power supply line 7 is shared by the emitters of the transistors q11 and q12 forming a differential pair via the resistor r10 and the transistor q10 forming a current mirror circuit with the transistor q31. Given to. One transistor q1
The input voltage v4 from the inverting input terminal 8 of the differential amplifier 6 is applied to the base of the differential amplifier 6. The other transistor q12
Is supplied with a reference voltage v3 from a reference voltage source b3. The collector of transistor q11 is grounded via transistor q13 and resistor r11, and the collector of transistor q12 is grounded via transistor q14 and resistor r12. The transistor q1
The collector of 2 is also connected to the base of the output transistor q4 to supply a base current to the output transistor q4.

On the other hand, on the amplifier 62 side, a current is supplied to the collector of one transistor q21 forming a differential pair from the power supply line 7 via a resistor r21 and a transistor q23.
2 has a resistor r22 and a transistor q2
Current is supplied via 4. Transistors q21 and q
The emitter of 22 is commonly grounded via a transistor q20 and a resistor r20 forming a current mirror circuit with the transistor q32. Transistor q
In the base of 21, as in the case of the transistor q11,
An input voltage v4 is applied to the input terminal 8, and a reference voltage v3 is applied to the base of the transistor q22, similarly to the transistor q12. The base current of the output transistor q3 is drawn from the collector of the transistor q22.

Therefore, when the input voltage v4 is equal to the reference voltage v
When it is higher than 3, the transistor q11 is turned off.
Then, the transistor q12 turns on. As a result, the transistors q31 and q1 are connected to the transistors q12 and q14.
The current i0 turned back at 0 flows and the transistor q1
3 is turned off, the base potential of the collector of the transistor q14, that is, the base potential of the output transistor q4 on the discharge side rises, and the output transistor q4 is turned on, and the load capacitance cl is increased.
, And the potential of the output terminal 5 becomes low level. At this time, the transistors q21 and q23
n, the current obtained by turning the current i0 back on the transistors q32 and q20 flows through the transistors q21 and q23, but the transistors q22 and q24 are turned off.
The transistor q3 on the charging side remains off. When the collector potential of the output transistor q4 becomes lower than the base potential due to the discharge, the output transistor q4 is turned off, and the charge of the load capacitance cl is maintained.

On the other hand, when the input voltage v4 is equal to the reference voltage v
When the voltage is lower than 3, the transistors q22 and q24 are turned on. The current i0 returned by the transistors q32 and q20 flows through the transistors q22 and q24, and the collector of the transistor q22, that is, the base of the output transistor q3 on the charging side. The potential drops, the output transistor q3 turns on, a charging current flows to the load capacitance cl, and the potential of the output terminal 5 goes high. At this time, the transistors q21 and q23 are turned off, the transistors q11 and q13 are turned on, and the transistor q1 is turned off.
Although the current i0 from the transistor q10 flows through the transistors q1 and q13, the transistors q12 and q14 are off, and the output transistor q4 on the discharging side remains off. When the collector potential of the output transistor q3 rises above the base potential due to discharging, the output transistor q3 is turned off, and the charge of the load capacitance cl is maintained.

As shown in FIG. 6, the driving circuit 1 configured as described above calculates the difference between the reference voltages v1 and v2 as r2
The output is amplified and multiplied by a factor of / r1 to charge and discharge the load capacitance cl. When the load capacity cl is charged or discharged to a predetermined amount,
When the charge / discharge is not required, the base current of the output transistors q3 and q4 is suppressed by the negative feedback by the feedback resistor r2.

FIG. 7 is a block diagram showing an electrical configuration of a driving circuit 11 for a capacitive load according to another prior art. This drive circuit 11 is the one shown in Japanese Patent No. 2548333. In this drive circuit 11, NPN output transistors q3 and q4 respond to control signals of opposite phases from input gate circuit 12 to control transistor q4.
1 and q42, respectively.
The bases of the output transistors q3, q4 are also supplied with base currents from the variable current sources 13, 14. The collector currents of the output transistors q3 and q4 are detected by current detection circuits 15 and 16, respectively, and the detection results are positively fed back to the variable current sources 13 and 14, respectively.

When the current detection circuit 15 or 16 detects the charging / discharging current to the load capacitance cl, the driving circuit 11 increases the charging / discharging current by the positive feedback to perform high-speed operation and charge or discharge. With respect to the variable current source on the charging side (for example, the variable current source 13 on the charging side), the current value of the variable current source on the non-charging or discharging side (i.e., 14) is reduced to reduce Power consumption is realized.

[0014]

In the driving circuit 1 configured as described above, the negative feedback is applied to the differential amplifier 6 by the feedback resistor r2. The base currents of q3 and q4 are suppressed, and low power consumption is achieved. However, oscillation or ringing may occur due to the feedback, and a capacitor or the like for phase compensation as shown by reference numerals c1 to c3 in FIG. 5 is required, resulting in a problem that the circuit configuration is complicated. Although the base currents of the output transistors q3 and q4 can be suppressed, there is a portion in the differential amplifier 6 where a constant current flows, such as the reference current generating circuit 60, so that the current consumption is sufficiently reduced. I can't say that. Further, the dynamic range as shown in FIG. 6 is determined around the reference voltage v3 of the differential amplifier 6, and when the reference voltage v3 fluctuates, a high level indicated by a reference numeral vh in FIG. The potential on the level side and the potential on the low level side indicated by the reference numeral vl respectively correspond to the power supply voltage Vcc and the ground potential, and there is a problem that the output margin vu on the upper limit side differs from the output margin vd on the lower limit side. .

In addition, since the drive circuit 11 also performs a positive feedback to instantaneously increase the charge / discharge current with a small bias current, a phase compensation circuit or the like is required to prevent oscillation, and the configuration is complicated. There is a problem that it becomes. Further, since the current detection circuits 15 and 16 are provided on the collector side of the output transistors q3 and q4, respectively, the current detection circuits 15 and 16 become loads.
There is a problem that the dynamic range of the output becomes narrow and the output amplitude cannot be controlled with high accuracy. Furthermore, the instantaneously increased output transistor q
The base currents of 3, q4 continue to flow until the output is inverted, and there is a problem that the power loss is large in the case of low-frequency operation.

An object of the present invention is to provide a driving circuit for a capacitive load with a simple configuration and low loss.

[0017]

According to a first aspect of the present invention, there is provided a drive circuit for a capacitive load, wherein a control circuit controls a charge / discharge circuit to charge / discharge an output load capacitance in response to an input signal. A driving circuit including a limiter circuit provided in association with the charging / discharging circuit, for limiting an output voltage amplitude to a predetermined voltage value, wherein the control circuit responds to the operation of the limiter circuit. The charging and discharging current of the discharging circuit is limited.

Further, in the capacitive load driving circuit according to the second aspect of the present invention, the charging / discharging circuit has an emitter connected to a high-level terminal and a low-level terminal of a power supply, and a collector commonly connected to an output terminal. And a first transistor and a second transistor respectively connected to the output load capacitor through the control circuit and supplied with a base current switched in response to the input signal from the control circuit, wherein the limiter circuit has a common emitter. A predetermined high-level reference voltage and a low-level reference voltage are respectively applied to the base, and a base current to the first and second transistors is controlled by the control circuit by a collector current. It is characterized by comprising third and fourth transistors for limiting.

According to the above arrangement, the output voltage amplitude is defined by the limiter circuit as defined in claim 2;
When the charging and discharging of the output load capacitance progresses and the limiter circuit operates, the control circuit limits the charging and discharging current of the charging and discharging circuit.

Therefore, since only the operation state of the control circuit is switched by utilizing the limiter circuit, no oscillation or ringing occurs, and no countermeasures are required for this, and the configuration can be simplified. Further, when the output load capacity reaches the voltage value specified by the limiter circuit, the control circuit limits the charge / discharge current, so that the base current of the output transistor forming the charge / discharge circuit as described in claim 2 is used. The power consumption can be limited, and low power consumption can be achieved. Furthermore, since the output voltage amplitude is limited to a constant value by the limiter circuit, the output dynamic range is stabilized and the margin for the potential on the power supply side can be kept constant.

Furthermore, in the capacitive load driving circuit according to the invention of claim 3, the output load capacitance is a common electrode of a liquid crystal panel.

According to the above configuration, since the common electrode operates at a relatively low speed, the present invention can be suitably implemented.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described.
The following is a description based on FIGS. 1 to 3.

FIG. 1 is a block diagram showing a schematic configuration of a capacitive load driving circuit 21 according to an embodiment of the present invention. This drive circuit 21 is used as a load capacitor CL as a common electrode of a liquid crystal panel driven at a comparatively low frequency.

The load capacitance CL is connected to an output terminal 22. The output terminal 22 is connected to the output transistor Q1 of the output transistors Q1 and Q2 constituting an output circuit.
1 supplies a charging current from the power supply line 23 of the high level Vcc, and the output transistor Q2 draws a discharging current to the ground line. The output transistor Q1 is a PNP transistor, and its base current I1 is
Pulled out by. On the other hand, the output transistor Q2 is an NPN transistor, and its base current I2 is supplied by the discharge control circuit 26. To these control circuits 25 and 26, a pulse-like video signal S1 for driving the common electrode is input from a video signal source (not shown).

The potential of the output terminal 22 is monitored by limiter circuits 27 and 28. The upper limiter circuit 27 controls the output transistor Q so that the potential of the output terminal 22 does not become higher than a predetermined amplitude upper limit E1.
1 and bypasses the charging current of
In response to the operation of 7, the charge control circuit 25 suppresses the amount of the base current I1 to be absorbed and limits the charge current. The lower limiter circuit 28 bypasses the discharge current of the output transistor Q2 so that the potential of the output terminal 22 does not become lower than a predetermined lower limit value E2, and the discharge control circuit 26 responds to the operation of the lower limiter circuit 28. Then, the supply amount of the base current I2 is suppressed, and the discharge current is limited.

FIG. 2 is an electric circuit diagram showing a specific configuration of the drive circuit 21 shown in FIG. 2, parts corresponding to those in FIG. 1 are denoted by the same reference numerals. The upper limiter circuit 27 includes a PNP transistor Q
3 and a reference voltage source B1. On the other hand, the lower limiter circuit 28 includes an NPN transistor Q4 and a reference voltage source B2.
The output voltages of the reference voltage sources B1 and B2 are V1 and V2, respectively.
When the base-emitter voltage of the transistors Q3 and Q4 is Vbe, the upper limit E1 and the lower limit
2 is E1 = V1 + Vbe (1) E2 = V2-Vbe (2) In FIG. 2, the potential of the output terminal 22 is shown in FIG. 3 with respect to the video signal S1 input to the input terminal 31 in FIG. Become like

The drive circuit 21 also includes the control circuit 25,
26, the constant current sources F1 and F2, the reference voltage source B0, the transistors Q11 to Q14 and the resistors R1 and R2, the transistors Q15 and Q16 and the resistors R3 and R4 on the discharge control circuit 26 side, and the charge control circuit 25 side It includes transistors Q17, Q18 and resistors R5, R6.
A resistor R2 interposed between the power supply line 23 and the ground line, and a diode-connected transistor Q14.
And the constant current source F2 always has a constant current I1
2 is flowing.

The emitters of the transistors Q11 and Q12 forming a differential pair for input detection are supplied with a constant current I11 from a constant current source F1.
Is connected to the input terminal 31, the collector is grounded, and the base of the transistor Q12 is connected to a reference voltage source B.
The reference voltage V0 is applied from 0, and the collector is grounded via a diode-connected transistor Q13 and a resistor R1. In the example shown in FIG. 2, although the input and output are in phase, the transistor Q13 and the resistor R1 are provided on the collector side of the transistor Q11 and the collector of the transistor Q12 is directly grounded, so that the input and output are in opposite phases. You can also.

When the video signal S1 to the input terminal 31 is lower than the reference voltage V0, the current I11 flows through the transistor Q11. On the other hand, when the current is high, the current I11 flows from the transistor Q12 via the transistor Q13 and the resistor R1. A discharge control circuit 2 is provided between the power supply line 23 and the ground line.
A series circuit composed of a resistor R3 for six, transistors Q15, Q16 and a resistor R4 and a series circuit composed of a resistor R6 for a charge control circuit 25 and transistors Q17, Q18 and a resistor R5 are interposed.

The transistor Q13 and the transistor Q
16 and Q18 constitute a current mirror circuit.
Also, the transistor Q14 and the transistors Q15, Q17
And constitute a current mirror circuit. The base current I1 is drawn from the collector of the transistor Q18,
The base current I2 flows out from the collector of the transistor Q15. On the other hand, part of the charging current I15 flowing out of the output transistor Q1 is
3, a part of the discharge current I19 which is given to the emitter side of the transistor Q18 and is to be drawn by the output transistor Q2 is bypassed by the transistor Q4 and drawn from the emitter side of the transistor Q15.

Therefore, when the level of the video signal S1 becomes higher than the reference voltage V0, the transistors Q12,
The transistor Q18 is turned on, the transistor Q18 is turned on, the base current I1 of the output transistor Q1 is extracted, and the charging of the load capacitance CL is started. At this time, the transistor Q1
8 is I14 and the collector current of the transistor Q17 is I13, I1 = I14-I1
3, and the charging current via the output transistor Q1 is
When the DC current amplification factor of the output transistors Q1 and h _FE, the I1 × h _FE. At this time, although the transistor Q16 is also turned on, the current I20 flowing through the transistor Q16 is I20 ≧ I17 with respect to the collector current I17 of the transistor Q15, so that the output transistor Q2 is off.

When the potential of the output terminal 22 rises and reaches the upper limit value E1, the transistor Q3 turns on, bypasses a part of the charging current, and supplies the charging current as a current I15 to the emitter side of the transistor Q18. At this time, assuming that the base current of the output transistor Q1 is sufficiently smaller than its collector current, the output transistor Q1 stabilizes substantially at I15 = I14-I13. Therefore, when the charging is stabilized, the charging current, that is, the collector current of the output transistor Q1, becomes substantially equal to the base current I1 of the output transistor Q1 at the start of charging, and is suppressed to approximately 1 / _hFE .

On the other hand, when the level of the video signal S1 becomes lower than the reference voltage V0, the transistors Q12, Q1
3 and the transistors Q16 and Q18 are turned off. As a result, the collector current I17 of the transistor Q15
Are supplied as the base current I2 of the transistor Q2, and the discharge of the load capacitance CL is started. At this time,
When the collector current of the transistor Q15 and I17, an I2 = I17, the discharge current through the output transistor Q2, the DC current amplification factor of the output transistor Q2 when the h _FE, the I2 × h _FE. At this time, although the transistor Q17 is also turned on, the reverse bias of the transistor Q1 occurs and the output transistor Q1 is turned off.

When the potential of the output terminal 22 decreases and reaches the lower limit value E2, the transistor Q4 is turned on, and the current I19 is drawn from the emitter side of the transistor Q15 and applied to the collector of the transistor Q2. At this time, with respect to the collector current I17 at the time of discharging the transistor Q15,
Assuming that the base current of the output transistor Q2 is sufficiently smaller than its collector current, the output transistor Q2 is stabilized at approximately I19 = I17. Therefore, the discharge current, i.e. the collector current of the output transistor Q2, the discharge is stabilized, the collector current I17 of the transistor Q15 during discharge initiation, i.e. approximately equal to the base current I2 of the output transistor Q2, approximately h _FE fraction 1 Is suppressed.

As described above, the driving circuit 21 according to the present invention
Limits the output voltage amplitude to the range from the upper limit value E1 to the lower limit value E2 by the limiter circuits 27 and 28, and controls the control circuit 2 by using a charge / discharge current bypassed for the voltage limit.
5, 26 suppress the base currents of the output transistors Q1 and Q2 and suppress the charge / discharge current, so that the loss can be reduced. Also, the output transistors Q1, Q1 of the control circuits 25, 26 are controlled by the limiter circuits 27, 28.
Since only the switching of the base current of Q2 is performed, oscillation or ringing does not occur.
The configuration such as the phase compensation circuit can be omitted, and the configuration can be realized with a simple configuration.

Furthermore, since the output voltage amplitude is determined by the reference voltages V1 and V2 and the center voltage is not determined, when the center voltage is shifted as in the prior art shown in FIG. 6, the Vcc or GND side is shifted. Does not become small. In addition, since the charge / discharge current is suppressed in a state where the charge / discharge is stable, the present invention can be suitably applied to a common electrode of the liquid crystal panel having a long charge / discharge cycle.

[0038]

As described above, the drive circuit for the capacitive load according to the first aspect of the present invention is configured such that the control circuit controls the charge / discharge circuit in response to the input signal to charge / discharge the output load capacitance. In the drive circuit, in connection with the charge and discharge circuit,
3. The output voltage amplitude is limited to a predetermined voltage value.
A limiter circuit as shown in FIG. 1 is provided, the output voltage amplitude is defined by the limiter circuit, and the control circuit limits the charge / discharge current of the charge / discharge circuit in response to the operation of the limiter circuit.

Therefore, since only the operation state of the control circuit is switched using the limiter circuit, oscillation and ringing do not occur, and no countermeasures are required for this, and the configuration can be simplified. Further, when the output load capacity reaches the voltage value specified by the limiter circuit, the control circuit limits the charge / discharge current, so that the base current of the output transistor constituting the charge / discharge circuit is limited. Power consumption can be reduced. Furthermore, since the output voltage amplitude is limited to a constant value by the limiter circuit, the output dynamic range is stabilized and the margin for the potential on the power supply side can be kept constant.

Furthermore, in the capacitive load driving circuit according to the third aspect of the present invention, the output load capacitance is used as the common electrode of the liquid crystal panel as described above.

Therefore, the present invention can be suitably implemented for a relatively low-speed operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a capacitive load drive circuit according to an embodiment of the present invention.

FIG. 2 is an electric circuit diagram showing a specific configuration of the drive circuit shown in FIG.

FIG. 3 is a waveform chart for explaining the operation of the drive circuit shown in FIG.

FIG. 4 is a block diagram showing the electrical configuration of a typical prior art capacitive load drive circuit.

5 is an electric circuit diagram showing a specific configuration of a differential amplifier in the drive circuit shown in FIG.

FIG. 6 is a waveform chart for explaining the operation of the drive circuit shown in FIG.

FIG. 7 is a block diagram illustrating an electrical configuration of a driving circuit for a capacitive load according to another related art.

[Explanation of symbols]

Reference Signs List 21 drive circuit 22 output terminal 25 charge control circuit (control circuit) 26 discharge control circuit (control circuit) 27 upper limiter circuit (limiter circuit) 28 lower limiter circuit (limiter circuit) B0 reference voltage source B1, B2 reference voltage source (limiter) Circuit) CL Load capacity (output load capacity) F1, F2 Constant current source Q1 Output transistor (charge / discharge circuit, first transistor) Q2 Output transistor (charge / discharge circuit, second transistor) Q3 Transistor (limiter circuit, third Transistor) Q4 transistor (limiter circuit, fourth transistor) Q11 to Q18 transistor

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 5C006 AA01 AF54 AF61 BC03 BC12 BF25 BF31 BF36 BF38 FA31 FA41 FA47 5C080 AA10 BB05 DD12 DD22 DD26 JJ02 JJ03 JJ04 5J055 AX12 AX44 AX64 BX16 CX12 CX30 DX17 EZ00 EZ04 EZ08 EZ16 EZ57 EZ69 GX01 GX02 GX04 5J056 AA05 BB17 BB24 BB51 CC00 CC01 CC02 CC13 CC28 DD02 DD25 EE11 FF08 GG06

Claims (3)

[Claims] 1. A driving circuit in which a control circuit controls a charging / discharging circuit to charge / discharge an output load capacitance in response to an input signal. A limiter circuit that limits the voltage to within a predetermined voltage value, wherein the control circuit responds to the operation of the limiter circuit,
A drive circuit for a capacitive load, wherein a charge / discharge current of the charge / discharge circuit is limited. 2. The charge / discharge circuit according to claim 1, wherein an emitter is connected to a high-level terminal and a low-level terminal of a power supply, and a collector is commonly connected to the output load capacitor via an output terminal. A first transistor and a second transistor, each of which receives a base current that is switched in response to the input signal, wherein the limiter circuit has an emitter commonly connected to the output terminal, and a predetermined high-level side connected to the base. And the low-level reference voltage are given, respectively.
The driving circuit for a capacitive load according to claim 1, further comprising third and fourth transistors for limiting a base current to the first and second transistors by the control circuit by a collector current. 3. The driving circuit according to claim 1, wherein the output load capacitance is a common electrode of a liquid crystal panel.