JP3278541B2 - Phase reference detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase reference detection circuit for a second generation EDTV identification control signal detection apparatus.

[0002]

2. Description of the Related Art In order to identify a second generation EDTV broadcast, it has been proposed to insert an identification control signal into the 22nd and 285th lines of a video signal. The discrimination control signal is composed of 27 bits as shown in FIG. 5, and one bit period is equivalent to seven periods (about 1.95 μs) of the 3.58 MHz chrominance subcarrier fsc. The first bit (B1) to the fifth bit (B5) are NRZ waveforms, and B6 to B2
Up to 3 are signals that are phase-modulated at fsc, and B25 to B27 are sine waves having a frequency of 4/7 fsc. The phase reference detection circuit generates a phase reference signal used for reproducing the reinforcement signal.

[0003] First, referring to FIGS.
A conventional phase reference detection circuit that generates a phase reference signal using a sine wave of / 7 fsc will be described.

A video signal input from an input terminal 1 is supplied to a clock generation circuit 2, a synchronization separation circuit 3, an A / D converter 5
Supplied to The clock generation circuit 2 generates a system lock signal having a frequency of 4 fsc locked to the burst signal and supplies it to each block. The synchronization separation circuit 3 separates the horizontal synchronization signal and the vertical synchronization signal from the video signal, and the control signal generation circuit 4 generates a signal for controlling each block.

[0005] The video signal quantized by the A / D converter 5 is band-limited by a 4/7 fsc band-pass filter (BPF) 6 to become a signal as shown in FIG. Supplied. Adder 8 of period accumulation circuit 7
Are input to B25 to B25 as shown in FIG.
According to the accumulated gate signal which becomes H level in the section of B27,
During this H level section, the adder output is added to the signal delayed by 7 clocks by the shift register 9. Since the frequency of the sine wave of the input signal is 4/7 fsc, sampling by a system clock having a frequency of 4 fsc is one cycle of 7 clocks. Therefore, the cycle accumulating circuit 7 has a noise reduction function since signals having the same phase are added. As shown in FIG. 8C, in synchronism with the peak detection gate signal which becomes H level during the period of 7 clocks included in the last cycle of the accumulated gate signal, FIG. A one-cycle sine wave signal as shown is input to the peak detection circuit 10. Peak detection circuit 1
At 0, as shown in FIG. 8 (e), a peak detection pulse having an H level is generated at a position where the input signal is maximum (in an actual circuit, the position is delayed by a certain number of clocks). . The horizontal counter 22 is reset by the peak detection pulse, and a horizontal reference pulse which becomes high for one clock every horizontal cycle (910 clocks) is applied to the phase reference signal output terminal 2.
3 is output.

Next, another conventional phase reference detection circuit for generating a phase reference signal using the falling edge of B1 will be described with reference to FIGS. The description of the same parts as those in the previous example will be omitted.

The video signal quantized by the A / D converter 5 is supplied to an inter-field accumulation circuit 24. In the inter-field accumulator circuit 24, as shown in FIGS. 9 (a) and 9 (b), according to the gate signal which becomes H level for several tens of clock periods before and after the fall of B1, the input video signal Is added to the output of the memory 26 by the adder 25 and written to the memory 26. The signal written in the memory 26 is read out in accordance with the B1 falling gate signal of the next field. By repeating this, a signal with reduced noise is supplied to the difference circuit 17. In the difference circuit 17, a difference between the input signal and the signal delayed by one clock by the flip-flop 18 is calculated by a subtractor 19, and a difference signal as shown in FIG. As shown in FIG. 9D, the peak detection circuit 20 generates a peak detection pulse which becomes H level at the position where the value of the difference signal becomes maximum. The horizontal counter 22 is reset by this peak detection pulse, and a horizontal reference pulse is output from the phase signal output terminal 23 as a phase reference signal.

[0008]

In the example in which the phase reference is detected from the 4/7 fsc sine wave included in B25 to B27, when the accumulated gate signal and the peak detection gate signal are shifted by several clocks due to a shift of a synchronization signal or the like. There is a possibility that the position of the peak is shifted by one cycle (7 clocks) due to the shift of the capturing position of the 4/7 fsc pulse. For example, FIG.
If the accumulated gate signals in (b) and (d) are delayed by three clocks, the signal fetch position is shifted by one cycle, so the output peak position is delayed by seven clocks from the correct position. .

In the example in which the phase reference is detected at the falling edge of B1, when the S / N is poor, accumulation for several tens of fields is performed by an inter-field accumulation circuit in order to detect without being affected by noise. Must be taken and it takes a long time to detect.

[0010]

According to the present invention, in order to solve the above-mentioned problems, 4 / 7fs included in the 25th to 27th bits of the second generation EDTV identification control signal is provided.
c by detecting the peak of the sine wave of frequency c
And means for synchronizing the sine wave and the phase, means for generating a pulse frequency of 4 / 7fsc the synchronized phase as the reference, and means for sampling the identification control signal by said pulse, said identification control sampled Detects the falling position of the first bit signal and issues a detection pulse
Means for raw, synchronized with the sine wave and the phase the 4 /
Logical product of the pulse frequency of 7fsc and the detection pulse
And a means for generating a phase reference pulse signal. 2. The phase reference detection circuit for a second generation EDTV identification control signal according to claim 1, further comprising:

In order to solve the above problem, according to the present invention, a peak of a sine wave having a frequency of 4/7 fsc included in the 25th to 27th bits of the second generation EDTV identification control signal is further detected. The sine wave and the position
And means for synchronizing the phases, the synchronized phase as the reference 4 / means for generating a pulse frequency of 7Fsc, the <br/> identification control signal for each period of the pulse frequency of the 4 / 7Fsc means for accumulating, by detecting the falling edge position of the first bit signal of the identification <br/> another control signal said cumulatively added
Means for generating a detection pulse and synchronizing the sine wave and phase
It has been the detected path and pulse frequency of the 4 / 7fsc
Means for generating a phase reference pulse signal by performing a logical AND operation with a pulse signal of the second generation EDTV identification control signal.

[0012]

According to the phase reference detection circuit of the first aspect, the second
The 25th to 27th bits of the generation EDTV identification control signal
Peak of a sine wave with a frequency of 4/7 fsc included in the unit
By detecting, by synchronizing the sine wave and the phase,
Generating a <br/> pulse frequency of 4 / 7fsc the basis of the synchronization phase. To support <br/> sampling the identification control signal by the pulse. The sampled identification control signal
Detection pulse by detecting the falling position of the first bit signal of
And the 4/7 phase synchronized with the sine wave
The logical product of a pulse having a frequency of fsc and the detection pulse is
And generates a phase reference pulse signal.

In the phase reference detecting circuit according to the second aspect,
From the 25th bit of the second generation EDTV identification control signal to the second
Of synchronizing the sine wave and the phase by detecting a peak <br/> over click of 4 / frequency 7fsc sine waves contained in the 7-bit
Allowed, frequency of 4 / 7fsc the basis of the synchronization phase
To generate a number of pulses. The identification control signal is transmitted to the 4/7
The cumulative addition is performed for each period of the pulse having the frequency of fsc.
Standby of the signal of the first bit of the discrimination control signal obtained by the product addition
A detection pulse is generated by detecting a down position. The sine wave
The 4/7 fsc frequency pulse synchronized in phase with
And a logical reference of the detection pulse and a phase reference pulse signal.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. The same reference numerals are given to the same components as those of the above-described conventional example, and the description thereof is omitted.

The video signal quantized by the A / D converter 5 is supplied to a 4/7 fsc band pass filter 6 and a delay circuit 12. After the filter 6, the noise is reduced by the period accumulation circuit 7 and the peak detection pulse which becomes H level at the position where the signal input by the peak detection circuit 10 becomes maximum is generated as in the conventional example. The 7-clock counter 11 is reset by the peak detection pulse, and FIG.
As shown in (a), a 7CLK pulse signal which becomes H level for one clock period is output every seven clocks.

The B1 falling portion of the video signal as shown in FIG. 2B is delayed by the delay circuit 12 until the peak of the sine wave of 4/7 fsc is detected, and then the difference circuit 29
Supplied to

In the difference circuit 29, first, the first flip-flop 18A thins out the data every seven system clocks by the 7CLK pulse as shown in FIG. 2C. The difference between the decimated signal and a signal obtained by delaying the signal by one cycle of the 7CLK pulse by the flip-flop 18B is calculated by the subtractor 19 to obtain a difference signal as shown in FIG.
Then, as shown in FIG. 2E, the peak detection circuit 20 generates a peak detection pulse which becomes H level at the position where the difference signal becomes maximum. An AND circuit 21 ANDs the peak detection pulse and the 7CLK pulse to output an output signal as shown in FIG.
Reset pulse. Then, the horizontal counter 22 outputs one clock period H every horizontal cycle (910 clocks).
A horizontal reference pulse having a level is output from the phase reference signal output terminal 23.

Next, a second embodiment of the present invention will be described with reference to FIGS.

As shown in FIG. 4A, a 7CLK pulse signal which is at the H level for one clock period every seven clocks is generated by a sine wave of 4/7 fsc as in the first embodiment.

The B1 falling portion of the video signal as shown in FIG. 4B is delayed by the delay circuit 12 until the peak of a sine wave of 4/7 fsc is detected.
3 is supplied. In the accumulation circuit 13, when the 7CLK pulse signal becomes H level, the flip-flop 15
Is reset. The input signal is added to the output of the flip-flop 15 by the adder 14, and the sum signal is supplied to the flip-flops 15 and 16. In the flip-flop 16, data is latched at the falling edge of the 7CLK pulse signal. That is, as shown in FIG. 4C, a signal accumulated in the section from the rising of the seven clock pulse to the rising is output. In the difference circuit 28, the difference between the accumulated signal and the signal obtained by delaying the accumulated signal by one cycle of the 7CLK pulse by the flip-flop 18 is calculated by the subtractor 19, and FIG.
A differential signal as shown in FIG. As shown in FIG. 4E, the peak detection circuit 20 generates a peak detection pulse which becomes H level at the position where the difference signal becomes maximum. An AND circuit 21 ANDs the peak detection pulse and the 7CLK pulse to output an output signal as shown in FIG.
(0 clock) A reset pulse of the counter 22. From the horizontal counter 22, a horizontal reference pulse that is at the H level for one clock period every horizontal cycle (910 clocks) is output from the phase reference signal output terminal 23.

The present invention can be applied not only to the above embodiment but also to the following cases.

(1) When a phase reference signal generating circuit other than the horizontal counter is used. (2) When detecting the phase of a 4/7 fsc sine wave using another method such as detecting a peak by taking a difference of one clock. (3) A case in which a sine wave of 4/7 fsc is accumulated between fields in order to further increase noise resistance. (4) A case where the delay control circuit does not use the delay circuit to detect the peak of the B1 difference signal but uses the identification control signal of the next field in which the 4/7 fsc peak is detected. (5) The falling part of B1 is a low-pass filter (LPF)
When performing peak detection after passing through. (6) When detecting the falling portion of B1 instead of taking the difference of one clock and detecting the peak, using another method.

[0023]

According to the phase reference detection circuit of the first aspect, the 25th bit of the second generation EDTV identification control signal is used.
Sine of the frequency of 4/7 fsc contained in the 27th bit
The pulse of the frequency of 4/7 fsc synchronized with the wave and the phase
And the first bit of the sampled identification control signal.
Detecting the falling position of the signal
Since the AND operation is performed to generate the phase reference pulse signal, the stability of the phase reference signal is improved. Further, the detection time can be reduced as compared with the case where the phase reference detection is performed using only the falling edge in B1. According to the phase reference detection circuit of the second aspect, since B1 is accumulated for each section of 7 clocks, it is more resistant to noise.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a phase reference detection circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory waveform diagram of the phase reference detection circuit according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a phase reference detection circuit according to a second embodiment of the present invention.

FIG. 4 is an explanatory waveform diagram of a phase reference detection circuit according to a second embodiment of the present invention.

FIG. 5 is a waveform diagram of an identification control signal.

FIG. 6 is a configuration diagram of a conventional phase reference detection circuit.

FIG. 7 is a configuration diagram of a conventional phase reference detection circuit.

FIG. 8 is an explanatory waveform diagram of a conventional phase reference detection circuit.

FIG. 9 is an explanatory waveform diagram of a conventional phase reference detection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Video signal input 2 Clock generation circuit 3 Synchronization separation circuit 4 Control signal generation circuit 5 A / D converter 6 4/7 fsc Band pass filter 7 Period accumulation circuit 10 Peak detection circuit

Claims (2)

(57) [Claims] 1. A twenty-fifth generation EDTV identification control signal.
By detecting the peak of the sine wave having a frequency of 4/7 fsc contained in the 27th bit from the 27th bit,
Means for synchronizing the phase, means for generating a pulse frequency of 4 / 7fsc the synchronized phase as the reference, and means for sampling the identification control signal by said pulse, first sampled the identification control signal Means for detecting the falling position of a 1-bit signal to generate a detection pulse, and the 4/7 fsc synchronized in phase with the sine wave
Phase reference detecting circuit of the second-generation EDTV identification control signal, characterized in that it comprises a means for generating a take-position <br/> phase reference pulse signal a logical product of the frequency pulse and the said detection pulses. 2. The 25th generation of the second generation EDTV identification control signal.
By detecting the peak of the sine wave having a frequency of 4/7 fsc contained in the 27th bit from the 27th bit,
Means for synchronizing the phase, means for generating a pulse frequency of 4 / 7fsc the synchronized phase as the reference, pre
Means for accumulating the serial identification control signals for each cycle of the pulse frequency of the 4 / 7fsc, detects the falling position of the first bit signal of the <br/> identification control signal which is the cumulative addition
Means for generating a detection pulse Te, the sine wave and the phase same
Synchronize the pulse frequency of the 4 / 7fsc and the detection
Means for calculating a logical AND with a pulse to generate a phase reference pulse signal, the phase reference detection circuit for a second generation EDTV identification control signal.