JP3312089B2 - Phase reference detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a second generation EDTV.
(Extended Definition Tele
vision) receiver, the 4th bit included in the 25th to 27th bits of the second generation EDTV identification control signal.
The present invention relates to a phase reference detection device that detects the phase of a sine wave signal having a frequency of / 7 fsc.

[0002]

2. Description of the Related Art In order to identify a second generation EDTV broadcast, a second signal at the top of the screen of each field in a video signal is used.
It has been proposed to insert a second generation EDTV identification control signal (hereinafter, referred to as an identification control signal) into line 2 and line 285. As shown in FIG. 10, the identification control signal is composed of 27 bits, and one bit period is 3.58.
MHz for 7 cycles of the color subcarrier (7SC = 1.95
μs). 1st bit (B1), 2nd bit (B
In 2), a reference signal serving as a phase reference for all signals, an identification signal in the third bit (B3) to 23rd bit (B23), and a 25th bit (B25) to 27th bit (B
27), a confirmation signal for discrimination from the current NTSC video signal is assigned to each.

In the identification control signal, the first bit (B1) to the fifth bit (B5) are in NRZ format, and the 25th bit (B25) to the 27th bit (B27) are of a carrier waveform type (carrier suppression amplitude modulation). ). This 25th
The carrier of the confirmation signal in the bit (B25) to the 27th bit (B27) is a sine wave of 4/7 (4/7 fsc) of the frequency fsc of the color subcarrier. The control (phase) information in the identification control signal is represented by the boundary of each bit area and the phase of the confirmation signal.

On the other hand, in the second generation EDTV, a reinforcement signal of a horizontal resolution of a still picture (hereinafter referred to as an HH signal) frequency-multiplexed in a main screen, and a vertical resolution of a moving picture multiplexed in a mask portion above and below the main screen. Reinforcement signal (hereinafter, VT
Three types of augmentation signals (hereinafter, referred to as VH signals) multiplexed in the upper and lower mask portions of the main screen.

In the HH signal, the phase of the carrier used for demodulation from the transmission format on the receiving side must match the carrier phase used on the transmitting side.
In the case of the T signal and the VH signal, when the receiving side expands the time axis from the upper and lower mask portions to the main screen three times, the VT / VH signal expanded three times is returned to the original predetermined position on the main screen. Standards are required.

Therefore, in order to reproduce these augmented signals, a phase reference signal which is strong against noise and can be detected quickly is required. The 25th bit (B25) to the 25th bit (B25) of the discrimination control signal are required. 4 included in 27 bits (B27)
The phase reference signal is generated using a sine wave signal having a frequency of / 7 fsc.

The 25th bit (B25) of the discrimination control signal
A conventional phase reference detection device that generates a phase reference signal using a sine wave signal having a frequency of 4/7 fsc included in the 27th bit (B27) will be described below with reference to FIGS. Here, FIG. 11 is a block diagram showing a conventional phase reference detecting device, and FIG. 12 is an explanatory diagram showing waveforms of respective parts in the conventional phase reference detecting device.

In a conventional phase reference detecting device, a video signal input from an input terminal 1 is supplied to a clock generation circuit 2,
The signal is supplied to the synchronization separation circuit 3 and the A / D converter 5. In the clock generation circuit 2, the signal locked to the color burst signal
A system clock of fsc is generated and supplied to each block. The synchronization separation circuit 3 separates the horizontal synchronization signal and the vertical synchronization signal from the video signal, and the control signal generation circuit 4 generates various control signals for controlling each block.

The video signal digitized by the A / D converter 5 is a 4/7 fsc band pass filter (hereinafter referred to as B
The signal is band-limited by a PF 6 and is supplied to the cycle accumulation circuit 7 as a signal as shown in FIG. The signal input to the adder 8 of the cycle accumulation circuit 7 is as shown in FIG.
25-th bit (B25) of the identification control signal as shown in FIG.
In accordance with the cumulative gate signal which becomes high level in the section of the 27th bit (B27), the output of the adder 8 is added to the signal obtained by delaying the output of the adder 8 by 7 clocks by the shift register 9 in the high level section of the cumulative gate signal.

The frequency of the sine wave signal of the input signal is 4 /
Since the sampling frequency is 7 fsc, sampling by a system clock having a frequency of 4 fsc is one cycle of seven clocks. Accordingly, the cycle accumulating circuit 7 adds signals having the same phase, and thus has a noise reduction function.

Further, as shown in FIG. 12 (c), the signals are accumulated in the above-mentioned section in synchronization with the peak detection gate signal which becomes high in the period of 7 clocks included in the last one cycle of the accumulated gate signal. A one-cycle sine wave signal as shown in FIG. In the peak detection circuit 10, as shown in FIG. 12 (e), a peak which becomes a high level at a position where the input sine wave signal is maximum (in an actual circuit, the position is delayed by a certain number of clocks). A detection pulse is generated and output from the phase reference signal output terminal 11 as a phase reference signal.

[0012]

The sampling clock (system clock) used for the identification signal processing is created by reproducing the fsc from the color burst and multiplying the fsc by four. It corresponds to the phase 1: 1. For this reason, the color burst (fsc) that determines the sampling clock phase according to the frequency characteristic of the SAW filter in the modulator on the transmitting side, that is, the group delay characteristic (depending on the transmitting station), the number of relay stations, or the like, has a large group delay. May have occurred. The sampling clock phase undergoes a phase change under the influence of the group delay.

On the other hand, 4/27 bits (B25) to 27th bits (B27) of the identification control signal
Since a sine wave signal with a frequency of 7 fsc has a smaller amount of group delay than a color burst, a relative phase change occurs between the sine wave signal with a frequency of 4/7 fsc and the sampling clock with a frequency of 4 fsc. .

That is, in the above-described conventional phase reference detecting device, as shown in FIG.
When the sine wave signal having the frequency of c and the sampling position are constant in an ideal relationship, the peak point a can be detected. However, as shown in FIG. 14.3 MHz)
When the period is shifted by 周期 cycle (= 35 ns), the point b and the point c have the same level.
There has been a problem that the phase fluctuates between point c and point c, and a stable phase reference signal cannot be obtained.

When the phase reference signal fluctuates, the phase of the demodulated carrier of the HH signal also fluctuates. Therefore, the phase of the demodulated HH signal also fluctuates, and the time axis elongation of the VT / VH signal is tripled. Since the reference fluctuates, a phenomenon occurs in which the VT / VH signal expanded on the time axis fluctuates left and right. In particular, in the case of a still image, only the reinforcement signal moves (vibrates), which impairs image quality. There was a problem.

The present invention has been made in view of the above points, and has been made in consideration of the 25th bit (B2
5) to 4/7 fsc included in the 27th bit (B27)
It is an object of the present invention to provide a phase reference detection device capable of detecting a stable reference phase signal even when the phase detection result of the sine wave signal of the frequency fluctuates.

[0017]

According to a first aspect of the present invention, there is provided a phase reference detecting apparatus comprising: 4 / 7fs included in bits 25 to 27 of a second generation EDTV identification control signal.
an A / D converter for digitally converting a sine wave signal having a frequency of c;
In a phase reference detecting apparatus comprising: a phase detecting means for detecting a phase of a sine wave signal having a frequency of 7 fsc; a fluctuation detecting means for detecting a fluctuation of a phase detected by the phase detecting means; If but detected, put the sine wave signal of a frequency of the 4 / 7fsc
Between the sampling points
And a sampling point converting means.

[0018]

[0019]

A phase reference detecting apparatus according to a second invention of the present application, as the fluctuation detecting means in the first invention, a counting means for counting the frequency of the timing position of the detection result in the phase detecting means a plurality of times, A maximum value detecting means for detecting a maximum value of the count value counted by the counting means; and a variation of the detection result in the peak detection circuit based on the count value of the maximum value detected by the maximum value detecting means. And a fluctuation determining means for determining the presence or absence.

According to a third aspect of the present invention, as the phase reference detecting apparatus according to the second aspect of the present invention, the fluctuation detecting means further selects the most frequent timing position counted by the counting means, A majority decision means for outputting as a signal is provided.

The phase reference detection apparatus according to the fourth invention of the present application is an A / A converter for digitally converting a sine wave signal having a frequency of 4/7 fsc contained in the 25th to 27th bits of the second generation EDTV identification control signal. A D converter and the A / D
A phase detecting means for detecting a phase of a sine wave signal having a frequency of 4/7 fsc which is digitally converted by the converter; a phase detecting means for detecting a motion of an image; And updating means for updating the detection result by the phase detecting means when a motion of the video image is detected by a predetermined amount or more.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a phase reference detecting apparatus according to the present invention will be described below with reference to FIGS. 1 to 3. The same reference numerals are used for the same parts as those in the above-mentioned conventional example. Is omitted. Here, FIG. 1 is a block diagram illustrating a phase reference detection device according to the present embodiment, FIG. 2 is a block diagram illustrating a toggle circuit according to the present embodiment, FIG. 3 is a block diagram illustrating a fluctuation detection circuit according to the present embodiment, and FIG. 5 is a timing chart showing each input signal of the fluctuation detection circuit in the present embodiment.

In FIG. 1, reference numeral 12 denotes -1 to a sine wave signal having a frequency of 4/7 fsc which has been cycle-accumulated by the cycle accumulation circuit 7.
A selection circuit 13 for switching between the sine wave signal (A input) output from the period accumulation circuit 7 and the sine wave signal (B input) phase inverted by the sign inversion circuit 12; Reference numeral 14 denotes a fluctuation detection circuit that detects a fluctuation of the peak detection position detected by the peak detection circuit 10 and outputs a fluctuation determination signal. 15 denotes a toggle every time the fluctuation of the peak detection position is detected by the fluctuation detection circuit 14. This is a toggle circuit that generates a signal (which alternates between a high level and a low level) and supplies it to the control terminal S of the selection circuit 13 as a selection signal.

In the above configuration, the toggle circuit 15
2, as shown in FIG. 2, is composed of an EX-OR circuit 15a and a D-type flip-flop circuit 15b, and inverts the polarity of the output signal when a high-level signal of one clock width is input. .

In the phase reference detecting device constructed as described above, the period accumulating circuit 7
The sine wave signal having the frequency of fsc is supplied to the A input terminal of the sign inverting circuit 12 and the selecting circuit 13. The sign inverting circuit 12 multiplies the input sine wave signal by -1 to select the signal.
3 B input terminal. The selection circuit 13 selects one of the A and B inputs based on a selection signal from the toggle circuit 15 and supplies the selected input to the peak detection circuit 10.

The peak detection circuit 10 outputs a peak detection pulse that goes high at the position where the input signal is maximum. The fluctuation detection circuit 14 compares the peak detection positions over a plurality of fields. The presence / absence of a change is detected, and if there is a change in the peak detection position, a pulse representing the change (a change determination signal) is output from the toggle circuit 15.
Output to The toggle circuit 15 outputs a low level in an initial state, and supplies a signal that toggles every time a pulse of 1 clock width representing a change is input from the change detection circuit 14 to the selection circuit 13 as a selection signal. The output is switched and selected.

For example, when the relationship between the sine wave signal having a frequency of 4/7 fsc and the sampling point is as shown in FIG. 13A, the selection circuit 13 selects the A input, and the peak detection circuit 10 A which is a positive peak position
A point will be detected. On the other hand, when the relationship between the sine wave signal of the frequency of 4/7 fsc and the sampling point is as shown in FIG. 13B, the fluctuation detecting circuit 14 changes the peak detection pulse between the points b and c. Is detected, the output of the toggle circuit 15 becomes high level, the selection circuit 13 selects the B input, and the peak detection circuit 10 detects the point d which is a negative peak position.

That is, in the phase reference detection device of the present embodiment, the sine wave signal having a frequency of 4/7 fsc is a signal having a period of 7 clocks and an odd period, so that the sampling point is located at a positive (negative) peak position. If there is, there is no sampling point at the negative (positive) peak position, and there are two sampling points of the same level in the vicinity thereof, and if the peak detection position fluctuates, The phase of the sine wave signal having the frequency of 4/7 fsc is inverted, and the phase of the sine wave signal having the frequency of 4/7 fsc is detected again. This makes it possible to reliably detect the peak position of the sine wave signal having a frequency of 4/7 fsc, and to obtain a stable phase reference signal.

Next, the fluctuation detecting circuit 1 in the present embodiment
4 will be described in detail below with reference to FIGS. 3 and 4.

In FIG. 3, reference numeral 21 denotes an input terminal to which a peak detection pulse from the peak detection circuit 10 at the preceding stage is input;
Reference numerals 22 to 25 denote input terminals to which various timing signals A to D from the control signal generation circuit 4 are input. 26
Is an AND circuit which takes the logical product of the peak detection pulse and the timing A signal so that it becomes a high level with a width of 7 clocks only once in one field period, and 27 is a 7 for holding the count values of the 7 types of peak detection results The stage flip-flop circuit 28 is an adder for adding a peak detection pulse to the output data of the seven-stage flip-flop circuit 27.

The loop composed of the seven-stage flip-flop circuit 27 and the adder 28 is for counting the frequency of the phases of the seven peak detection pulses, and the number of bits of this loop data is used for peak fluctuation detection. Determined by the number of fields, for example, as shown in FIG. 4, when peak fluctuation detection is performed over eight fields, the maximum possible value of the loop data is eight, which requires four bits. Similarly, for example, in the case of 16 fields, the maximum value that the loop data can take is 16, so
Five bits are required.

Reference numeral 29 denotes a seven-stage flip-flop circuit 2
AND circuit for ANDing the output loop data (count value of peak detection pulse) from 7 and the timing B signal which becomes high level with 7 clock widths only once in 8 field periods (maximum count value detection period) , 30 is a flip-flop circuit for holding the maximum value, 31 is a selection circuit for switching and selecting the maximum value data (A input) from the flip-flop circuit 30 and new loop data (B input) from the AND circuit 29, and 32 is a selection circuit. The new loop data (A input) from the AND circuit 29 and the maximum value data (B input) from the flip-flop circuit 30 are compared, and A is compared with B input.
The comparison circuit outputs a low level when the input is small and outputs a high level when the A input is larger than the B input.

When the output A> B of the comparison circuit 32 is at a low level, the selection circuit 31
The signal (A input) from 0 is selected, and the output data of the flip-flop circuit 30 is not updated. On the other hand, the comparison circuit 32
When the output A> B is at a high level, the selection circuit 31 selects the signal (input B) from the AND circuit 29 and updates the output data of the flip-flop circuit 30. By repeating such an operation for seven clocks, the maximum value of the loop data finally remains in the flip-flop circuit 30.

The reference numeral 33 compares the maximum value (A input) of the loop data from the flip-flop circuit 30 with a threshold value k (for example, k = 5) (B input). If it is smaller, set the low level to A
A comparison circuit that outputs a high level when the input is large,
Numeral 34 denotes a comparison result output of the comparison circuit 33, counting of eight fields and detection of the maximum value of the count value (7 clock periods).
Is an AND circuit which takes a logical product with the timing C signal which goes high in one clock width after the completion of
This is a fluctuation determination signal output terminal for outputting the fluctuation determination signal converted into a signal of one clock width by the circuit 34 to the toggle circuit 15 in the next stage.

The timing D signal is a signal for resetting the flip-flop circuit after a series of fluctuation detection processing is completed and preparing for the next fluctuation detection processing. The seven-stage flip-flop circuit 27 and the flip-flop circuit 3
0 is supplied to each clear terminal.

In the above configuration, the AND circuit 26,
Counting means is provided by the seven-stage flip-flop circuit 27 and the adder 28, and maximum value detecting means is provided by the flip-flop circuit 30, the selection circuit 31, and the comparison circuit 32.
The comparison circuit 33 constitutes a variation determination unit.

In the fluctuation detecting circuit configured as described above, the AND circuit 26 supplies the peak detecting pulse to the adder 28 only while the timing A signal is at the high level. This is because the identification control signal is sent only once in one field, the peak detection result is updated for each field, and there are seven phases of the peak detection result.

Then, in a loop composed of a seven-stage flip-flop circuit 27 and an adder 28, the frequency of the phases of the seven peak detection pulses is counted, and the AND circuit 2
At 9, the count value is supplied to the selection circuit 31 and the comparison circuit 32 only while the timing B signal is at the high level. This is because the count value is output as loop data during the maximum value detection period (7 clock widths) after the completion of the counting of eight fields.

The comparison circuit 32 compares the maximum value data held in the flip-flop circuit 30 with the new data supplied from the AND circuit 29. If the new data is larger, the new data is used as the maximum value data. The output data of the flip-flop circuit 30 is updated. Such an operation is repeated for seven clocks, and finally the data held in the flip-flop circuit 30 is supplied to the comparison circuit 33 as the maximum value of the loop data.

In the output data of the flip-flop circuit 30, the peak detection pulse is always input at the same timing when there is no change in the peak detection result. Become. On the other hand, when there is a variation in the peak detection result, the maximum value of the count value is a value less than 8. Therefore, the comparison circuit 33 compares the peak value with the threshold value k, and if the maximum value is equal to or less than the threshold value k, outputs a high level indicating that there is a change, thereby determining whether there is a change in the peak detection result.

The AND circuit 34 outputs the comparison result of the comparison circuit 33 only while the timing C signal is at the high level. This is because, when there is a change, the detection of the maximum value in the seven clock period is completed, and during the period when the detected maximum value is held in the flip-flop circuit 30, the next toggle circuit 1
This is for outputting a high-level signal of one clock width for switching the polarity of the output of No. 5.

As described above, the fluctuation detecting circuit according to the present embodiment detects that the relationship between the sine wave signal having the frequency of 4/7 fsc and the sampling point is as shown in FIG. 13B. In addition, since the frequency of each phase of the peak detection result is counted a plurality of times and detected based on the fluctuation of the count value, the detection is performed based on the difference between the respective quantization levels at adjacent sampling points. In comparison with this, it is possible to easily and surely detect the impulse noise or the like which affects the sampling value.

A second embodiment of the phase reference detecting apparatus according to the present invention will be described with reference to FIG. 5. The same reference numerals are used for the same parts as those in the first embodiment, and the description is omitted. Here, FIG. 5 is a block diagram showing the phase reference detection device of the present embodiment.

In FIG. 5, reference numeral 16 denotes a signal from the clock generation circuit 2 in response to a signal supplied from the toggle circuit 15.
This is a clock switching circuit that inverts and outputs the phase of the fsc system clock.

In the phase reference detection device having the above-described configuration, the peak detection circuit 10 outputs a high-level peak detection pulse at a position where the input signal is maximum. The circuit 14 detects the presence or absence of a change by comparing the peak detection positions over a plurality of fields, and if there is a change in the peak detection position, outputs a pulse representing the change to the toggle circuit 15. The toggle circuit 15 outputs a low level in the initial state, and supplies a signal that toggles every time a pulse representing a change is input from the change detection circuit 14 to the clock switch circuit 16. The clock switch circuit 16 outputs a 4 fsc system clock. Are switched and output.

For example, when the relationship between the sine wave signal having the frequency of 4/7 fsc and the sampling point is as shown in FIG. 13A, the clock switching circuit 16 outputs the input 4 fsc system clock as it is. , The peak detection circuit 10 detects the point a which is a positive peak position. On the other hand, the relationship between the sine wave signal having a frequency of 4/7 fsc and the sampling point is shown in FIG.
In the case shown in FIG. 3 (b), the fluctuation detecting circuit 14 detects the fluctuation of the peak detection pulse between the points b and c, so that the output of the toggle circuit 15 becomes high level and the clock switching circuit 16 Outputs the inverted 4 fsc system clock phase.

Therefore, the sampling clock phase is 1 /
Since the period changes by two periods, the A / D converter 5 samples the intermediate point between the points b and c, so that the state shown in FIG.
The peak position of the sine wave signal having a frequency of 7 fsc can be detected, and a stable phase reference signal can be obtained.

Also, in this embodiment, 4/7 fs
When the peak detection phase of the sine wave signal having the frequency of c fluctuates, the phase of the sampling clock is changed, so that the sampling phase approaches a more accurate sampling phase. Therefore, the television signal can be sampled by the sampling clock having the correct phase, and the reinforcing signal can be reproduced more accurately.

Further, the third reference of the phase reference detecting apparatus of the present invention
This embodiment will be described with reference to FIG. 6. However, the same reference numerals are used for the same portions as those in the first and second embodiments, and the description thereof will be omitted. Here, FIG. 6 is a block diagram showing the phase reference detection device of the present embodiment.

In FIG. 6, reference numeral 17 denotes a one-clock delay circuit for delaying one cycle of a sine wave signal having a frequency of 4/7 fsc accumulated by the cycle accumulation circuit 7, and reference numeral 18 denotes a sine wave signal output from the cycle accumulation circuit 7. And a sine wave signal delayed by the one-clock delay circuit 17. The one-clock delay circuit 17 and the adder 18 form an interpolation filter having a simple configuration. The sum of two samples is calculated and supplied to the selection circuit 13.

In the phase reference detection device having the above-described configuration, the peak detection circuit 10 outputs a high-level peak detection pulse at a position where the input signal is maximum. The circuit 14 detects the presence or absence of a change by comparing the peak detection positions over a plurality of fields, and if there is a change in the peak detection position, outputs a pulse representing the change to the toggle circuit 15. The toggle circuit 15 outputs a low level in an initial state, and supplies a signal to be toggled as a selection signal to the selection circuit 13 every time a pulse representing a change is input from the change detection circuit 14, and switches the output of the selection circuit 13. select.

For example, when the relationship between a sine wave signal having a frequency of 4/7 fsc and the sampling point is as shown in FIG. 13A, the selection circuit 13 selects the A input, and the peak detection circuit 10 A which is a positive peak position
A point will be detected. On the other hand, when the relationship between the sine wave signal of the frequency of 4/7 fsc and the sampling point is as shown in FIG. 13B, the fluctuation detecting circuit 14 changes the peak detection pulse between the points b and c. Is detected, the output of the toggle circuit 15 becomes high level, the selection circuit 13 selects the B input, and the peak detection circuit 10 detects the peak point from the output result of the interpolation filter.

That is, in the phase reference detecting apparatus of the present embodiment, the signal as shown in FIG. 13B is subjected to the interpolation filter processing, so that the intermediate point between two adjacent sampling points, that is, 1 /. When a sampling point shifted by two periods is calculated and a sampling point similar to a waveform as shown in FIG. 13A is calculated, when the peak detection position fluctuates, 4/7 fsc is used. Is interpolated at the sampling point of the sine wave signal having the frequency of, and again detects the phase of the sine wave signal having the frequency of 4/7 fsc. This makes it possible to reliably detect the peak position of the sine wave signal having a frequency of 4/7 fsc, and to obtain a stable phase reference signal.

A fourth embodiment of the phase reference detecting apparatus according to the present invention will be described with reference to FIGS. 7 and 8. The same reference numerals are used for the same parts as those in the first to third embodiments. The description is omitted. Here, FIG. 7 is a block diagram showing a phase reference detecting device of the present embodiment, and FIG. 8 is a block diagram showing a majority decision / fluctuation detecting circuit in the phase reference detecting device of the present embodiment.

In FIG. 7, reference numeral 19 denotes the peak detection circuit 10.
This is a majority / fluctuation detection circuit that performs both majority and fluctuation detection of the peak detection position detected by the control circuit, and outputs the result of the fluctuation detection to the toggle circuit 15 and outputs the result of the majority decision as a phase reference signal. Output to terminal 11.

In the present embodiment, the majority decision / fluctuation detection circuit 19 accumulates the timing of the peak detection result detected for each field by the peak detection circuit 10 over a plurality of fields, and determines the highest frequency timing therefrom. Since many are detected, it is possible to detect and output a more accurate phase reference signal which is not affected by noise or the like.

In FIG. 8 showing a specific configuration of the majority / fluctuation detection circuit 19, reference numeral 36 denotes a seven-digit counter circuit comprising a NOR circuit 36a, a 3-bit counter 36b, and an AND circuit 36c. When the output of the 3-bit counter 36b becomes "1, 1, 0",
Alternatively, the timing is determined by being reset when the maximum value of the peak detection position is detected by the comparison circuit 32, and a signal having a period of 7 clocks is output to the phase reference signal output terminal 11 as a phase reference signal. It is.

In the present embodiment, the majority decision / fluctuation detection circuit 19 is configured so that the majority decision and the fluctuation detection of the peak detection position are performed in combination. Can be simplified. In addition, since the presence or absence of the fluctuation is determined based on the frequency of the fluctuation of the peak detection phase, the detection result fluctuates at the time of the peak detection, but this fluctuation is absorbed by using the majority decision together. This makes it possible to reproduce a reinforcing signal without shaking.

Next, a fifth embodiment of the phase reference detecting apparatus of the present invention will be described with reference to FIG.
The same reference numerals are used for the same parts as in the fourth to fourth embodiments,
The description is omitted. Here, FIG. 9 is a block diagram showing the phase reference detection device of the present embodiment.

In FIG. 9, reference numeral 41 denotes a one-frame delay circuit for delaying and inverting the video signal digitized by the A / D converter 5 by one frame, and reference numeral 42 denotes a signal from the A / D converter 5 and a one-frame delay. Adding the signals from the circuit 41,
An adder 43 for generating an inter-frame difference signal;
An absolute value converting circuit 44 for converting the one-frame difference signal from 2 into an absolute value, 44 accumulates the absolute value of the one-frame difference signal in the absolute value circuit 43 in the field to reduce the motion amount of the field. The intra-field accumulation circuit to be created, 45, compares the amount of motion created by the intra-field accumulation circuit with a predetermined threshold, and sets a high level when the amount of motion is large, and a high level when the amount of motion is small. Is a motion determining circuit that outputs a low level.

An AND circuit 46 calculates the logical product of a peak detection pulse from the peak detection circuit 10 and an output signal from the motion determination circuit 45. 47 is reset by the output of the AND circuit 46 and has a pulse of 7 clock cycles. Is a seven-digit counter circuit.

In the above configuration, the one-frame delay circuit 41, the adder 42, the absolute value conversion circuit 43, the intra-field accumulation circuit 44, and the motion determination circuit 45 serve as a motion detection means. 47 constitutes updating means.

In the phase reference detecting device configured as described above, the one-frame delay circuit 41 and the adder 42
A difference signal between one frame is created by the above. A signal obtained by converting the difference signal between one frame into an absolute value by an absolute value circuit 43 is accumulated in a field by an intra-field accumulation circuit 44,
Create the amount of motion for that field. Motion determination circuit 45
The AND circuit 46 supplies a peak detection pulse to the ternary counter circuit 47 only when it is determined that the amount of movement is larger than the predetermined threshold value, and adjusts the output timing of the ternary counter circuit 47. Update.

Normally, when the timing of the phase reference signal is changed, the augmentation signal also moves along with the change. In particular, the movement of the augmentation signal is conspicuous at the time of a still image, but according to the phase reference detection apparatus of this embodiment, Since the amount of motion of the image is detected and the timing of the phase reference signal is changed (at the time of a moving image) in a field having a large amount of motion, the fluctuation of the reinforcement signal can be made inconspicuous.

In the above-described first to fifth embodiments of the present invention, the peak detecting circuit 10 for detecting a positive peak value (maximum value) is used as a phase detecting means of a sine wave having a frequency of 4/7 fsc. However, the present invention is not limited to this. For example, a method for detecting a negative peak value (minimum value) or a maximum slope point of falling / rising (a certain sampling point is set one Falling / obtained by subtracting from the sampling point of
It is apparent that the detection of the point (the point where the rising edge is the largest) may be used.

[0067]

According to the phase reference detecting device of the present invention, when the peak detection result fluctuates, it is 4/7.
Interpolate the sampling points of the sine wave signal at fsc frequency
Since the peak detection of the sine wave signal having the frequency of 4/7 fsc is performed again, the 4/7 fsc is reliably detected with a simple configuration.
, It is possible to detect the peak position of the sine wave signal having the frequency of, and to obtain a stable phase reference signal.

[0068]

[0069]

The phase reference detecting apparatus according to the second aspect of the present invention counts the frequency of the peak detection result for each phase a plurality of times and detects the fluctuation from the count value, so that the peak detection can be performed easily and reliably. Variations in the result can be detected.

The phase reference detecting apparatus according to the third aspect of the present invention counts the frequency of each phase of the peak detection result a plurality of times, and there are many peak detection results from the count value. Thus, the fluctuation of the phase reference signal can be reduced. In addition, by using the majority decision means and the fluctuation detecting means together, a simpler circuit configuration can be obtained.

In the phase reference detecting apparatus according to the fourth aspect of the present invention, the timing of the phase reference signal is changed at a position where the amount of motion of the video is large. Can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a phase reference detection device of the present invention.

FIG. 2 is a block diagram showing a toggle circuit in the first embodiment of the phase reference detection device of the present invention.

FIG. 3 is a block diagram showing a fluctuation detection circuit in the first embodiment of the phase reference detection device of the present invention.

FIG. 4 is a timing chart showing input signals of a fluctuation detection circuit in the first embodiment of the phase reference detection device of the present invention.

FIG. 5 is a block diagram showing a second embodiment of the phase reference detection device of the present invention.

FIG. 6 is a block diagram showing a third embodiment of the phase reference detection device of the present invention.

FIG. 7 is a block diagram showing a fourth embodiment of the phase reference detection device of the present invention.

FIG. 8 is a block diagram showing a majority / fluctuation detection circuit in a fourth embodiment of the phase reference detection device of the present invention.

FIG. 9 is a block diagram showing a fifth embodiment of the phase reference detection device of the present invention.

FIG. 10 is a schematic explanatory diagram showing a second generation EDTV identification control signal.

FIG. 11 is a block diagram showing a conventional phase reference detection device.

FIG. 12 is a timing chart showing input signals in a conventional phase reference detection device.

13A illustrates a state in which a sine wave signal having a frequency of 4/7 fsc and a sampling position are constant in an ideal relationship, and FIG. 13B illustrates a state in which the phase of a sampling clock changes by 周期 cycle. FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Video signal input terminal 2 Clock generation circuit 3 Synchronization separation circuit 4 Control signal generation circuit 5 A / D converter 6 Band pass filter 7 Period accumulation circuit 10 Peak detection circuit 11 Phase reference signal output terminal 12 Sign inversion circuit 13 Selection circuit 14 Fluctuation detection circuit 15 Toggle circuit 16 Clock switching circuit 17 1 clock delay circuit 18 Adder 19 Majority decision / fluctuation detection circuit 21 Peak detection pulse input terminal 26 AND circuit 27 Seven-stage flip-flop circuit 28 Adder 29 AND circuit 30 Flip-flop circuit 31 Selection circuit 32 Comparison circuit 33 Comparison circuit 34 AND circuit 35 Fluctuation determination signal output terminal 36 Hexadecimal counter circuit 41 1-frame delay circuit 42 Adder 43 Absolute value conversion circuit 44 In-field accumulation circuit 45 Motion determination circuit 46 AND circuit 47 Susumu counter circuit

Continuation of the front page (72) Inventor Takao Suzuki 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (56) References JP-A-7-298214 (JP, A) (58) Fields investigated (Int) .Cl. ⁷ , DB name) H04N 7/015

Claims (4)

(57) [Claims] 1. A 25th generation EDTV identification control signal
4/7 fsc frequency included in bit 27 to bit 27
A / D converter for digitally converting a number of sine wave signals, and 4/7 fsc digitally converted by the A / D converter
Phase detection means for detecting the phase of a sine wave signal having a frequency of
A phase reference detection device comprising: detecting a phase change detected by the phase detection means.
The fluctuation detecting means, and when a fluctuation is detected by the fluctuation detecting means,
Sampling in a sinusoidal signal with a frequency of 4/7 fsc
Sampling point conversion by interpolating between sampling points
Phase reference detection, characterized in that the phase reference detection means is provided.
apparatus. 2. The phase reference detecting device according to claim 1, wherein :
In the above, the fluctuation detecting means includes a detection result of the phase detecting means.
Count timing location frequency multiple times
Counting means, and the maximum value of the count value counted by the counting means
Value detection means for detecting the maximum value, and a count value of the maximum value detected by the maximum value detection means.
The fluctuation of the detection result in the peak detection circuit based on the
And fluctuation determining means for determining presence or absence.
Phase reference detector. 3. The phase reference detecting device according to claim 2,
In the above , further, the most frequency counted by the counting means
Select a high-timing timing position and output it as the phase reference signal.
Phase reference detection characterized by the provision of
Output device. 4. A twenty-fifth generation EDTV identification control signal.
4/7 fsc frequency included in bit 27 to bit 27
A / D converter for digitally converting a number of sine wave signals, and 4/7 fsc digitally converted by the A / D converter
Phase detection means for detecting the phase of a sine wave signal having a frequency of
A motion detection means for detecting motion of a video, and a motion of a predetermined or more video is detected by the motion detection means.
Update the detection result of the phase detection means
Phase reference detection device characterized by comprising updating means.
Place.