JPH0440788A - Television receiver - Google Patents

Abstract

PURPOSE:To execute clear display without out-of-focus not only in a still part but also in a moving picture part in the case of video software by discriminating a video signal converted from a movie film from the other video signals precisely and finding the group of fields converted from a same frame. CONSTITUTION:A means 16 to detect a difference between the one frame of an input video signal, a integrator 19 to integrate the detected said difference, a discriminating means 20 to discriminate whether the component of a 5-field cycle exists in integrator output or not and so on are provided. When it is discriminated by the means 20 that the component of the 5-field cycle exists, the number of times of the repeating of display in the display means of the same video signal of a one frame portion outputted from a signal converting circuit 5 is controlled to the specified number. Thus, inter-field scanning line interpolation is always executed and movie software is converted into the non- interlace scanning signal of double density scanning without deteriorating resolution and is screen-displayed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides movie software (
For example, when a movie film shot at 24 frames per second is converted into a video signal with 607 field scans per second by a telecine device, the number of horizontal scanning lines is converted to double density to produce high image quality. This invention relates to a television receiver that can display television programs.

(Prior Art) Conventionally, ordinary television receivers display video signals with a 2:1 interlaced scanning structure, so the number of scanning lines per field is as small as 262.5. The resolution of the image was insufficient.For this reason, the still image part is interpolated using information from adjacent fields, and the moving image part is interpolated using information from vertically adjacent scanning lines within the same field. , a television that uses so-called motion-adaptive scanning line interpolation to sequentially scan (non-interlaced) a video signal with an interlaced scanning structure, and doubles the number of scanning lines to achieve higher image quality. Receivers were proposed (for example, Japanese Patent Laid-Open No. 58-77
(See Publication No. 373 "Television Signal Processing Circuit").

[Problem to be solved by the invention]

In the above-mentioned conventional technology, when performing scanning line interpolation to convert an interlaced scanning video signal to a non-interlaced scanning video signal, for the moving image part,
Since scanning lines for interpolation are created from scanning lines that are adjacent to each other in the vertical direction, there is a problem in that when the input video signal is movie software, the vertical resolution of the image deteriorates.

This will be explained in more detail below.

FIG. 7 is an explanatory diagram of the relationship between the number of frames of a movie film and the number of fields of a video signal as movie software.

That is, Figure 7 (a) shows the frames of a movie film as a, b,
FIG. 7B shows only three frames in chronological order as shown in FIG.

When converting movie film into a video signal (movie software), the movie has 24 frames per second.

Since the television signal has 60 fields per second, the first frame (a
) to create a 2-field (1, 2) signal, and the next 1
From frame (b), a signal of 3 fields (3, 4, 5) is created, and from the next frame (c), a signal of 2 fields (6, 7) is created, and so on. It creates a 5-field signal. In other words, 2
While a frame is (2/24) seconds - (1/12) seconds, 5 fields is (5/60) seconds = (1/12) seconds, so the two coincide in time. That's why there is.

Since the television signal performs 2:1 interlaced scanning, one field has 262.5 scanning lines, and two fields have a total of 525 scanning lines. That is, in FIG. 7, frame (a) of the movie film is scanned with 525 scanning lines in fields 1 and 2. Furthermore, frame (b) is scanned with 525 scanning lines in fields 3 and 4, and field 5 is a repetition of field 3.

That is, if we focus on field 3 and field 5,
Field 3 and field 5 perform horizontal scanning of the same position, so field 3 and field 5 are in the same frame (b
) will be horizontally scanned at the same position, and in principle the signals are exactly the same.

In FIG. 7, field 1.2 of the television signal
was created by interlaced scanning from the same frame (a) of a movie film, so fields 1.2 are It is best to create a non-interlaced screen (a high-quality screen with twice the scanning line density) by using Creating scanning lines for interpolation actually impairs image quality.

The present invention detects this on the receiver side when movie software converted to a television signal is received, and the field is always displayed regardless of whether the image content is a still image or a moving image. Perform inter-scan line interpolation,
An object of the present invention is to provide a television receiver that converts movie software into non-interlaced scanning signals of double-density scanning without resolution deterioration and enables high-quality screen display.

[Means for Solving the Problems] In order to achieve the above object, it is first necessary to detect that the input video signal is movie software. A feature of movie software is that, as already explained with reference to FIG. 7, the same information as the previous frame is sent once every five fields. That is, in FIG. 7(b), fields 1 and 2 target the same frame (a), but since they are the results of interlaced scanning, their information contents are not the same. Fields 2 and 3 are intended for different frames (a) and (b), respectively, so their information contents are not the same. Fields 3 and 4 target the same frame (b), but because they are the results of interlaced scanning, their information content is not the same.

Field 5 is a repeat of field 3, so
Field 5 has exactly the same information content as field 3. The same can be said of field 6 and subsequent fields.

In this way, it is detected that the input video signal is movie software from the fact that the same information as the previous frame is sent once every five fields.

Once this was detected, it determined which fields were transformed from the same frame and used them to create a complete frame image (a double-density, non-interlaced scan signal).

[Effect]

As mentioned above, the signal converted from the film is sent once every five fields with the same information as the previous frame, so the difference between frames becomes smaller once every five fields. Therefore, when the inter-frame difference is integrated for approximately one screen to determine the amount of change from one frame before that screen, this amount of change has a characteristic that it decreases once every five fields.

Therefore, by detecting the periodicity of this 5-field period, it becomes possible to reliably determine the signal converted from the film.

℃ Example] Hereinafter, an example of the present invention will be described with reference to FIG. 1st
The figure is a block diagram showing one embodiment of the present invention.

In the figure, 1 is an input terminal to which a luminance signal in a video signal is input, 2 is an output terminal to which a double-density scan-converted luminance signal is output, and 3 is a horizontal synchronization signal for double-density scanning. Output terminal, 4 is an output terminal that outputs a vertical synchronization signal,
It is.

5 is an A/D converter that converts the input luminance signal from analog to digital, 6.7 is a field memory that stores signals for one field each, 8゜11.13 is a changeover switch, and 9 and 12 are time axis compression circuits. , 10 is a line memory that delays the signal by one horizontal scanning period, 15 is a subtraction circuit,
16 is a low pass filter (LPF), 17 is LPF16
This is an absolute value circuit for obtaining amplitude information of the output of .

18 is a gate circuit; 19 is an integration circuit that integrates the output of the absolute value circuit 17 for approximately one field; 20 is a period determination circuit that determines whether or not the output of the integration circuit has periodicity of 5 field periods; and 21 is a period determination circuit. 22 is a phase comparison circuit (PD); 23 is a voltage-controlled optical oscillator (VCO) that oscillates at a frequency 2N times that of the horizontal sync signal; 24 is 1 /2 frequency divider, 25 is a 2/N frequency divider, 26 is a 1/2 frequency divider (22 to 2
Please note that 6 constitutes a PLL circuit),
27 is a vertical synchronization separation circuit that separates a vertical synchronization signal from an input luminance signal, 28 is a control signal generation circuit, and 29 is a gate circuit.

When converting a movie film into a video signal, a movie has 24 frames per second and a television signal (video signal) has 60 fields per second. As shown in the figure, a 2-field signal is created from the first frame, a 3-field signal is created from the next frame, and a 2-field signal is created from the next frame, and so on. A 5-field signal is created from each frame.

Since the television signal performs 2:1 interlaced scanning, one field has 262,5 scanning lines, resulting in a total of 525 scanning lines in two fields, a complete 525 scanning lines.

In other words, in Figure 2, field 1 and field 2
Thus, frame (a) of the movie film is scanned with 525 scanning lines. Also, field 3 and field 4
Alternatively, in fields 4 and 5, frame b is scanned with 525 scanning lines.

Now, focusing on fields 3 and 5, as mentioned earlier, fields 3 and 5 perform horizontal scanning of the same position, so fields 3 and 5 are at the same position of the same frame (b). Horizontal scanning will be performed, and in principle the signals will be exactly the same.

Therefore, the output of the A/D converter 5, which is the input signal,
The output of the subtraction circuit 15 that performs subtraction with the output of the field memory 7, which is a signal delayed by one frame, becomes zero or a value close to it over the entire screen only when the input signal is this field 5 (here, , field memory 6
is a field memory that delays the signal by 263H (H: 1 horizontal scanning period), field memory 7 is a memory that delays the signal by 262H, and the total delay of both is 525H, that is, one frame).

The luminance signal is created by removing the color signal component from the composite video signal, but generally this color signal component cannot be completely removed. Since the subcarrier of this color signal has the property that the phase is inverted every frame, this color signal component causes a difference component even in the case of field 5, so the LP
This effect is removed by passing through Fl 6. This LPF1
Since the difference in the output of 6 is a signal of both positive and negative polarity, the absolute value circuit 17 calculates the absolute value of the difference.

This absolute value is integrated over approximately one field period by an integrating circuit 19, and the difference in that field is determined.

If it is a video signal converted from a movie film, as mentioned above, there is a field with a smaller difference than other fields once every five fields, so the period determination circuit 20 determines the difference once every five fields. , the existence of a field with a small difference and the position of the field are detected (a specific example of the configuration of the period determination circuit 20 will be described later).

On the other hand, the output of the absolute value circuit 17 provides the difference between frames for each pixel, which determines whether the image of that pixel is the same as the previous frame, that is, whether it is still or moving. The second output is used to control the information of the interpolated scan line above the pixel.

That is, when the output of the absolute value circuit 17 is zero, it is a still image position, so the changeover switch 11 selects a field that is a signal 263H before (that is, a signal at the position of the interpolated scanning line captured in the previous field). When the output of the memory 6 is selected and the output of the absolute value circuit 17 is not zero, it is a moving image position, so the changeover switch 11 converts the information before IH in the same field delayed by the line memory 10 to the information of the interpolated scanning line. The output of the absolute value circuit 17 is applied as a switching control signal to the changeover switch 11 via the gate 18 which is in an open state at this time.

The current signal and this interpolated scanning line signal are time-compressed by time-base compression circuits 9 and 12 so that the time-base becomes 1/2, and the changeover switch 1 is pressed in the first half of the original horizontal scanning period.
In step 3, the output of the time axis compression circuit 12, which is the interpolation scanning line signal, is first selected, and in the second half, the output of the time axis compression circuit 9, which is the current signal, is selected, thereby obtaining a double-density scanning signal.

On the other hand, if the input video signal is movie software, gate 18
is turned off by the output of the period determination circuit 20, so the gate 1
The output of field memory 6 is always zero, and the output of field memory 6 is always output to changeover switch 11.

On the other hand, the output of the control signal generation circuit 28 is as shown in FIG.
), a control signal having a predetermined phase relationship with the vertical synchronization signal is output (a specific example of this generation method will be described later). During the period when this control signal is high,
The changeover switch 8 selects the output of the field memory 7, which is the signal of one frame before, and selects the output of the A/D converter 5, which is the current signal, during the low period. 29, the output of the control signal generation circuit 28 is applied to the changeover switch 8 as a changeover control signal.

In other words, when field 2 in Figure 2 (b) is input (part (2) in Figure 3), the current signal, Figure 2 (b)
When field 3 is input (part (3) in FIG. 3), the signal from one frame before is selected.

Since the changeover switch 11 always selects the information one field before, the output of the changeover switch 13 includes the second
When field 2 in Figure (b) is input, the signal of field 2 and the signal of field 1, which is the signal one field before, are selected, and when field 3 is input, the signal of field 1, which is the signal two fields before. field 2
Field 1, which is the signal one field before, is selected.

Similarly, in field 4, field 3 and field 4
However, in field 5, field 4 and field 5 are
In field 6, field 4, field 5, and field 5 are selected. Therefore, the displayed signal becomes like the display signal shown in FIG. 2(c).

As shown in Figure 2, this combination of fields (field 1 and field 2, field 3 and field 4)
．． Fields 4 and 5) are a combination of signals of the same frame, and a complete frame image is reproduced.

The gate 29 is turned off when the period determination circuit 20 determines that there is no periodicity and is fixed at a low level, so in this case the current signal is always selected in the switch 8.

Here, a specific example of the period determination circuit 20 is shown in FIG.

In FIG. 4, 101 is an input terminal to which the output of the integrating circuit 19 is input, 102 is an input terminal to which the output of the vertical synchronization separation circuit 27 is input, 103 is an adder, and 104 to 108
is a register group for delaying the output result of the adder 103 in units of one field, and 109 to 112 are registers 104.
This is a group of comparators that compares the output of the register with the output of other registers.

113.122 is an AND gate, 114 to 117 are AN
A group of flip-flops (FF) that delay the output of the D gate 113 in units of one field, 118 to 121 are inverters, 123 is reset by the output of the AND gate 122 and counts the vertical synchronization signal, and the count value is a constant value of 6 or more. (For example, 7) A counter that goes high when it counts more than 7; 124 is an output terminal that outputs a signal to control the control signal generation circuit 28; 125 is an output that outputs a signal to control the gate circuits 18 and 29. It is a terminal.

A value integrated over one field period is input from an input terminal 101, passes through an adder 103, and is delayed by five fields by registers 104 to 108. 1
Since it is added with the input from 01, adder 103 adds 5
The five addition results added for each field are stored in five registers 104-108.

Each of the comparators 109-112 determines whether the output of the register 104 is smaller than the output of the other registers 105-108 by a certain value or more, and outputs a high signal if the output is smaller than the output of the other registers 105-108, and otherwise outputs a low signal. Then, in the case of movie software, the frame of the field corresponding to field 5 is stored in the register 104 during the vertical synchronization period immediately after the field corresponding to field 5 in FIG. Since the difference between is input, at this time,
All four comparators 109-112 will output high.

Meanwhile, the other four fields (fields 1 to 4)
In the field immediately after the period corresponding to , the information in field 5 corresponding to cono field 5 is stored in registers 105 to
Since the signal is held in one of the registers 108, one of the comparators 109 to 112 will always output a low signal, and the AND gate 113 will output a low signal. In this way, the AND gate 113 has one in five fields.
The field has a period of going high and the others going low.

The FFs 114 to 117 and the AND gate 122 are configured so that a high signal can be output only when only one field among these five fields is in a high state.

In this way, periodicity once every five fields can be obtained more accurately.

In the case of normal software other than movie software, there is no such special bias, so on average, the difference is almost the same in 5 fields, and no field is particularly small, so the comparator 109 Since the circuits 112 to 112 generally output low, the AND gate 113 always outputs low.

Therefore, in the case of movie software, a control signal is outputted from the output terminal 124, which is one field high every five fields.

On the other hand, the counter 123 becomes high when the vertical synchronization signal is counted 6 or more (for example, 7), but in the case of movie software, it is always reset by the output of the AND gate 112 once every 5 fields, so in the case of movie software is always output low.

In other cases, the AND gate 122 does not output a high level and is not reset, so that fields 7 and above are always high, making it possible to distinguish between movie software and other cases.

FIG. 5 shows a specific example of the control signal generation circuit 28 that generates a control signal based on the output of the output terminal 124 of the period determination circuit 20.

In FIG. 5, 201 is an input terminal for inputting the vertical synchronization signal, 202 is an input terminal for inputting the output signal of the period determination circuit 20, 203 to 205 are FF groups forming a 115 frequency divider circuit, and 206 is a 115 frequency divider 207 and 208 are an OR gate and an AND gate for generating a control signal from the output of the FF group of this 115 frequency divider circuit, and 209 is a control signal output terminal. FF203~
The FF 205 performs a frequency division operation by 115 using the vertical synchronization signal as a clock.

Here, as shown in FIG. 6, the output of the period determination circuit 20 becomes high at a position corresponding to field 6 in FIG. 2 (b), so if a reset is applied at this rising edge, the output of each FF (ji) in Figure 6.

(iv), (v). The desired output is (vi) in FIG.

This is the low period of the Q output of FF205, and
Since both the Q output of FF 207 and the Q output of FF 204 exclude the low period, the OR gate 207. AND
A desired control signal can be generated at gate 208.

As explained above, the period determination circuit 20. All of the control signal generation circuits 28 can be easily created using logic circuits. It goes without saying that this construction method is not limited to that shown in FIGS. 4 and 5.

For example, in FIG. 4, synchronization can be determined using only the information of each field without using the adder 103. However, in this case, there is a possibility that the two frames are the same and there is almost no difference between them, and the output cannot be output. In this case, the count value of the counter 123 should be increased. Therefore, it is necessary to make some modifications such as making it possible for the output of the AND gate 122 to be missing.

Further, although only the luminance signal is shown in FIG. 1, it is clear that the interpolation scanning line for the color signal can be constructed in exactly the same manner as for the luminance signal. In this case, the control signal is
Of course, the control signal generated from the luminance signal shown in FIG. 1 can be used in common.

〔Effect of the invention〕

As explained above, the present invention can accurately distinguish a video signal converted from a movie film from other video signals, and can also accurately determine a set of fields converted from the same frame. As a result, it is possible to generate a display signal for double-density scanning of a complete frame image, so in the case of movie software, it is possible to display clear, blur-free images not only in still parts but also in moving parts.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the relationship between conversion from a movie film to a video signal and television screen display according to the present invention, and FIG. 4 is a circuit diagram showing a configuration example of the period determination circuit in FIG. 1, and FIG. 5 is a configuration example of the control signal generation circuit in FIG. 1. 6 is a timing diagram showing waveforms of various parts in the circuit of FIG. 5, and FIG. 7 is an explanatory diagram showing the relationship between the two when converting a movie film to a video signal. Explanation of symbols 6.7...Field memory, 8, 11.13...
Changeover switch, 9.12... Time axis compression circuit, 15.
...Subtraction circuit, 16...LPF, 17...Absolute value circuit, 19...Integrator circuit, 20...Period determination circuit, 2
8...Control signal generation circuit, 18.29...Gate agent Patent attorney Akio Namiki (ili) FF203■C1 (Iυ) 0 of FF204 (υ) Q of FF205 (Vl) output #i61111

Claims (1)

[Claims] 1. A video signal having an interlaced scanning structure is input,
a signal conversion circuit that generates and outputs a one-frame video signal having a double-speed non-interlaced scanning structure by alternately arranging two adjacent fields of the video signal every scanning line; A television receiver comprising: display means for displaying one frame worth of video signal from a conversion circuit; means for detecting a difference between one frame of the input video signal; and means for integrating the detected difference. an integrator; a determining means for determining whether or not there is a 5-field period component in the output of the integrator; control means for controlling the number of repetitions of displaying the same video signal for frames on the display means to a specific number;
A television receiver characterized by comprising: