JP3229920B2 - Wide clear vision identification control signal detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an apparatus for detecting an identification control signal of wide clear vision.

[0002]

2. Description of the Related Art FIG. 10 shows a waveform of an identification control signal used in wide clear vision. This waveform is inserted into the 22nd and 285th lines of the video signal during wide clear vision broadcasting. .

A conventional device for detecting the identification control signal will be described with reference to FIGS.

In FIG. 11, a video signal input from a video signal input terminal 1 is a low-pass filter 2, 4/7 fsc.
The signal is supplied to the bandpass filter 4, the delay circuit 6, the fsc bandpass filter 7, and the control signal generation circuit 11. The control signal generating circuit 11 separates a vertical synchronizing signal and a horizontal synchronizing separation signal from the video signal, and generates various control signals for controlling each circuit block from each synchronizing signal.

The horizontal control signal generation section included in the control signal generation circuit 11 has a configuration as shown in FIG. In the figure, a horizontal synchronizing signal HD is separated from an input video signal by a horizontal synchronizing separation circuit 17. The clock input terminal 15 supplies a clock having a frequency four times as high as the color subcarrier frequency fsc locked to the burst signal. The counter circuit 19 outputs the horizontal synchronizing signal H
Reset at any falling edge of D and set clock to 1
Count and reset for 910 cycles, which is the horizontal period,
It has a configuration to repeat 910 counts again, and the output of the counter is supplied to the counter decode circuit 20. The counter decode circuit 20 generates a control signal that switches between high and low according to the count value for each circuit block, and outputs the control signal to each block.

In FIG. 11, the low frequency component of the video signal supplied to the low-pass filter 2 is extracted, and the DC component detecting circuit 3 converts the DC component of the latter half of the identification control signal (for example, B25 to B27 in FIG. If it is determined that the signal is at the pedestal level, a high signal is output to the combining circuit 13 if the signal is not at the pedestal level.

The video signal supplied to the 4/7 fsc band-pass filter 4 is 4/7 fsc (about 2.04 MHz).
The frequency component of z) is extracted, and the 4/7 fsc component detection circuit 5 adds 4/7 fs to the identification control signals B25 to B27.
When it is determined that the c component is present, a high signal is output to the combining circuit 13 when the c component is not present.

The fsc component of the video signal supplied to the fsc bandpass filter 7 is extracted and the fsc component is extracted.
The signal is demodulated by the demodulation circuit 8 at the same phase fsc as the burst signal, and output to the switching circuit 9.

The video signal supplied to the delay circuit 6 is fs
The signal is delayed by an amount corresponding to the processing of the c-bandpass filter 7 and the demodulation circuit 8 and output to the switching circuit 9. The switching circuit 9 supplies the bit decoding circuit 10 with the demodulated output from the fsc demodulation circuit 8 for the fsc modulation portions B6 to B23 in FIG. 10 and the output from the delay circuit 6 for the other portions.

The bit decoding circuit 10 has the configuration shown in FIG. 13, and a signal input from an input terminal 22 is supplied to an accumulation circuit 24. The accumulation circuit 24 is configured as shown in FIG. 14, and receives an accumulation gate pulse signal from the control signal generation circuit via the accumulation gate input terminal 23. When the gate pulse signal is low, the output of the gate circuit 36 is cleared, but when the gate pulse signal goes high, the gate circuit 36 becomes active, the input signal is accumulated by the adder 35, and the accumulation result is output via the output terminal 37. It is supplied to thirteen comparison circuits 26. The comparison circuit 26 compares the input signal with the threshold from the threshold generation circuit 25, and generates a high signal when the input signal is larger than the threshold and a low signal when the input signal is smaller than the threshold. For example, the input signal is as shown in FIG.
When the gate pulse signal is as shown in FIG. 15B, the accumulated output is as shown in FIG. Here, when the threshold value is represented by a broken line, the accumulation result becomes larger than the threshold value, and a high signal is output as a decoded output.

When both the output of the DC component detecting circuit 3 and the output signal of the 4/7 fsc component detecting circuit 5 become high, the synthesizing circuit 13 outputs a bit decoded signal from the output terminal 14 as an identification signal output.

[0012]

In the above conventional apparatus, when a control signal is generated from a synchronization signal, the control signal may be shifted due to instability of synchronization separation due to a ghost signal or a pixel shift on the transmission side. . For example, if the accumulated gate pulse signal deviates from the correct position as shown in FIG. 15D, the accumulated output becomes as shown in FIG. 15E, the accumulated result falls below the threshold value, and the signal is erroneously detected as low. Will be.

Further, if the accumulation section of the accumulation circuit is made longer, the number of bits becomes larger, so that the hardware scale becomes larger.

[0014]

Means for Solving the Problems In order to solve the above problems,
According to the present invention, there is provided an apparatus for detecting a wide clear vision identification control signal, comprising: a means for generating a control signal including a gate pulse indicating an accumulation period from a horizontal synchronization signal; and means for controlling a phase of the control signal. When,
Means for accumulating a given bit in the discrimination control signal over the accumulation section, and means for detecting a largest one of a plurality of accumulation results obtained by shifting the phase of the control signal, The apparatus according to claim 1, wherein a phase of the control signal is adjusted so that a result is maximized.

[0015] In order to solve the above problems, according to the present invention,
Further, an apparatus for detecting an identification control signal of a wide clear vision, comprising: means for generating a control signal including a gate pulse indicating an accumulation period from a horizontal synchronization signal; means for controlling a phase of the control signal; Means for accumulating a given bit in the signal over the accumulation interval, means for comparing the accumulation result with a threshold value to detect an identification control signal, and means for shifting the phase of the control signal And means for determining an intermediate value of the determined range, wherein the phase of the control signal is adjusted to an intermediate value of the determined range. 2. An apparatus for detecting an identification control signal according to item 2.

According to the present invention, there is further provided an apparatus for detecting an identification control signal of a wide clear vision, wherein two consecutive continuous signals indicating a first and a second cumulative interval from a horizontal synchronization signal are provided. Means for generating a control signal including a gate pulse; means for controlling the phase of the control signal; means for accumulating a given bit in an identification control signal over the first accumulation interval; Means for accumulating bits adjacent to the second bit over the second accumulation section, means for calculating the difference between the accumulation results of the two accumulation means, and a plurality of bits obtained by shifting the phase of the control signal. 4. A means for detecting a maximum difference among the accumulation results, wherein the phase of the control signal is adjusted so that the difference between the accumulation results becomes the maximum. An apparatus for detecting an on-board identification control signal is provided.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention is shown in FIG.
Description will be made using 2, 3, and 4.

In FIG. 1, the DC component of the input signal and 4/7
The part for detecting the fsc component and the part for fsc demodulation of the discrimination control signal are the same as those in the above-described conventional example, and thus the description thereof will not be repeated.

FIG. 2 shows the configuration of the horizontal control signal generator included in the control signal generator 11a. In the figure, a horizontal synchronization signal HD is separated from an input video signal by a horizontal synchronization separation circuit 17a. The clock input terminal 15 supplies a clock having a frequency four times as high as the color subcarrier frequency fsc locked to the burst signal. When the power is turned on, an initial value A set in advance is supplied from the initial value input terminal 16 to the counter circuit 18a. The counter circuit 18a loads the initial value A from the initial value control circuit 18a at an arbitrary fall of the horizontal synchronization signal HD, and counts the clock. Count value is 9
When it reaches 09, it is reset to 0 at the next clock. The counter is repeated from 0 to 909, and the output of the counter is supplied to the counter decode circuit 19a. The counter decode circuit 19a generates a control signal that switches between high and low according to the count value for each circuit block,
The data is output from the output terminal 20 to each block. Here, when data of Ak is given from the initial value input terminal 16, the counter is reloaded as the initial value Ak. Therefore, the count value is shifted by k clocks later, and the control signal is delayed by k clocks.

In FIG. 1, B6 from fsc demodulation circuit 8
The demodulated outputs B2 to B23 and the portions B1 to B5 delayed by the delay circuit 6 by the amount required for the demodulation processing are switched by the switching circuit 9 and supplied to the bit decoding circuit 10a.

FIG. 3 shows the configuration of the bit decoding circuit 10a. The horizontal phase adjustment operation will be described below with reference to FIGS. From the signals input from the bit decoding input terminal 21, the bit B1 in the identification signal is used as a signal to be used as shown in FIG. First, a preset constant A is output from the initial value control circuit 128 via the output terminal 30. Using this initial value, the horizontal control signal generating section generates an accumulated gate pulse having the same width as the bit width (28 cycles with a clock of 4 fsc) as shown in FIG. You. Since the bit decoding input signal is accumulated during the period when the accumulation gate pulse is high, the accumulated output is as shown in FIG.
As shown in (c), the value of the accumulation result SUM and the initial value A at that time are written in the memory 126. Subsequently, the initial value data output from the initial value control circuit 128 is reduced.

For example, when An is output, the accumulated gate pulse signal is delayed by n clocks as shown in FIG. Therefore, the accumulated output is as shown in FIG. This accumulated result is stored in the maximum value detection circuit 127 in the memory 12.
The new accumulated result and the initial value are written to the memory 126 when the current accumulated result is larger than the accumulated result written to the memory 126 and compared with the value written to the memory 126.
Similarly, the data output from the initial value control circuit 128 is A
(Where N is a preset constant), and the point at which the cumulative result becomes the maximum is detected. When the point at which the accumulation result becomes the maximum is detected, the initial value at that time is stored in the memory 126 from the initial value control circuit 128 and the output terminal 30.
And supplies it to the horizontal control signal generator via the control unit, and enters a normal operation mode. The following bit decoding operation is the same as in the conventional example, and a description thereof will be omitted.

Next, a second embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. The description of the same parts as those in the first embodiment will be omitted.

From among the signals input from the bit decoding input terminal 21, the bit B1 in the identification signal is used as a signal to be used here as shown in FIG. 6A. First, a preset constant A is output from the initial value control circuit 228 via the output terminal 30. Using the initial value, the horizontal control signal generator generates an accumulated gate pulse having a width smaller than the bit width as shown in FIG. Since the bit decoding input signal is accumulated while the accumulation gate pulse is high, the accumulated output is as shown in FIG. The accumulated result is compared with the threshold value (broken lines in FIGS. 6C, 6E, and 6G) from the threshold value generating circuit 224 by the comparing circuit 225. Otherwise it outputs a low. The determination circuit 231 does nothing when the output of the comparison circuit 225 is low, but writes the initial value of the initial value control circuit 228 into the memory 226 when the output becomes high. In the case shown in FIG. 6C, the initial value data is not written in the memory 226 since the accumulated result does not exceed the threshold value. As in the above example, the initial value data output from the initial value control circuit 228 is reduced.

For example, when A-n1 is output, the accumulated gate pulse signal is delayed by n1 clocks as shown in FIG. Therefore, the accumulated output is as shown in FIG. 6E, and since the accumulated result exceeds the threshold value, the initial value is stored in the memory 2.
26 is written. When An-n2 is output as an initial value, the accumulated gate pulse signal is delayed by n2 clocks as shown in FIG. 6F, and the accumulated output is as shown in FIG. 6G. Since the accumulated result does not exceed the threshold, the initial value is not written to the data. The data output from the initial value control circuit 228 is changed from A to AN (N is a preset constant), and the initial value data when the output of the comparison circuit 225 goes high is stored in the memory. 226 are sequentially recorded. When the accumulated gate pulse is near the center of B1, the accumulated result exceeds the threshold value.
Then, an intermediate value of the initial value data written in the memory 226 is extracted and supplied to the horizontal control signal generating unit from the output terminal 30 via the initial value control circuit 228, and the operation enters a normal operation mode. In the normal operation mode, the accumulated gate pulse is output from the pulse control signal generation circuit positioned at the center of the bit based on the extracted intermediate value.

Next, a third embodiment of the present invention will be described with reference to FIGS.
This will be described below with reference to FIG. The description of the same parts as those in the above-described embodiment will be omitted.

From among the signals input from the bit decoding input terminal 21, B1 and B2 in the discrimination control signal are used as signals to be used here as shown in FIG. First, a preset constant A is output from the initial value control circuit 328 via the output terminal 30. Using the initial value, the horizontal control signal generator generates an accumulated gate pulse in which two continuous gate pulses having a width smaller than the bit width are generated as shown in FIG.
2 is input. While the first accumulation gate pulse is high, the bit decoded input signal is accumulated, so that the accumulated output S
B1 is as shown in FIG. Similarly, the input signal is accumulated while the second accumulation gate pulse is high, so that the accumulation output SB2 is as shown in FIG. Subtracter 33
In the second, the second cumulative output S1 from the first cumulative output SB1
B2 is subtracted, and the difference signal is as shown in FIG. The difference value DF and the initial value A at that time are written to the memory 326. Subsequently, the initial value data output from the initial value control circuit 328 is reduced.

For example, when An is output, the accumulated gate pulse signal is delayed by n clocks as shown in FIG. Accordingly, the accumulated outputs SB1 and SB2 are as shown in FIGS. 8G and 8H, and the difference signal of the subtractor output is as shown in FIG. 8I. This subtraction result is compared with the value written in the memory 326 by the maximum value detection circuit 327,
If the current subtraction result is larger than the subtraction result written in the memory 326, the new subtraction result and the initial value are stored in the memory 3
26 is written. The data from the initial value control circuit 328 is changed from A to AN (N is a preset constant), and the point at which the subtraction result is maximum is detected. When the point at which the result of the subtraction becomes maximum can be detected, the initial value at that time is supplied from the memory 326 to the horizontal control signal generator via the initial value control circuit 328 and the output terminal 30, and the operation enters the normal operation mode.

Next, a bit composite circuit used in the identification control signal detecting device of the embodiment described above will be described with reference to FIG.

The inside of the accumulating circuit (123 in FIG. 3) included in the bit decoding circuit (10a in FIG. 1) is configured as shown in FIG.

The signal input from the accumulation input terminal 33 is supplied to a comparison circuit 39. The comparison circuit 39 outputs a low signal when the input signal is higher than the threshold and lower when the input signal is higher than the threshold, as compared with the threshold output from the threshold generator 38. Here, as is clear from FIG. 10, B1 to B5 are threshold values corresponding to 20 IRE, and B6 to B6.
23 is switched to be 0 because it is a demodulated output.

The output from the comparison circuit 39 is input to the adder 35. The output of the adder 35 is input to the adder 35 again via the gate circuit 36. An accumulation gate pulse signal is input from the control signal generation circuit via the accumulation gate input terminal 23. When the accumulated gate pulse signal is low, the output of the gate circuit 36 is cleared, and when it becomes high, the input signal of the gate circuit 36 is output. Therefore, the input signal is accumulated by the adder 35 in the section where the accumulated gate pulse signal becomes high, and the accumulation result is outputted from the output terminal 37.

In each of the embodiments described above, the horizontal phase adjustment is performed using the B1 portion, but other bits or a plurality of bits may be used.

In the second embodiment, the parity check results of B3 to B5, the error detection results of B3 to B23, and the like may be used instead of the high / low determination of each bit.

[0035]

According to the first aspect of the present invention, the horizontal control signal generator is controlled so that the accumulated gate pulse is located at the center of the bit of the identification control signal. The identification signal can be detected stably even if it is shifted.

According to the second aspect of the present invention, the horizontal control signal generator is controlled such that the accumulated gate pulse is located at the center of the bit of the identification control signal. Since the identification signal can be detected stably even if it deviates, and the intermediate value of the detectable range of the identification control signal is obtained by calculation, the circuit scale can be reduced as compared with the device according to the first aspect.

According to the third aspect of the present invention, since the horizontal control signal generator is controlled so that the accumulated gate pulse is located at the center of each bit, even if the horizontal synchronization signal is shifted with respect to the identification control signal. An identification signal can be detected stably. Since the difference between the accumulated results of two adjacent bits is obtained, the circuit scale is slightly larger than that of the device according to the first aspect.

[Brief description of the drawings]

FIG. 1 is a block diagram of an identification control signal detection device of the present invention.

FIG. 2 is a block diagram of a horizontal control signal generation unit included in a control signal generation circuit of the identification control signal detection device of FIG.

FIG. 3 is a block diagram of a first embodiment of a bit decoding circuit of the identification control signal detection device of FIG. 1;

FIG. 4 is an explanatory diagram of an operation of the bit decoding circuit in FIG. 3;

FIG. 5 is a block diagram of a second embodiment of a bit decoding circuit of the identification control signal detection device of FIG. 1;

6 is an explanatory diagram of an operation of the bit decoding circuit in FIG.

FIG. 7 is a block diagram of a third embodiment of a bit decoding circuit of the identification control signal detection device of FIG. 1;

FIG. 8 is an explanatory diagram of the operation of the bit decoding circuit in FIG. 7;

FIG. 9 is a block diagram of an accumulating circuit in the bit composite circuit of the identification control signal detecting device of FIG. 1;

FIG. 10 is a waveform chart of an identification control signal of wide clear vision.

FIG. 11 is a block diagram of a conventional identification control signal detection device.

12 is a block diagram of a horizontal control signal generation unit included in a control signal generation circuit of the identification control signal detection device of FIG.

13 is a block diagram of a bit decoding circuit of the identification control signal detection device of FIG.

FIG. 14 is a block diagram of an accumulating circuit in a bit composite circuit of the identification control signal detecting device of FIG. 11;

15 is an explanatory diagram of the operation of the bit composite circuit of FIG.

[Explanation of symbols]

 1, video signal input terminal 2, low-pass filter 3, DC component detection circuit 4, 4/7 fsc band-pass filter 5, 4/7 fsc component detection circuit 6, delay circuit 7, fsc band-pass filter 8, fsc demodulation circuit 9, switching Circuit 10, Bit composite circuit 11, Control signal generation circuit 13, Synthesis circuit 14, Identification signal output terminal

Claims (4)

(57) [Claims] 1. An apparatus for detecting a wide clear vision identification control signal, comprising: means for generating a control signal including a gate pulse indicating an accumulation period from a horizontal synchronization signal; and means for controlling a phase of the control signal. Means for accumulating a given bit in the identification control signal over the accumulation section, and means for detecting the largest one of a plurality of accumulation results obtained by shifting the phase of the control signal, A wide clear vision identification control signal detection device, wherein the phase of the control signal is adjusted so that the accumulation result becomes maximum. 2. An apparatus for detecting a wide clear vision identification control signal, comprising: means for generating a control signal including a gate pulse indicating an accumulation period from a horizontal synchronization signal; and means for controlling a phase of the control signal. Means for accumulating a given bit in the identification control signal over the accumulation section, means for detecting the identification control signal by comparing the accumulation result with a threshold, and shifting the phase of the control signal. Means for determining a detectable range of the identification control signal, and means for determining an intermediate value of the determined range, wherein the phase of the control signal is adjusted to an intermediate value of the determined range. Wide clear vision identification control signal detection device. 3. An apparatus for detecting an identification control signal of a wide clear vision, comprising: a first synchronizing signal;
Means for generating a control signal including two consecutive gate pulses indicating the cumulative interval of the control signal, means for controlling the phase of the control signal, and providing a given bit in the identification control signal over the first cumulative interval. Means for accumulating the bits adjacent to the given bit, accumulating means for accumulating bits adjacent to the given bit over the second accumulation section, means for calculating the difference between the accumulation results of the two accumulating means, and the control signal Means for detecting the largest one of a plurality of cumulative results obtained by shifting the phase of the control signal, and adjusting the phase of the control signal so that the difference of the cumulative results is maximized. Wide clear vision identification control signal detection device. 4. The apparatus according to claim 1, wherein said means for accumulating bits includes means for comparing an input signal with a threshold value, and means for accumulating the comparison result over an accumulation section. The wide clear vision identification control signal detection device according to any one of the above.