JPH08242428A - Phase reference detection circuit - Google Patents

Abstract

PURPOSE: To obtain the phase reference detection circuit in which a phase reference signal with high stability is generated in a short time from a 2nd generation EDTV identification control signal. CONSTITUTION: A peak detection circuit 10 detects a phase of a sine wave with a period of 4/7fsc, and a 7CLK counter 11 generates a pulse signal with a period of 4/7fsc and the same phase as that of the sine wave. A flip-flop 18A samples the vicinity of the trailing of an identification control signal B1 based on the pulse signal and interleaves the control signal with a period of 4/7fsc. A flip-flop 18B and a subtractor 19 calculate a difference from a signal delayed by one period to detect the trailing point of the signal B1. An AND circuit 21 is used to AND a detection signal and a pulse signal with a period of 4/7fsc and to provide an output of a phase reference pulse signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase reference detection circuit for a second generation EDTV identification control signal detection device.

[0002]

2. Description of the Related Art In order to identify a second generation EDTV broadcast, it has been proposed to insert an identification control signal into lines 22 and 285 of a video signal. The identification control signal is composed of 27 bits as shown in FIG. 5, and the 1-bit period is 7 cycles (about 1.95 μs) of the color subcarrier fsc of 3.58 MHz. The 1st bit (B1) to the 5th bit (B5) are NRZ waveforms, and B6 to B2
Signals up to 3 are phase-modulated by fsc, and B25 to B27 are sine waves having a frequency of 4/7 fsc. The phase reference detection circuit produces a phase reference signal used to reproduce the augmented signal.

First, referring to FIGS. 6 and 8, B25 to B27, 4
A conventional phase reference detection circuit that generates a phase reference signal using a / 7fsc sine wave will be described.

The video signal input from the input terminal 1 is a clock generation circuit 2, a sync separation circuit 3, and an A / D converter 5.
Is supplied to. The clock generation circuit 2 generates a system lock signal having a frequency of 4 fsc locked to the burst signal and supplies it to each block. The sync separation circuit 3 separates the horizontal sync signal and the vertical sync signal from the video signal, and the control signal generation circuit 4 generates a signal for controlling each block.

The video signal quantized by the A / D converter 5 is band-limited by a bandpass filter (BPF) 6 of 4/7 fsc, and becomes a signal as shown in FIG. Supplied. Adder 8 of cycle accumulating circuit 7
The signal input to B25-
According to the cumulative gate signal which becomes H level in the section of B27,
In this H level section, the adder output is added to the signal delayed by 7 clocks by the shift register 9. Since the frequency of the sine wave of the input signal is 4/7 fsc, sampling with the system clock having a frequency of 4 fsc is 7 clocks and one cycle. Therefore, the period accumulating circuit 7 adds signals having the same phase, and thus has a noise reducing function. As shown in FIG. 8C, in synchronization with the peak detection gate signal which becomes the H level during the period of 7 clocks included in the last one cycle of the accumulation gate signal, FIG. A sine wave signal of one cycle as shown is input to the peak detection circuit 10. Peak detection circuit 1
At 0, as shown in FIG. 8 (e), a peak detection pulse having an H level is generated at a position where the input signal is maximum (in an actual circuit, a position delayed by a certain number of clocks). . The horizontal reference pulse that is reset by the peak detection pulse and becomes high for one clock every horizontal period (910 clocks) is the phase reference signal output terminal 2.
It is output from 3.

Next, another conventional phase reference detection circuit for generating a phase reference signal using the falling edge of B1 will be described with reference to FIGS. The description of the same parts as those in the previous example will be omitted.

The video signal quantized by the A / D converter 5 is supplied to the inter-field accumulating circuit 24. In the inter-field accumulator circuit 24, as shown in FIGS. 9A and 9B, according to the gate signal which becomes H level in the period of several tens clocks before and after the fall of B1, the input video signal is generated in this H level period. Is added to the output of the memory 26 by the adder 25 and written in the memory 26. The signal written in the memory 26 is read according to the B1 falling gate signal of the next field. By repeating this, the noise-reduced signal is supplied to the difference circuit 17. In the difference circuit 17, the subtractor 19 calculates the difference between the input signal and the signal delayed by one clock by the flip-flop 18, and outputs the difference signal as shown in FIG. 9C. As shown in FIG. 9D, the peak detection circuit 20 generates a peak detection pulse which becomes H level at the position where the value of the differential signal becomes maximum. The horizontal counter 22 is reset by this peak detection pulse, and the horizontal reference pulse is output from the phase signal output terminal 23 as a phase reference signal.

[0008]

In the example in which the phase reference is detected from the 4/7 fsc sine wave included in B25 to B27, when the accumulated gate signal or the peak detection gate signal is deviated by several clocks due to the deviation of the synchronization signal or the like. The position of the peak may be shifted by one cycle (7 clocks) because the position of capturing the 4/7 fsc pulse is displaced. For example, in FIG.
If the cumulative gate signals in (b) and (d) are delayed by 3 clocks, the signal acquisition position is shifted by one cycle, so the output peak position is delayed by 7 clocks from the correct position. .

Further, in the example of detecting the phase reference at the falling edge of B1, if the S / N is bad, the inter-field accumulating circuit accumulates several tens of fields in order to detect without being affected by noise. It takes a long time to detect.

[0010]

In order to solve the above problems, according to the present invention, 4 / 7fs included in the 25th to 27th bits of the second generation EDTV identification control signal.
a means for detecting the phase of a sine wave having a frequency of c, a means for generating a pulse having a frequency of 4/7 fsc on the basis of the detected phase, a means for sampling an identification control signal by the pulse, and a sampled Means for detecting the falling position of the first bit of the identification control signal;
The second generation EDTV according to claim 1, further comprising: a means for generating a phase reference pulse signal whose phase is determined based on the phase of a pulse having a frequency of 7 fsc and the detected fall position. A phase reference detection circuit for the identification control signal is provided.

In order to solve the above problems, according to the present invention, the phase of a sine wave having a frequency of 4/7 fsc included in the 25th to 27th bits of the second generation EDTV identification control signal is further detected. Means, a means for generating a pulse having a frequency of 4/7 fsc on the basis of the detected phase, a means for accumulating an identification control signal for each period of the pulse having a frequency of 4/7 fsc, and Means for detecting the falling position of the first bit of the identification control signal, and generating a phase reference pulse signal whose phase is determined based on the phase of the pulse having the frequency of 4/7 fsc and the detected falling position. The second-generation EDTV identification control signal phase reference detection circuit according to claim 2, further comprising:

[0012]

In the phase reference detection circuit according to the first aspect, the phase of a 4/7 fsc sine wave is detected by a method such as peak detection, and a pulse signal having a 4/7 fsc cycle of the same phase is generated. With this pulse signal, the vicinity of the fall of B1 of the identification control signal is sampled and thinned out to 4/7 fsc cycle. After this, for example, the difference from the signal delayed by one cycle is calculated to detect the fall of B1, and the detected signal and 4 /
A phase reference pulse signal is generated by performing a logical product with the pulse signal of 7 fsc cycle.

In the phase reference detection circuit according to the second aspect,
The phase of a 4/7 fsc sine wave is detected by a method such as peak detection, and a pulse signal with a 4/7 fsc cycle having the same phase as this is generated. The portion near the falling edge of B1 of the identification control signal is accumulated for each cycle of the pulse signal. After this, for example, the difference from the signal delayed by one cycle is calculated and B
The falling edge of 1 is detected, and the phase reference pulse signal is generated by taking the logical product of the detection signal and the pulse signal of 4/7 fsc period.

[0014]

EXAMPLE A first example of the present invention will be described with reference to FIGS. The same elements as those of the above-described conventional example are designated by the same reference numerals, and the description thereof will be omitted.

The video signal quantized by the A / D converter 5 is supplied to the bandpass filter 6 of 4/7 fsc and the delay circuit 12. Similar to the conventional example, after the filter 6, noise is reduced by the cycle accumulating circuit 7 and a peak detection pulse having an H level is generated at a position where the signal input by the peak detection circuit 10 becomes maximum. The 7-clock counter 11 is reset by the peak detection pulse, and FIG.
As in (a), the 7CLK pulse signal that is at the H level for a period of one clock every seven clocks is output.

The B1 falling portion of the video signal as shown in FIG. 2B is delayed until the peak of the 4/7 fsc sine wave is detected by the delay circuit 12, and then the differential circuit 29.
Is supplied to.

In the differential circuit 29, the first flip-flop 18A first decimates the data every 7 system clocks by the 7CLK pulse as shown in FIG. 2 (C). The difference between the decimated signal and the signal delayed by one cycle of 7CLK pulse by the flip-flop 18B is calculated by the subtractor 19 to obtain a difference signal as shown in FIG. 2 (d).
Then, as shown in FIG. 2E, the peak detection circuit 20 generates a peak detection pulse having an H level at the position where the difference signal becomes maximum. By ANDing the peak detection pulse and the 7CLK pulse with the AND circuit 21, the horizontal (910 clock) counter 22 outputs the output signal as shown in FIG.
Reset pulse. Then, from the horizontal counter 22, one clock period H for each horizontal cycle (910 clocks)
A horizontal reference pulse having a level is output from the phase reference signal output terminal 23.

Next, a second embodiment of the present invention will be described with reference to FIGS.

Similar to the first embodiment, a 7CLK pulse signal which is at H level for one clock period is generated every 7 clocks as shown in FIG. 4A by a sine wave of 4/7 fsc.

The B1 falling portion of the video signal as shown in FIG. 4B is delayed until the peak of the sine wave of 4/7 fsc is detected by the delay circuit 12, and then the accumulator circuit 1 is provided.
3 is supplied. In the accumulator circuit 13, when the 7CLK pulse signal becomes H level, the flip-flop 15
Is reset. The input signal is added by the adder 14 to the output of the flip-flop 15, and the sum signal is supplied to the flip-flops 15 and 16. The flip-flop 16 latches the data at the falling edge of the 7CLK pulse signal. That is, as shown in FIG. 4C, signals accumulated in the section from the rising edge of the 7-clock pulse to the rising edge are output. In the difference circuit 28, the difference between the accumulated signal and the signal obtained by delaying the accumulated signal by one cycle of the 7CLK pulse by the flip-flop 18 is calculated by the subtractor 19 and is calculated as shown in FIG.
A differential signal as shown in is obtained. As shown in FIG. 4E, the peak detection circuit 20 generates a peak detection pulse having an H level at the position where the difference signal is maximum. By ANDing the peak detection pulse and the 7CLK pulse by the AND circuit 21, the output signal as shown in FIG.
0 clock) Reset pulse for the counter 22. The horizontal counter 22 outputs a horizontal reference pulse, which is at H level for one clock period every horizontal period (910 clocks), from the phase reference signal output terminal 23.

The present invention can be applied not only to the above embodiment but also to the following cases.

(1) When using a phase reference signal generating circuit other than the horizontal counter. (2) When another method is used to detect the phase of the 4/7 fsc sine wave, such as taking the difference of one clock and detecting the peak. (3) When 4/7 fsc sine wave is accumulated between fields in order to further strengthen noise. (4) When using the discrimination control signal of the next field after detecting the peak of 4/7 fsc without using the delay circuit to detect the peak of the differential signal of B1. (5) Low pass filter (LPF) at the falling edge of B1
When performing peak detection after passing through. (6) When detecting the falling edge of B1, instead of taking the difference of 1 clock and detecting the peak, other methods are used.

[0023]

According to the phase reference detection circuit of the first aspect, 4 / included in the identification control signals B25 to B27.
Since both the phase of the signal having the frequency of 7 fsc and the falling position of B1 are used, the stability of the phase reference signal is improved.
Further, the detection time can be shortened as compared with the case where the phase reference detection is performed using only the falling edge of B1. According to the phase reference detection circuit of the second aspect, since B1 is accumulated for each 7-clock section, it becomes more resistant to noise.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a phase reference detection circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory waveform diagram of the phase reference detection circuit according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a phase reference detection circuit according to a second embodiment of the present invention.

FIG. 4 is an explanatory waveform diagram of a phase reference detection circuit according to a second embodiment of the present invention.

FIG. 5 is a waveform diagram of an identification control signal.

FIG. 6 is a configuration diagram of a conventional phase reference detection circuit.

FIG. 7 is a configuration diagram of a conventional phase reference detection circuit.

FIG. 8 is an explanatory waveform diagram of a conventional phase reference detection circuit.

FIG. 9 is an explanatory waveform diagram of a conventional phase reference detection circuit.

[Explanation of symbols]

 1 Video signal input 2 Clock generation generation circuit 3 Synchronization separation circuit 4 Control signal generation circuit 5 A / D converter 6 4 / 7fsc Band pass filter 7 Period accumulation circuit 10 Peak detection circuit

Claims (2)

[Claims] 1. The 25th of the second generation EDTV identification control signal.
Means for detecting the phase of a sine wave having a frequency of 4/7 fsc included in the 27th bit from the bit, means for generating a pulse having a frequency of 4/7 fsc with the detected phase as a reference, and discrimination control by the pulse Means for sampling the signal, means for detecting the falling position of the first bit of the sampled identification control signal, and 4 / 7fsc
Second-generation EDT, comprising means for generating a phase reference pulse signal whose phase is determined based on the phase of a pulse having a frequency of 1 and the detected fall position.
Phase identification detection circuit for V identification control signal. 2. The 25th of the second generation EDTV identification control signal
Means for detecting the phase of a sine wave having a frequency of 4 / 7fsc included in the bit to the 27th bit, means for generating a pulse having a frequency of 4 / 7fsc on the basis of the detected phase, and an identification control signal Means for accumulating in each cycle of a pulse having a frequency of 4/7 fsc, means for detecting a falling position of the first bit of the accumulated identification control signal, phase of the pulse having a frequency of 4/7 fsc, and the detection Means for generating a phase reference pulse signal whose phase is determined based on the determined fall position, and a phase reference detection circuit for a second generation EDTV identification control signal.