JP3214091B2 - Method for manufacturing thin film transistor - Google Patents
Method for manufacturing thin film transistorInfo
- Publication number
- JP3214091B2 JP3214091B2 JP24907592A JP24907592A JP3214091B2 JP 3214091 B2 JP3214091 B2 JP 3214091B2 JP 24907592 A JP24907592 A JP 24907592A JP 24907592 A JP24907592 A JP 24907592A JP 3214091 B2 JP3214091 B2 JP 3214091B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- thin film
- forming
- layer
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010409 thin film Substances 0.000 title claims description 25
- 238000000034 method Methods 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000012535 impurity Substances 0.000 claims description 45
- 239000004065 semiconductor Substances 0.000 claims description 42
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 69
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 239000010407 anodic oxide Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、液晶表示装置やイメー
ジセンサ等に応用される薄膜トランジスタの製造方法に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor applied to a liquid crystal display, an image sensor, and the like.
【０００２】[0002]
【従来の技術】薄膜トランジスタ（Ｔｈｉｎ Ｆｉｌｍ
Ｔｒａｎｓｉｓｔｏｒ：以下では、ＴＦＴと略記す
る）を例えば液晶表示装置の画素のスイッチング素子と
して用いる場合、ＴＦＴの逆バイアス時のリーク電流
（以下では、オフ電流と記す）は映像信号の保持特性を
悪化させることから、このオフ電流を低減する必要があ
る。また、ＴＦＴの信頼性を向上させることも重要であ
り、そのためにＬＳＩ技術として培われてきたライトリ
ィー・ドープト・ドレイン（Ｌｉｇｈｔｌｙ Ｄｏｐｅ
ｄ Ｄｒａｉｎ，以下ＬＤＤと略す）構造がＴＦＴにも
応用されている。その例が、イクステンテ゛ィット゛・アフ゛ストラクツ・オフ゛
・サ゛・1991・インターナショナル・コンファレンス・オン・ソリット゛・ステート・テ゛ハ゛イセス゛・
アント゛・マテリアルス゛(1991年)第641頁から第643頁(Extended Ab
stracts of the1991 International Conference on Sol
id State Devices and Materials (1991) P641-643)に
記載されている。2. Description of the Related Art Thin film transistors (Thin Film)
When a transistor (hereinafter abbreviated as TFT) is used, for example, as a switching element of a pixel of a liquid crystal display device, a leakage current (hereinafter, referred to as an off-state current) at the time of reverse bias of the TFT degrades a video signal holding characteristic. Therefore, it is necessary to reduce this off current. It is also important to improve the reliability of the TFT. For this purpose, a lightly doped drain (Lightly Dope) cultivated as an LSI technology has been developed.
d Drain (hereinafter abbreviated as LDD) structure is also applied to a TFT. An example is Extensible Affairs Off Support, 1991 International Conference on Solid State State Devices, Inc.
Ant Materials (1991) pp. 641-643 (Extended Ab
stracts of the1991 International Conference on Sol
id State Devices and Materials (1991) P641-643).
【０００３】以下に、（図４）に示したＬＤＤ構造のコ
プレナ型ＴＦＴの製造方法について説明する。絶縁性基
板である透光性ガラス基板１上に活性半導体層２を形成
する。その上に、ゲート絶縁層５およびゲート電極６を
形成する。次に、ゲート電極６をマスクとしてイオン注
入法により低不純物濃度の半導体層３を形成する。さら
に、（図５）に示すように、フォトレジスト１１でマス
クを形成してイオン注入法により不純物を高濃度に添加
することによって、低不純物濃度の半導体層３の外側に
高不純物濃度の半導体層４を形成する。そして、フォト
レジスト１１を除去した後、層間絶縁層８，コンタクト
ホール，ソース電極９，ドレイン電極１０を形成してＴ
ＦＴが完成する。このようにして、ドレイン領域が低不
純物濃度の半導体層３と高不純物濃度の半導体層４とか
らなるＬＤＤ構造を形成する。A method of manufacturing a coplanar TFT having the LDD structure shown in FIG. 4 will be described below. Insulating group
An active semiconductor layer 2 is formed on a transparent glass substrate 1 which is a plate . A gate insulating layer 5 and a gate electrode 6 are formed thereon. Next, the semiconductor layer 3 having a low impurity concentration is formed by ion implantation using the gate electrode 6 as a mask. Further, as shown in FIG. 5, by forming a mask with the photoresist 11 and adding an impurity at a high concentration by ion implantation, a high impurity is formed outside the semiconductor layer 3 having a low impurity concentration. A semiconductor layer 4 having a concentration is formed. Then, after removing the photoresist 11, an interlayer insulating layer 8, a contact hole, a source electrode 9, and a drain electrode 10 are formed.
FT is completed. In this manner, the drain region is formed an LDD structure comprising a semiconductor layer 3 of a low impurity concentration higher impurity concentration of the semiconductor layer 4.
【０００４】[0004]
【発明が解決しようとする課題】不純物添加時のマスク
としてのフォトレジスト１１の形成位置を、（図５
（ａ））と（図５（ｂ））に比較して示している。設計
状態と実工程におけるこのような差異は、フォトリソグ
ラフィーのマスク合わせ精度の範囲で生じることは避け
られない。そのために、低不純物濃度の半導体層３（図
５のＬｌｄｄ）を精度よく微細に形成することは難し
い。また、ガラス基板１上に多くのＴＦＴを作製する場
合などには、基板の熱収縮などの影響を受けるために、
一基板内でのフォトレジストの形成位置の均一性を得る
ことも容易ではなく、低不純物濃度の半導体層３（図５
のＬｌｄｄ）を一基板内で均一に形成することは難し
い。また、ゲート電極６をマスクとして低不純物濃度の
半導体層３を形成した時点で、ゲート電極６とドレイン
領域とのソース・ドレイン方向に対する重なり（図５の
Ｌｇｄ）が決定するために、このＬｇｄを容易に変化さ
せることはできない。The formation position of the photoresist 11 as a mask at the time of impurity addition is shown in FIG.
(A) ) and (FIG. 5 (b) ). It is inevitable that such a difference between the design state and the actual process occurs within the range of mask alignment accuracy of photolithography. Therefore, it is difficult to form the semiconductor layer 3 (Lldd in FIG. 5) having a low impurity concentration with high precision and fineness. Further, when many TFTs are formed on the glass substrate 1 , the TFT is affected by heat shrinkage of the substrate and the like.
It is not easy to obtain uniformity of the photoresist formation position within one substrate, and the semiconductor layer 3 having a low impurity concentration (FIG. 5)
It is difficult to form Lldd) uniformly in one substrate. When the low impurity concentration semiconductor layer 3 is formed using the gate electrode 6 as a mask, the overlap between the gate electrode 6 and the drain region in the source / drain direction (Lgd in FIG. 5) is determined. It cannot be changed easily.
【０００５】本発明においては、半導体層に不純物を添
加する際のマスクを精度よく、しかも基板内での均一性
を損なわずに形成すると同時に、ゲート電極とドレイン
領域とのソース・ドレイン方向に対する重なり（図５の
Ｌｇｄに相当する）を制御してＬＤＤ構造のＴＦＴを作
製することを目的としている。In the present invention, a mask for adding an impurity to a semiconductor layer is formed with high accuracy and without impairing uniformity in a substrate, and at the same time, an overlap of a gate electrode and a drain region in a source / drain direction. (Corresponding to Lgd in FIG. 5) to manufacture a TFT having an LDD structure.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
に本発明は、ゲート電極をマスクとして低不純物濃度の
半導体層を形成した後、前記ゲート電極の一部を改質層
とする。次に、前記ゲート電極および前記改質層をマス
クとして高不純物濃度の半導体層を形成する。そしてそ
の際、ゲート電極の端部の形状をテーパー状としておく
ものである。 [MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
According to the present invention, after a semiconductor layer having a low impurity concentration is formed using a gate electrode as a mask, a part of the gate electrode is used as a modified layer. Next, a semiconductor layer having a high impurity concentration is formed using the gate electrode and the modified layer as a mask. And that
In this case, the shape of the end of the gate electrode is tapered.
Things.
【０００７】[0007]
【作用】以下に、本発明による作用について説明する。
まず、最大の要所であるゲート電極の一部（表面と考え
ると理解し易い）を改質層とする工程について説明す
る。ゲート電極の表面側から他元素を取り込むことや原
子の結合状態を変えること等により改質層を形成するこ
とによって、改質層形成前のゲート電極よりも改質層形
成後のゲート電極および改質層の体積を膨張させる。つ
まり、改質層の形成によって、低不純物濃度の半導体層
を形成する際のマスク（ゲート電極）面積よりも高不純
物濃度の半導体層を形成する際のマスク（ゲート電極お
よび改質層）面積は拡大する。この改質層は精度よく微
細にしかも基板内で均一に形成できるために、不純物を
添加する際のマスクも精度よく微細に形成することがで
きると同時に、一枚の基板上の異なる位置においても均
一に形成することができる。さらに、改質層を絶縁性物
質とすることにより、ゲート電極自身は小さくなるため
に、ゲート電極とドレイン領域とのソース・ドレイン方
向に対する重なりを小さくすることができる。その上、
端部がテーパー状のゲート電極を用いた場合には、ゲー
ト電極もしくはゲート電極および改質層の厚みが小さい
部分では、それらが完全なマスクとして働かないことか
ら、ゲート電極とドレイン領域とのソース・ドレイン方
向に対する重なりを大きくすることもできる。The operation of the present invention will be described below.
First, a process of forming a part of the gate electrode (which is easy to understand when considered as a surface), which is the most important point, as a modified layer will be described. By forming the modified layer by taking in other elements from the surface side of the gate electrode or changing the bonding state of atoms, the gate electrode after the formation of the modified layer and the gate electrode after the formation of the modified electrode are formed more than the gate electrode before the formation of the modified layer. The volume of the porous layer is expanded. In other words, by forming the modified layer, the area of the mask (gate electrode and modified layer) when forming the semiconductor layer with a higher impurity concentration is larger than the area of the mask (gate electrode) when forming the semiconductor layer with a lower impurity concentration. Expanding. Since this modified layer can be formed precisely and finely and uniformly within the substrate, the mask for adding the impurity can be formed precisely and finely, and at the same time, even at different positions on one substrate. It can be formed uniformly. Further, by using an insulating material for the modified layer, the size of the gate electrode itself is reduced, so that the overlap between the gate electrode and the drain region in the source / drain direction can be reduced. Moreover,
When a gate electrode having a tapered end is used, the gate electrode or the gate electrode and the modified layer do not function as a complete mask at a small thickness, so that the source electrode between the gate electrode and the drain region is not formed. -The overlap in the drain direction can be increased.
【０００８】[0008]
【実施例】以下、本発明の実施例について説明する。そ
の前に、本発明に先行して開発した先行開発例について
説明する。 Embodiments of the present invention will be described below. So
Before, about the example of the prior development developed prior to the present invention
explain.
【０００９】（先行開発例） （図１）は本発明より先に開発したコプレナ型ＴＦＴの
作製工程図であり、（図２）は同コプレナ型ＴＦＴの断
面図である。以下に、これらの図を用いて説明する。ま
ず、絶縁性基板としての透光性ガラス基板１上に活性半
導体層２として例えばプラズマＣＶＤ法により非晶質シ
リコンを成膜し、フォトリソグラフィーおよびエッチン
グを用いて島状に加工する。その上に、ゲート絶縁層５
として例えば常圧ＣＶＤ法により二酸化シリコンを形成
する。さらに、ゲート電極６として例えばアルミニウム
を成膜し、フォトリソグラフィーおよびエッチングを用
いて加工する。そして、ゲート電極６をマスクとして、
例えばイオン注入法により燐を不純物として導入して低
不純物濃度の半導体層３を形成する。次に、例えば陽極
酸化法によってゲート電極６の表面に絶縁性物質である
陽極酸化層７例えば酸化アルミニウムを形成する。そし
て、ゲート電極６および陽極酸化層７をマスクとして、
例えばイオン注入法により燐を不純物として導入して高
不純物濃度の半導体層４を形成する。その上に、層間絶
縁層８として例えば常圧ＣＶＤ法により二酸化シリコン
を形成した後、フォトリソグラフィーおよびエッチング
によってコンタクトホールを形成する。さらに、ソース
電極９およびドレイン電極１０を例えばチタン，アルミ
ニウムの順で成膜，加工してＴＦＴが完成する。[0009] (Advanced Development Example) (Figure 1) is coplanar type TFT was developed before the present invention
It is a manufacturing process figure , (FIG. 2) is sectional drawing of the same coplanar TFT. Hereinafter, description will be made with reference to these drawings. First, amorphous silicon is formed as an active semiconductor layer 2 on a translucent glass substrate 1 as an insulating substrate by, for example, a plasma CVD method, and is processed into an island shape using photolithography and etching. On top of that, the gate insulating layer 5
For example, silicon dioxide is formed by a normal pressure CVD method. Further, for example, an aluminum film is formed as the gate electrode 6 and processed using photolithography and etching. Then, using the gate electrode 6 as a mask,
For example, phosphorus is introduced as an impurity by an ion implantation method to form the semiconductor layer 3 having a low impurity concentration. Next, an anodic oxide layer 7 made of an insulating material, for example, aluminum oxide is formed on the surface of the gate electrode 6 by, for example, an anodizing method. Then, using the gate electrode 6 and the anodic oxide layer 7 as a mask,
For example, phosphorus is introduced as an impurity by an ion implantation method to form the semiconductor layer 4 having a high impurity concentration. After that, silicon dioxide is formed as the interlayer insulating layer 8 by, for example, normal pressure CVD, and then a contact hole is formed by photolithography and etching. Further, the source electrode 9 and the drain electrode 10 are formed and processed in the order of, for example, titanium and aluminum to complete the TFT.
【００１０】この先行開発例により作製したＬＤＤ構造
のコプレナ型ＴＦＴには、次の２つの効果がある。一つ
は、低不純物濃度の半導体層３を精度よく微細に形成す
ることができることである。もう一つは、ゲート電極６
と低不純物濃度の半導体層３とのソース・ドレイン方向
に対する重なりを制御できることであり、陽極酸化層７
の厚みによって前記重なりの度合を変化させることがで
きる。このように作製したＴＦＴでは、オフ電流の低減
および信頼性の向上が実現できる。The coplanar TFT having the LDD structure manufactured according to this prior development example has the following two effects. One is that the semiconductor layer 3 having a low impurity concentration can be finely formed with high precision. The other is the gate electrode 6
And the semiconductor layer 3 having a low impurity concentration can be controlled in the source / drain direction.
The degree of the overlap can be changed by the thickness of the sheet. In the TFT manufactured as described above, reduction in off current and improvement in reliability can be realized.
【００１１】次に、上記先行開発例を基礎として開発し
た本発明の実施例につて説明する。 （第１の実施例）本実施例 におけるＴＦＴの作製方法は、上記先行開発例
と次の点についてのみ異なる。以下に、（図３）の本発
明により作製したテーパー状のゲート電極を有するコプ
レナ型ＴＦＴの断面図を用いて説明する。ゲート絶縁層
５として例えば常圧ＣＶＤ法により二酸化シリコンを形
成した上に、ゲート電極６として例えばアルミニウムを
成膜し、フォトリソグラフィーおよびテーパーエッチン
グを用いて加工する。テーパーエッチングを用いること
によって、（図３）のようにゲート電極６の端部を勾配
をもったテーパー状に形成する。この工程以降は、上記
先行開発例と同様である。 Next, based on the preceding development example,
An embodiment of the present invention will be described. ( First Embodiment) The method of manufacturing a TFT in this embodiment is different from the above-mentioned prior development example only in the following points. Hereinafter, a cross-sectional view of a coplanar TFT having a tapered gate electrode manufactured according to the present invention (FIG. 3) will be described. For example, after silicon dioxide is formed as the gate insulating layer 5 by a normal pressure CVD method, for example, aluminum is formed as the gate electrode 6 and processed using photolithography and taper etching. By using taper etching, the end of the gate electrode 6 is formed in a tapered shape having a gradient as shown in FIG. After this process, the above-mentioned
It is the same as the preceding development example .
【００１２】この第１の実施例により作製したＬＤＤ構
造のコプレナ型ＴＦＴには、次の２つの効果がある。一
つは、低不純物濃度の半導体層３を精度よく微細に形成
することができることである。もう一つは、ゲート電極
６のテーパーの角度および陽極酸化層７の厚みを変化さ
せることによって、ゲート電極６と低不純物濃度の半導
体層３とのソース・ドレイン方向に対する重なりおよび
低不純物濃度の半導体層３の領域の大きさをそれぞれ制
御できることである。これは、ゲート電極６のテーパー
状の膜厚が薄い部分は不純物添加時に完全なマスクとし
て働かず、その下の半導体層にも不純物が添加されるこ
とを利用しているのである。The coplanar TFT having the LDD structure manufactured according to the first embodiment has the following two effects. One is that the semiconductor layer 3 having a low impurity concentration can be finely formed with high precision. The other is to change the taper angle of the gate electrode 6 and the thickness of the anodic oxide layer 7 so that the gate electrode 6 and the low impurity concentration semiconductor layer 3 overlap in the source / drain direction and the low impurity concentration semiconductor layer. That is, the size of the region of the layer 3 can be controlled. This is based on the fact that the tapered portion of the gate electrode 6 where the film thickness is small does not function as a complete mask when the impurity is added, and the impurity is also added to the underlying semiconductor layer.
【００１３】（第２の実施例） 上記第１の実施例と同様に、ゲート電極６の端部の形状
をテーパー状として、先行開発例のＴＦＴ作製工程にお
いて、絶縁層５上に所定の形状のゲート電極６を形成す
る工程からゲート電極６の一部を改質層とする工程まで
を、絶縁層５上に導電層を形成する工程、前記導電層上
に所定の形状のフォトレジストを形成する工程、前記フ
ォトレジストを用いて前記導電層を所定の形状に加工し
てゲート電極６を形成する工程、前記ゲート電極６およ
び前記ゲート電極６上のフォトレジストをマスクとして
半導体薄膜２の一部の領域に不純物を添加する工程、前
記フォトレジストを除去する工程、前記ゲート電極６の
一部を改質層とする工程の順にすることもできる。この
ようにフォトレジストをマスクとして利用することによ
りチャンネルへの不純物阻止能力をより一層高めること
ができる。 [0013] Similar to the Second Embodiment The above first embodiment, the shape of the end portion of the gate electrode 6 as a tapered, in the TFT manufacturing process of advanced development example, the predetermined on the insulating layer 5 form forming a step of forming a gate electrode 6 up to the step of the part of the gate electrode 6 and the modified layer, forming a conductive layer over the insulating layer 5, a photoresist having a predetermined shape on the conductive layer of the Forming a gate electrode 6 by processing the conductive layer into a predetermined shape using the photoresist; and forming a part of the semiconductor thin film 2 using the gate electrode 6 and the photoresist on the gate electrode 6 as a mask. The step of adding an impurity to the region, the step of removing the photoresist, and the step of forming a part of the gate electrode 6 as a modified layer. By using the photoresist as a mask in this way, the ability to block impurities in the channel can be further enhanced .
【００１４】なお、本実施例では、先行開発例に準じて
ゲート電極６としてアルミニウムを用いたが、これは陽
極酸化が可能であり、また端部の形状をテーパー状に形
成することが可能で、不純物導入時のマスクとなる導電
層なら何でもよく、例えばアルミニウムを主成分とする
金属やタンタルを主成分とする金属などでもよい。In this embodiment, aluminum is used as the gate electrode 6 according to the prior development example, but this can be anodized and the end portion is formed in a tapered shape. Any conductive layer serving as a mask for introducing impurities can be used. For example, a metal containing aluminum as a main component or a metal containing tantalum as a main component may be used.
【００１５】なお、本実施例では、先行開発例に準じて
ゲート電極６の一部を改質層とする方法として陽極酸化
法を用いたが、これは熱酸化法やプラズマ酸化法やプラ
ズマ窒化法など改質層として絶縁性物質を形成し、改質
層形成前のゲート電極よりも改質層形成後のゲート電極
および改質層の体積を膨張させる方法ならば何でもよ
い。In this embodiment , the anodic oxidation method is used as a method for forming a part of the gate electrode 6 as a modified layer in accordance with the preceding development example. Any method may be used as long as an insulating material is formed as a modified layer, such as a method or a plasma nitridation method, and the volumes of the gate electrode and the modified layer after the modified layer are formed are expanded more than the gate electrode before the modified layer is formed.
【００１６】なお、本実施例では、先行開発例に準じて
不純物として燐を用いたが、これはｎチャネルのＴＦＴ
を作製する場合にはひ素などドナーとして働くものなら
何でもよく、ｐチャネルのＴＦＴを作製する場合にはほ
う素などアクセプターとして働くものならば何でもよ
い。In this embodiment , phosphorus is used as an impurity according to the prior development example.
If you work as a donor such as arsenic
Any material may be used, and in the case of manufacturing a p-channel TFT, any material that works as an acceptor, such as boron, may be used.
【００１７】なお、本実施例では、先行開発例に準じて
絶縁層５および層間絶縁層８として常圧ＣＶＤ法により
作製した二酸化シリコンを用いたが、これはプラズマＣ
ＶＤ法により作製した窒化シリコンなど絶縁層として働
くものならば何でもよい。In this embodiment, silicon dioxide produced by the normal pressure CVD method is used as the insulating layer 5 and the interlayer insulating layer 8 according to the preceding development example.
Any material that functions as an insulating layer, such as silicon nitride manufactured by the VD method, may be used.
【００１８】なお、本実施例では、先行開発例に準じて
活性半導体層２として非晶質シリコンを用いたが、これ
は多結晶シリコン，単結晶シリコン，化合物半導体など
活性半導体として働くものならば何でもよい。In this embodiment, amorphous silicon is used as the active semiconductor layer 2 in accordance with the preceding development example, but this is used as an active semiconductor such as polycrystalline silicon, single crystal silicon, or a compound semiconductor. Anything that works.
【００１９】なお、本実施例では、先行開発例に準じて
不純物を添加する方法としてイオン注入法を用いたが、
高周波放電により添加すべき不純物を少なくとも含むイ
オンを生成して質量分離せずに加速して不純物イオンを
添加する方法など不純物を添加できる方法ならば何でも
よい。In this embodiment, an ion implantation method is used as a method for adding impurities according to the prior development example .
Any method can be used as long as it can add impurities, such as a method of generating ions containing at least impurities to be added by high-frequency discharge and accelerating without mass separation to add impurity ions.
【００２０】[0020]
【発明の効果】以上説明したように本発明によれば、半
導体層に不純物を添加する際のマスクを精度よく微細
に、しかも絶縁性基板内での均一性を損なわずに形成す
ると同時に、ゲート電極とドレイン領域とのソース・ド
レイン方向に対する重なりを制御してＬＤＤ構造のＴＦ
Ｔを作製することができる。As described above, according to the present invention, a mask for adding an impurity to a semiconductor layer is formed precisely and finely without impairing uniformity in an insulating substrate, and at the same time, a gate is formed. By controlling the overlap between the electrode and the drain region in the source / drain direction, the TF having the LDD structure is formed.
T can be made.
【図１】本発明に先行して開発した先行開発例としての
コプレナ型薄膜トランジスタの作製工程図 FIG. 1 is a manufacturing process diagram of a coplanar thin film transistor as a development example developed prior to the present invention .
【図２】同コプレナ型薄膜トランジスタの断面図2 is a cross-sectional view of the coplanar type thin film transistor
【図３】本発明により作製した端部がテーパー状のゲー
ト電極を有するコプレナ型薄膜トランジスタの断面図FIG. 3 is a cross-sectional view of a coplanar thin film transistor having a tapered gate electrode manufactured according to the present invention.
【図４】ＬＤＤ構造のコプレナ型薄膜トランジスタの断
面図FIG. 4 is a cross-sectional view of a coplanar thin film transistor having an LDD structure.
【図５】ＬＤＤ構造のコプレナ型薄膜トランジスタの作
製工程において、フォトレジストをマスクとして高不純
物濃度の半導体層を形成した後の断面図FIG. 5 is a cross-sectional view after a semiconductor layer with a high impurity concentration is formed using a photoresist as a mask in a manufacturing process of a coplanar thin film transistor having an LDD structure.
１ 透光性ガラス基板（絶縁性基板） ２ 活性半導体層 ３ 低不純物濃度の半導体層 ４ 高不純物濃度の半導体層 ５ ゲート絶縁層 ６ ゲート電極 ７ 陽極酸化層 ８ 層間絶縁層 ９ ソース電極 １０ ドレイン電極 １１ フォトレジストDESCRIPTION OF SYMBOLS 1 Translucent glass substrate (insulating substrate) 2 Active semiconductor layer 3 Low impurity concentration semiconductor layer 4 High impurity concentration semiconductor layer 5 Gate insulating layer 6 Gate electrode 7 Anodized layer 8 Interlayer insulating layer 9 Source electrode 10 Drain electrode 11 Photoresist
フロントページの続き (72)発明者 川村 哲也 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (72)発明者 宮田 豊 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (56)参考文献 特開 平５−114724（ＪＰ，Ａ) 特開 平１−173647（ＪＰ，Ａ) 特開 昭62−214669（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/786 H01L 21/336 Continued on the front page (72) Inventor Tetsuya Kawamura 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. References JP-A-5-114724 (JP, A) JP-A-1-173647 (JP, A) JP-A-62-214669 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB Name) H01L 29/786 H01L 21/336
Claims (2)
と、前記半導体薄膜上に絶縁層を形成する工程と、前記
絶縁層上に所定の形状のゲート電極を形成する工程と、
前記ゲート電極をマスクとして前記半導体薄膜の一部の
領域に不純物を添加する工程と、前記ゲート電極の一部
を改質層とする工程と、前記ゲート電極および前記改質
層をマスクとして前記半導体薄膜の一部の領域に２度目
の不純物を添加する工程と、前記２度目の不純物を添加
した半導体薄膜にソース電極およびドレイン電極を形成
する工程とを有する薄膜トランジスタの製造方法であっ
て、前記ゲート電極の端部の形状をその形成時にテーパ
ー状としておくことを特徴とする薄膜トランジスタの製
造方法。A step of forming a semiconductor thin film on an insulating substrate; a step of forming an insulating layer on the semiconductor thin film; and a step of forming a gate electrode having a predetermined shape on the insulating layer.
Adding an impurity to a part of the semiconductor thin film using the gate electrode as a mask, forming a part of the gate electrode as a modified layer, and using the gate electrode and the modified layer as a mask to form the semiconductor. A method for manufacturing a thin film transistor, comprising: a step of adding a second impurity to a partial region of a thin film; and a step of forming a source electrode and a drain electrode in the semiconductor thin film to which the second impurity is added, wherein A method of manufacturing a thin film transistor, wherein an end of an electrode is tapered at the time of forming the electrode.
と、前記半導体薄膜上に絶縁層を形成する工程と、前記
絶縁層上に導電層を形成する工程と、前記導電層上に所
定の形状のフォトレジストを形成する工程と、前記フォ
トレジストを用いて前記導電層を所定の形状に加工して
ゲート電極を形成する工程と、前記ゲート電極および前
記ゲート電極上のフォトレジストをマスクとして前記半
導体薄膜の一部の領域に不純物を添加する工程と、前記
フォトレジストを除去する工程と、前記ゲート電極の一
部を改質層とする工程と、前記ゲート電極および前記改
質層をマスクとして前記半導体薄膜の一部の領域に２度
目の不純物を添加する工程と、前記２度目の不純物を添
加した半導体薄膜にソース電極およびドレイン電極を形
成する工程とを有する薄膜トランジスタの製造方法であ
って、前記ゲート電極の端部の形状をその形成時にテー
パー状としておくことを特徴とする薄膜トランジスタの
製造方法。A step of forming a semiconductor thin film on the insulating substrate; a step of forming an insulating layer on the semiconductor thin film; a step of forming a conductive layer on the insulating layer; Forming a photoresist of a shape, forming the gate electrode by processing the conductive layer into a predetermined shape using the photoresist, and using the photoresist on the gate electrode and the gate electrode as a mask. Adding an impurity to a partial region of the semiconductor thin film, removing the photoresist, forming a part of the gate electrode as a modified layer, and masking the gate electrode and the modified layer. Yes adding an second time impurities in a partial region of the semiconductor thin film, and forming a source electrode and a drain electrode on the semiconductor thin film obtained by adding the second time impurities as Manufacturing method der of that thin film transistor
Therefore, the shape of the end portion of the gate electrode is tapered during its formation.
A method for manufacturing a thin film transistor, wherein the thin film transistor is formed in a par shape .
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24907592A JP3214091B2 (en) | 1992-09-18 | 1992-09-18 | Method for manufacturing thin film transistor |
| EP19930115113 EP0588370A3 (en) | 1992-09-18 | 1993-09-20 | Manufacturing method of thin film transistor and semiconductor device utilized for liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24907592A JP3214091B2 (en) | 1992-09-18 | 1992-09-18 | Method for manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06104279A JPH06104279A (en) | 1994-04-15 |
| JP3214091B2 true JP3214091B2 (en) | 2001-10-02 |
Family
ID=17187636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24907592A Expired - Fee Related JP3214091B2 (en) | 1992-09-18 | 1992-09-18 | Method for manufacturing thin film transistor |
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| Country | Link |
|---|---|
| JP (1) | JP3214091B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102192132B1 (en) * | 2018-02-09 | 2020-12-18 | 주식회사 블러썸엠앤씨 | A three-dimensional puff with a film attached to some surface and a method for manufacturing the same |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3762002B2 (en) | 1996-11-29 | 2006-03-29 | 株式会社東芝 | Thin film transistor and liquid crystal display device |
| GB2396743B (en) * | 1999-03-10 | 2004-08-18 | Matsushita Electric Ind Co Ltd | Thin film transistor |
| JP5977804B2 (en) * | 2014-11-18 | 2016-08-24 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
-
1992
- 1992-09-18 JP JP24907592A patent/JP3214091B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102192132B1 (en) * | 2018-02-09 | 2020-12-18 | 주식회사 블러썸엠앤씨 | A three-dimensional puff with a film attached to some surface and a method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06104279A (en) | 1994-04-15 |
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