JPH06104279A - Manufacture of this film transistor - Google Patents
Manufacture of this film transistorInfo
- Publication number
- JPH06104279A JPH06104279A JP24907592A JP24907592A JPH06104279A JP H06104279 A JPH06104279 A JP H06104279A JP 24907592 A JP24907592 A JP 24907592A JP 24907592 A JP24907592 A JP 24907592A JP H06104279 A JPH06104279 A JP H06104279A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- thin film
- forming
- layer
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 51
- 239000004065 semiconductor Substances 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000010409 thin film Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 239000011810 insulating material Substances 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 238000007743 anodising Methods 0.000 claims 1
- 239000012212 insulator Substances 0.000 claims 1
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 7
- 239000011521 glass Substances 0.000 abstract description 5
- 230000003647 oxidation Effects 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 63
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000002407 reforming Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000010407 anodic oxide Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 210000000434 stratum corneum Anatomy 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、液晶表示装置やイメー
ジセンサ等に応用される薄膜トランジスタの製造方法に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor applied to a liquid crystal display device, an image sensor or the like.
【０００２】[0002]
【従来の技術】薄膜トランジスタ（Ｔｈｉｎ Ｆｉｌｍ
Ｔｒａｎｓｉｓｔｏｒ：以下では、ＴＦＴと略記す
る）を例えば液晶表示装置の画素のスイッチング素子と
して用いる場合、ＴＦＴの逆バイアス時のリーク電流
（以下では、オフ電流と記す）は映像信号の保持特性を
悪化させることから、このオフ電流を低減する必要があ
る。また、ＴＦＴの信頼性を向上させることも重要であ
り、そのためにＬＳＩ技術として培われてきたライトリ
ィー・ドープト・ドレイン（Ｌｉｇｈｔｌｙ Ｄｏｐｅ
ｄ Ｄｒａｉｎ，以下ＬＤＤと略す）構造がＴＦＴにも
応用されている。その例が、イクステンテ゛ィット・アフ゛ストラクツ・オフ゛・
サ゛・1991・インターナショナル・コンファレンス・オン・ソリット゛・ステート・テ゛ハ゛イセス゛・ア
ント゛・マテリアルス゛(1991年)第641頁から第643頁(Extended Abs
tracts of the1991 International Conference on Soli
d State Devices and Materials(1991)P641-643)に記載
されている。BACKGROUND OF THE INVENTION thin film transistor (T hin F ilm
T ransistor: In the following, when used as switching elements of pixels of the abbreviated as TFT) for example, a liquid crystal display device, when a reverse bias TFT in the leak current (hereinafter is referred to as off current) is deteriorated retention properties of the video signal Therefore, it is necessary to reduce this off current. Also, it is important to improve the reliability of the TFT, the write Ryi-doped has been cultivated as LSI technology to the drain (L ightly D ope
d D rain, hereinafter referred to as LDD) structure is applicable for the TFT. Examples are extended, abstract, and off.
The 1991 International Conference on Solid State Devices and Materials (1991) 641 to 643 (Extended Abs
tracts of the1991 International Conference on Soli
d State Devices and Materials (1991) P641-643).
【０００３】以下に、（図４）に示したＬＤＤ構造のコ
プレナ型ＴＦＴの製造方法について説明する。透光性ガ
ラス基板１上に活性半導体層２を形成する。その上に、
ゲート絶縁層５およびゲート電極６を形成する。次に、
ゲート電極６をマスクとしてイオン注入法により低不純
物濃度の半導体層を形成する。さらに、（図５）に示す
ように、フォトレジスト１１でマスクを形成してイオン
注入法により不純物を高濃度に添加することによって、
低不純物濃度の半導体層３と高不純物濃度の半導体層４
を形成する。そして、フォトレジスト１１を除去した
後、層間絶縁層８，コンタクトホール，ソース電極９，
ドレイン電極１０を形成してＴＦＴが完成する。このよ
うにして、ドレイン領域が低不純物濃度の半導体層と高
不純物濃度の半導体層とからなるＬＤＤ構造を形成す
る。A method of manufacturing the LDD structure coplanar TFT shown in FIG. 4 will be described below. The active semiconductor layer 2 is formed on the transparent glass substrate 1. in addition,
The gate insulating layer 5 and the gate electrode 6 are formed. next,
A semiconductor layer having a low impurity concentration is formed by an ion implantation method using the gate electrode 6 as a mask. Further, as shown in (FIG. 5), a mask is formed with the photoresist 11 and impurities are added at a high concentration by an ion implantation method.
Low impurity concentration semiconductor layer 3 and high impurity concentration semiconductor layer 4
To form. Then, after removing the photoresist 11, the interlayer insulating layer 8, the contact hole, the source electrode 9,
The drain electrode 10 is formed to complete the TFT. Thus, the LDD structure in which the drain region is composed of the semiconductor layer having a low impurity concentration and the semiconductor layer having a high impurity concentration is formed.
【０００４】[0004]
【発明が解決しようとする課題】不純物添加時のマスク
としてのフォトレジストの形成位置を、（図５ａ）と
（図５ｂ）に比較して示している。設計状態と実工程に
おけるこのような差異は、フォトリソグラフィーのマス
ク合わせ精度の範囲で生じることは避けられない。その
ために、低不純物濃度の半導体層（図５のＬｌｄｄ）を
精度よく微細に形成することは難しい。また、ガラス基
板上に多くのＴＦＴを作製する場合などには、基板の熱
収縮などの影響を受けるために、一基板内でのフォトレ
ジストの形成位置の均一性を得ることも容易ではなく、
低不純物濃度の半導体層（図５のＬｌｄｄ）を一基板内
で均一に形成することは難しい。また、ゲート電極をマ
スクとして低不純物濃度の半導体層を形成した時点で、
ゲート電極とドレイン領域とのソース・ドレイン方向に
対する重なり（図５のＬｇｄ）が決定するために、この
Ｌｇｄを容易に変化させることはできない。The formation position of the photoresist as a mask at the time of adding impurities is shown in comparison with (FIG. 5a) and (FIG. 5b). It is unavoidable that such a difference between the design state and the actual process occurs in the range of the mask alignment accuracy of photolithography. Therefore, it is difficult to precisely and finely form the semiconductor layer (Lldd in FIG. 5) having a low impurity concentration. In addition, when many TFTs are manufactured on a glass substrate, it is not easy to obtain the uniformity of the photoresist formation position within one substrate because it is affected by heat shrinkage of the substrate.
It is difficult to uniformly form a low impurity concentration semiconductor layer (Lldd in FIG. 5) in one substrate. Further, when the semiconductor layer having a low impurity concentration is formed using the gate electrode as a mask,
Since the overlap between the gate electrode and the drain region in the source / drain direction (Lgd in FIG. 5) is determined, this Lgd cannot be easily changed.
【０００５】本発明においては、半導体層に不純物を添
加する際のマスクを精度よく、しかも基板内での均一性
を損なわずに形成すると同時に、ゲート電極とドレイン
領域とのソース・ドレイン方向に対する重なり（図５の
Ｌｇｄに相当する）を制御してＬＤＤ構造のＴＦＴを作
製することを目的としている。According to the present invention, a mask for adding impurities to a semiconductor layer is formed with high precision and without impairing the uniformity in the substrate, and at the same time, the gate electrode and the drain region overlap in the source / drain direction. The purpose is to control (corresponding to Lgd in FIG. 5) to manufacture a TFT having an LDD structure.
【０００６】[0006]
【課題を解決するための手段】ゲート電極をマスクとし
て低不純物濃度の半導体層を形成した後、前記ゲート電
極の一部を改質層とする。次に、前記ゲート電極および
前記改質層をマスクとして高不純物濃度の半導体層を形
成する。A low impurity concentration semiconductor layer is formed using a gate electrode as a mask, and then a part of the gate electrode is used as a modified layer. Next, a semiconductor layer having a high impurity concentration is formed using the gate electrode and the modified layer as a mask.
【０００７】[0007]
【作用】以下に、本発明による作用について説明する。
まず、最大の要所であるゲート電極の一部（表面と考え
ると理解し易い）を改質層とする工程について説明す
る。ゲート電極の表面側から他元素を取り込むことや原
子の結合状態を変えること等により改質層を形成するこ
とによって、改質層形成前のゲート電極よりも改質層形
成後のゲート電極および改質層の体積を膨張させる。つ
まり、改質層の形成によって、低不純物濃度の半導体層
を形成する際のマスク（ゲート電極）面積よりも高不純
物濃度の半導体層を形成する際のマスク（ゲート電極お
よび改質層）面積は拡大する。この改質層は精度よく微
細にしかも基板内で均一に形成できるために、不純物を
添加する際のマスクも精度よく微細に形成することがで
きると同時に、一枚の基板上の異なる位置においても均
一に形成することができる。さらに、改質層を絶縁性物
質とすることにより、ゲート電極自身は小さくなるため
に、ゲート電極とドレイン領域とのソース・ドレイン方
向に対する重なりを小さくすることができる。また、テ
ーパー状のゲート電極を用いた場合には、ゲート電極も
しくはゲート電極および改質層の厚みが小さい部分で
は、それらが完全なマスクとして働かないことから、ゲ
ート電極とドレイン領域とのソース・ドレイン方向に対
する重なりを大きくすることもできる。The function of the present invention will be described below.
First, a step of forming a part of the gate electrode (which is easy to understand when considered as a surface) as a modified layer, which is the most important point, will be described. By forming the modified layer by incorporating other elements from the surface side of the gate electrode or changing the bonding state of atoms, the gate electrode after the modified layer is formed and the modified layer is formed more than the gate electrode before the modified layer is formed. Expand the volume of the stratum corneum. That is, the area of the mask (gate electrode and modified layer) used to form the semiconductor layer having a high impurity concentration is smaller than the area of the mask (gate electrode) used to form the semiconductor layer having a low impurity concentration due to the formation of the modified layer. Expanding. Since this modified layer can be formed precisely and finely and uniformly within the substrate, the mask when adding impurities can be formed accurately and finely, and at the same time, even at different positions on one substrate. It can be formed uniformly. Furthermore, since the gate electrode itself is made small by using an insulating material for the modified layer, the overlap between the gate electrode and the drain region in the source / drain direction can be made small. Further, when a tapered gate electrode is used, it does not work as a complete mask in the gate electrode or a portion where the thickness of the gate electrode and the modified layer is small, so that the source electrode of the gate electrode and the drain region is The overlap in the drain direction can be increased.
【０００８】[0008]
【実施例】以下、本発明の実施例について述べる。EXAMPLES Examples of the present invention will be described below.
【０００９】（第１の実施例）（図１）は本発明による
コプレナ型ＴＦＴの作製工程の断面図であり、（図２）
は本発明により作製したコプレナ型ＴＦＴの断面図であ
る。以下に、これらの図を用いて第１の実施例を説明す
る。まず、透光性ガラス基板１上に活性半導体層２とし
て例えばプラズマＣＶＤ法により非晶質シリコンを成膜
し、フォトリソグラフィーおよびエッチングを用いて島
状に加工する。その上に、ゲート絶縁層５として例えば
常圧ＣＶＤ法により二酸化シリコンを形成する。さら
に、ゲート電極６として例えばアルミニウムを成膜し、
フォトリソグラフィーおよびエッチングを用いて加工す
る。そして、ゲート電極６をマスクとして、例えばイオ
ン注入法により燐を不純物として導入して低不純物濃度
の半導体層３を形成する。次に、例えば陽極酸化法によ
ってゲート電極６の表面に絶縁性物質である陽極酸化層
７（酸化アルミニウム）を形成する。そして、ゲート電
極６および陽極酸化層７をマスクとして、例えばイオン
注入法により燐を不純物として導入して高不純物濃度の
半導体層４を形成する。その上に、層間絶縁層８として
例えば常圧ＣＶＤ法により二酸化シリコンを形成した
後、フォトリソグラフィーおよびエッチングによってコ
ンタクトホールを形成する。さらに、ソース電極９およ
びドレイン電極１０を例えばチタン，アルミニウムの順
で成膜，加工してＴＦＴが完成する。(First Embodiment) (FIG. 1) is a cross-sectional view of a manufacturing process of a coplanar TFT according to the present invention (FIG. 2).
FIG. 3 is a cross-sectional view of a coplanar TFT manufactured according to the present invention. The first embodiment will be described below with reference to these drawings. First, an amorphous silicon film is formed as the active semiconductor layer 2 on the translucent glass substrate 1 by, for example, a plasma CVD method, and is processed into an island shape by using photolithography and etching. Silicon dioxide is formed thereon as the gate insulating layer 5 by atmospheric pressure CVD, for example. Further, for example, a film of aluminum is formed as the gate electrode 6,
Process using photolithography and etching. Then, using the gate electrode 6 as a mask, phosphorus is introduced as an impurity by, for example, an ion implantation method to form the semiconductor layer 3 having a low impurity concentration. Next, the anodic oxide layer 7 (aluminum oxide), which is an insulating material, is formed on the surface of the gate electrode 6 by, for example, an anodic oxidation method. Then, using the gate electrode 6 and the anodized layer 7 as a mask, phosphorus is introduced as an impurity by, for example, an ion implantation method to form the semiconductor layer 4 having a high impurity concentration. After that, silicon dioxide is formed as the interlayer insulating layer 8 by, for example, the atmospheric pressure CVD method, and then a contact hole is formed by photolithography and etching. Further, the source electrode 9 and the drain electrode 10 are deposited and processed in the order of, for example, titanium and aluminum to complete the TFT.
【００１０】この第１の実施例により作製したＬＤＤ構
造のコプレナ型ＴＦＴには、次の２つの効果がある。一
つは、低不純物濃度の半導体層３を精度よく微細に形成
することができることである。もう一つは、ゲート電極
６と低不純物濃度の半導体層３とのソース・ドレイン方
向に対する重なりを制御できることであり、陽極酸化層
７の厚みによって前記重なりの度合を変化させることが
できる。この様に作製したＴＦＴでは、オフ電流の低減
および信頼性の向上が実現できる。The LDD-structured coplanar TFT manufactured according to the first embodiment has the following two effects. One is that the semiconductor layer 3 having a low impurity concentration can be precisely and finely formed. The other is that the overlap of the gate electrode 6 and the semiconductor layer 3 having a low impurity concentration in the source / drain direction can be controlled, and the degree of the overlap can be changed depending on the thickness of the anodized layer 7. With the TFT manufactured in this manner, reduction in off current and improvement in reliability can be realized.
【００１１】（第２の実施例）第２の実施例におけるＴ
ＦＴの作製方法は、第１の実施例と次の点についてのみ
異なる。以下に、（図３）の本発明により作製したテー
パー状のゲート電極を有するコプレナ型ＴＦＴの断面図
を用いて説明する。ゲート絶縁層５として例えば常圧Ｃ
ＶＤ法により二酸化シリコンを形成した上に、ゲート電
極６として例えばアルミニウムを成膜し、フォトリソグ
ラフィーおよびテーパーエッチングを用いて加工する。
テーパーエッチングを用いることによって、（図３）の
ようにゲート電極６の端は、勾配をもったテーパー状に
形成する。この工程以降は、第１の実施例と同様であ
る。(Second Embodiment) T in the second embodiment
The manufacturing method of the FT differs from that of the first embodiment only in the following points. Hereinafter, a description will be given using a cross-sectional view of a coplanar TFT having a tapered gate electrode manufactured by the present invention (FIG. 3). As the gate insulating layer 5, for example, normal pressure C
After forming silicon dioxide by the VD method, for example, aluminum is formed as the gate electrode 6 and processed by using photolithography and taper etching.
By using the taper etching, the end of the gate electrode 6 is formed in a tapered shape having a gradient as shown in FIG. After this step, it is the same as in the first embodiment.
【００１２】この第２の実施例により作製したＬＤＤ構
造のコプレナ型ＴＦＴには、次の２つの効果がある。一
つは、低不純物濃度の半導体層３を精度よく微細に形成
することができることである。もう一つは、ゲート電極
６のテーパーの角度および陽極酸化層７の厚みを変化さ
せることによって、ゲート電極６と低不純物濃度の半導
体層３とのソース・ドレイン方向に対する重なりおよび
低不純物濃度の半導体層３の領域の大きさをそれぞれ制
御できることである。これは、ゲート電極６のテーパー
状の膜厚が薄い部分は不純物添加時に完全なマスクとし
て働かず、その下の半導体層にも不純物が添加されるこ
とを利用しているのである。The LDD structure coplanar TFT manufactured according to the second embodiment has the following two effects. One is that the semiconductor layer 3 having a low impurity concentration can be precisely and finely formed. Another is to change the taper angle of the gate electrode 6 and the thickness of the anodic oxide layer 7 so that the gate electrode 6 and the semiconductor layer 3 having a low impurity concentration overlap with each other in the source / drain direction and the semiconductor having a low impurity concentration is formed. It is possible to control the size of each region of the layer 3. This is because the tapered thin portion of the gate electrode 6 does not work as a complete mask when impurities are added, and the impurities are added to the semiconductor layer thereunder.
【００１３】なお、第１の実施例ではゲート電極６とし
てアルミニウムを用いたが、これは陽極酸化が可能で不
純物導入時のマスクとなる導電層なら何でもよく、例え
ばアルミニウムを主成分とする金属やタンタルを主成分
とする金属などでもよい。Although aluminum is used as the gate electrode 6 in the first embodiment, any conductive layer that can be anodized and serves as a mask at the time of introducing impurities, such as a metal containing aluminum as a main component or A metal containing tantalum as a main component may be used.
【００１４】なお、第２の実施例ではゲート電極６とし
てアルミニウムを用いたが、これはテーパー状に形成が
可能であり、陽極酸化が可能であって、不純物導入時の
マスクとなる導電層なら何でもよく、例えばアルミニウ
ムを主成分とる金属やタンタルを主成分とする金属など
でもよい。Although aluminum is used as the gate electrode 6 in the second embodiment, it can be formed in a tapered shape and can be anodized if it is a conductive layer that serves as a mask at the time of introducing impurities. It may be anything, for example, a metal containing aluminum as a main component or a metal containing tantalum as a main component.
【００１５】なお、第１および第２の実施例ではゲート
電極６の一部を改質層とする方法として陽極酸化法を用
いたが、これは熱酸化法やプラズマ酸化法やプラズマ窒
化法など改質層として絶縁性物質を形成し、改質層形成
前のゲート電極よりも改質層形成後のゲート電極および
改質層の体積を膨張させる方法ならば何でもよい。In the first and second embodiments, the anodic oxidation method is used as a method for forming a part of the gate electrode 6 as a modified layer. However, this is a thermal oxidation method, a plasma oxidation method, a plasma nitriding method, or the like. Any method may be used as long as an insulating material is formed as the reforming layer and the volume of the gate electrode and the reforming layer after the reforming layer are expanded more than that of the gate electrode before the reforming layer is formed.
【００１６】なお、第１および第２の実施例では不純物
として燐を用いたが、これはｎチャネルのＴＦＴを作製
する場合にはひ素などドナーとして働くものならなんで
もよく、ｐチャネルのＴＦＴを作製する場合にはほう素
などアクセプターとして働くものならば何でもよい。Although phosphorus is used as an impurity in the first and second embodiments, any element that acts as a donor such as arsenic may be used when an n-channel TFT is manufactured, and a p-channel TFT is manufactured. If it does, it can be anything that works as an acceptor, such as boron.
【００１７】なお、第１および第２の実施例ではゲート
絶縁層５および層間絶縁層８として常圧ＣＶＤ法により
作製した二酸化シリコンを用いたが、これはプラズマＣ
ＶＤ法により作製した窒化シリコンなど絶縁層として働
くものならば何でもよい。In the first and second embodiments, silicon dioxide produced by the atmospheric pressure CVD method is used as the gate insulating layer 5 and the interlayer insulating layer 8, but this is plasma C
Any material such as silicon nitride manufactured by the VD method that functions as an insulating layer may be used.
【００１８】なお、第１および第２の実施例では活性半
導体層２として非晶質シリコンを用いたが、これは多結
晶シリコン，単結晶シリコン，化合物半導体など活性半
導体として働くものならば何でもよい。Although amorphous silicon is used as the active semiconductor layer 2 in the first and second embodiments, any material such as polycrystalline silicon, single crystal silicon, or compound semiconductor that works as an active semiconductor may be used. .
【００１９】なお、第１および第２の実施例では不純物
を添加する方法としてイオン注入法を用いたが、高周波
放電により添加すべき不純物を少なくとも含むイオンを
生成して質量分離せずに加速して不純物イオンを添加す
る方法など不純物を添加できる方法ならば何でもよい。Although the ion implantation method is used as a method for adding impurities in the first and second embodiments, the ions containing at least the impurities to be added are generated by the high frequency discharge and accelerated without mass separation. Any method can be used as long as impurities can be added, such as a method of adding impurity ions.
【００２０】[0020]
【発明の効果】以上説明したように本発明によれば、半
導体層に不純物を添加する際のマスクを精度よく微細
に、しかも基板内での均一性を損なわずに形成すると同
時に、ゲート電極とドレイン領域とのソース・ドレイン
方向に対する重なりを制御してＬＤＤ構造のＴＦＴを作
製することができる。As described above, according to the present invention, a mask for adding impurities to a semiconductor layer is formed with high precision and fineness, and without impairing the uniformity within the substrate, and at the same time, as a gate electrode. A TFT having an LDD structure can be manufactured by controlling the overlap between the drain region and the source / drain direction.
【図１】本発明によるコプレナ型薄膜トランジスタの作
製工程の断面図FIG. 1 is a sectional view of a manufacturing process of a coplanar thin film transistor according to the present invention.
【図２】本発明により作製したコプレナ型薄膜トランジ
スタの断面図FIG. 2 is a sectional view of a coplanar thin film transistor manufactured by the present invention.
【図３】本発明により作製したテーパー状のゲート電極
を有するコプレナ型薄膜トランジスタの断面図FIG. 3 is a cross-sectional view of a coplanar thin film transistor having a tapered gate electrode manufactured according to the present invention.
【図４】ＬＤＤ構造のコプレナ型薄膜トランジスタの断
面図FIG. 4 is a sectional view of a coplanar thin film transistor having an LDD structure.
【図５】ＬＤＤ構造のコプレナ型薄膜トランジスタ作製
工程において、フォトレジストをマスクとして高不純物
濃度の半導体層を形成した後の断面図FIG. 5 is a cross-sectional view after a semiconductor layer with a high impurity concentration is formed using a photoresist as a mask in a manufacturing process of a coplanar thin film transistor having an LDD structure.
１ 透光性ガラス基板 ２ 活性半導体層 ３ 低不純物濃度の半導体層 ４ 高不純物濃度の半導体層 ５ ゲート絶縁層 ６ ゲート電極 ７ 陽極酸化層 ８ 層間絶縁層 ９ ソース電極 １０ ドレイン電極 １１ フォトレジスト 1 Translucent Glass Substrate 2 Active Semiconductor Layer 3 Low Impurity Concentration Semiconductor Layer 4 High Impurity Concentration Semiconductor Layer 5 Gate Insulating Layer 6 Gate Electrode 7 Anodized Layer 8 Interlayer Insulating Layer 9 Source Electrode 10 Drain Electrode 11 Photoresist
───────────────────────────────────────────────────── フロントページの続き (72)発明者 川村 哲也 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 宮田 豊 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuya Kawamura 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Yutaka Miyata, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.
Claims (8)
記半導体薄膜上に絶縁層を形成する工程と、前記絶縁層
上に所定の形状の電極を形成する工程と、前記電極をマ
スクとして前記半導体薄膜の一部の領域に不純物を添加
する工程と、前記電極の一部を改質層とする工程と、前
記電極および前記改質層をマスクとして前記半導体薄膜
の一部の領域に不純物を添加する工程とを有することを
特徴とする薄膜トランジスタの製造方法。1. A step of forming a semiconductor thin film on a substrate, a step of forming an insulating layer on the semiconductor thin film, a step of forming an electrode having a predetermined shape on the insulating layer, and using the electrode as a mask. A step of adding an impurity to a partial region of the semiconductor thin film; a step of forming a part of the electrode as a modified layer; and an impurity in a partial region of the semiconductor thin film using the electrode and the modified layer as a mask. And a step of adding the above.
記半導体薄膜上に絶縁層を形成する工程と、前記絶縁層
上に導電層を形成する工程と、前記導電層上に所定の形
状のフォトレジストを形成する工程と、前記フォトレジ
ストを用いて前記導電層を所定の形状に加工して電極を
形成する工程と、前記電極および前記電極上の前記フォ
トレジストをマスクとして前記半導体薄膜の一部の領域
に不純物を添加する工程と、前記フォトレジストを除去
する工程と、前記電極の一部を改質層とする工程と、前
記電極および前記改質層をマスクとして前記半導体薄膜
の一部の領域に不純物を添加する工程とを有することを
特徴とする薄膜トランジスタの製造方法。2. A step of forming a semiconductor thin film on a substrate, a step of forming an insulating layer on the semiconductor thin film, a step of forming a conductive layer on the insulating layer, and a predetermined shape on the conductive layer. A step of forming a photoresist, a step of forming the electrode by processing the conductive layer into a predetermined shape using the photoresist, and a step of forming the semiconductor thin film using the electrode and the photoresist on the electrode as a mask. A step of adding impurities to a part of the region; a step of removing the photoresist; a step of forming a part of the electrode as a modified layer; a step of using the electrode and the modified layer as a mask And a step of adding an impurity to the region of the portion.
る請求項１または２記載の薄膜トランジスタの製造方
法。3. The method of manufacturing a thin film transistor according to claim 1, wherein the substrate is a translucent insulator.
質層を絶縁性物質とし、前記改質層を形成する前の前記
電極の体積よりも前記改質層を形成した後の前記電極お
よび前記改質層の体積を増加させることを特徴とする請
求項１〜３記載の薄膜トランジスタの製造方法。4. The step of forming a part of the electrode as a modified layer forms the modified layer more than the volume of the electrode before forming the modified layer by using the modified layer as an insulating material. The method for manufacturing a thin film transistor according to claim 1, wherein the volume of the electrode and the modified layer afterward is increased.
極酸化法を用いることを特徴とする請求項１〜３記載の
薄膜トランジスタの製造方法。5. The method of manufacturing a thin film transistor according to claim 1, wherein an anodizing method is used as a method for forming a part of the electrode as a modified layer.
コン，多結晶シリコン，または単結晶シリコンであるこ
とを特徴とする請求項１〜５記載の薄膜トランジスタの
製造方法。6. The method of manufacturing a thin film transistor according to claim 1, wherein the semiconductor thin film is amorphous silicon, microcrystalline silicon, polycrystalline silicon, or single crystal silicon.
る工程として、添加すべき不純物を少なくとも含む高周
波放電により不純物イオンを生成する工程と、前記不純
物イオンを加速する工程を少なくとも有することを特徴
とする請求項１〜６記載の薄膜トランジスタの製造方
法。7. The step of adding an impurity to a partial region of a semiconductor thin film includes at least a step of generating impurity ions by a high frequency discharge containing at least impurities to be added, and a step of accelerating the impurity ions. 7. The method of manufacturing a thin film transistor according to claim 1, wherein the thin film transistor is manufactured.
特徴とする請求項１〜７記載の薄膜トランジスタの製造
方法。8. The method of manufacturing a thin film transistor according to claim 1, wherein the end portion of the electrode has a tapered shape.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24907592A JP3214091B2 (en) | 1992-09-18 | 1992-09-18 | Method for manufacturing thin film transistor |
| EP19930115113 EP0588370A3 (en) | 1992-09-18 | 1993-09-20 | Manufacturing method of thin film transistor and semiconductor device utilized for liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24907592A JP3214091B2 (en) | 1992-09-18 | 1992-09-18 | Method for manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06104279A true JPH06104279A (en) | 1994-04-15 |
| JP3214091B2 JP3214091B2 (en) | 2001-10-02 |
Family
ID=17187636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24907592A Expired - Fee Related JP3214091B2 (en) | 1992-09-18 | 1992-09-18 | Method for manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3214091B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6096585A (en) * | 1996-11-29 | 2000-08-01 | Kabushiki Kaisha Toshiba | Method of manufacturing thin film transistor |
| GB2393574A (en) * | 1999-03-10 | 2004-03-31 | Matsushita Electric Ind Co Ltd | Top-gate LDD TFT |
| JP2015079972A (en) * | 2014-11-18 | 2015-04-23 | 株式会社半導体エネルギー研究所 | Manufacturing method of semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102192132B1 (en) * | 2018-02-09 | 2020-12-18 | 주식회사 블러썸엠앤씨 | A three-dimensional puff with a film attached to some surface and a method for manufacturing the same |
-
1992
- 1992-09-18 JP JP24907592A patent/JP3214091B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6096585A (en) * | 1996-11-29 | 2000-08-01 | Kabushiki Kaisha Toshiba | Method of manufacturing thin film transistor |
| US6670641B1 (en) | 1996-11-29 | 2003-12-30 | Kabushiki Kaisha Toshiba | Thin film transistor, method of manufacturing the same and thin film transistor liquid crystal display device |
| GB2393574A (en) * | 1999-03-10 | 2004-03-31 | Matsushita Electric Ind Co Ltd | Top-gate LDD TFT |
| GB2393574B (en) * | 1999-03-10 | 2004-06-02 | Matsushita Electric Ind Co Ltd | Method of manufacturing a thin film transistor |
| JP2015079972A (en) * | 2014-11-18 | 2015-04-23 | 株式会社半導体エネルギー研究所 | Manufacturing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3214091B2 (en) | 2001-10-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6720221B1 (en) | Structure and method for dual gate oxide thicknesses | |
| US5512494A (en) | Method for manufacturing a thin film transistor having a forward staggered structure | |
| US20020006705A1 (en) | Semiconductor device and method for manufacturing same | |
| JP4963140B2 (en) | Semiconductor device | |
| JPH06104279A (en) | Manufacture of this film transistor | |
| JPH07273349A (en) | Semiconductor integrated circuit | |
| JPH05182983A (en) | Manufacture of thin-film transistor | |
| JP2841381B2 (en) | Method for manufacturing thin film transistor | |
| JP3391176B2 (en) | Method for manufacturing thin film transistor | |
| JPH06232398A (en) | Manufacture of thin film transistor and manufacture of semiconductor device | |
| KR20050001552A (en) | Tft | |
| JPH01302768A (en) | Inverse stagger type si-thin film transistor | |
| JP2014013948A (en) | Semiconductor device | |
| JP3216173B2 (en) | Method of manufacturing thin film transistor circuit | |
| JPH07115203A (en) | Thin film, manufacture of the thin film and thin-film transistor using the thin film | |
| JP2002319678A (en) | Thin film semiconductor device and manufacturing method therefor | |
| JP3206069B2 (en) | Method for manufacturing thin film transistor | |
| JP5417476B2 (en) | Semiconductor device and electronic equipment | |
| JP5830150B2 (en) | Semiconductor device | |
| US8466053B2 (en) | Method of manufacturing semiconductor device, and semiconductor device | |
| JP2001177104A (en) | Thin film transistor, method of manufacturing the same, and liquid crystal display device equipped therewith | |
| JP2001042354A (en) | Tft type liquid crystal display device and its production | |
| TWI221339B (en) | Thin film transistor with a self-aligned lightly doped structure and its manufacturing method | |
| KR960036145A (en) | Highly Integrated Thin Film Transistors and Manufacturing Method Thereof | |
| JP2010287906A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080727 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090727 Year of fee payment: 8 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090727 Year of fee payment: 8 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100727 Year of fee payment: 9 |
|
| LAPS | Cancellation because of no payment of annual fees |