TWI221339B - Thin film transistor with a self-aligned lightly doped structure and its manufacturing method - Google Patents

Abstract

A kind of thin film transistor with a self-aligned lightly doped structure and its manufacturing method are provided in the present invention. At first, a substrate is provided; and a semiconductor layer is formed on the substrate surface. Then, a gate insulation layer is sequentially formed on the semiconductor layer such that the gate insulation layer covers part of the semiconductor layer surface. Then, a conducting layer is formed on the gate insulation layer and is undergone with an etching process to expose part of the gate insulation layer. An ion implantation process is then conducted onto the semiconductor layer to form the first doped region on the semiconductor layer, which is covered by gate insulation layer, and to form the second doped region on the semiconductor layer that is exposed from the surface.

Description

1221339

FIELD OF THE INVENTION The present invention relates to a silk # ^ ^ _ l + T, ^ a rhenium film transistor structure and a method for manufacturing the same, and particularly to a self-aligned light doping that can be used in preparation. Structured tritium film transistor and manufacturing method thereof. Prior art In the active matrix liquid crystal display (AMLCD), thin filni

tranS1Str (TFT) has been widely used, but thin-film transistors are prone to cause leakage current in the off state, which causes the LCD display to lose its charge. In order to solve this problem, a lightly doped drain (LDD) structure has been developed in the conventional technology to reduce the electric field at the non-polar junction to reduce leakage current. Referring to Figures 1a and 1b, Figures 1a and 1b are schematic diagrams showing a conventional method for manufacturing a thin film transistor having a lightly doped anode structure. Please refer to Figure 1a. First, a transparent insulating substrate 丨 〇1 is provided. The surface of the transparent insulating substrate 101 has a polycrystalline silicon layer 〇〇2, and a gate insulating layer 104. The gate is insulated. The layer 104 covers the polycrystalline silicon layer 102.

In the conventional manufacturing method, a photoresist layer 106 is first defined on the gate insulating layer 104, and then the photoresist layer 106 is used as a mask to perform a heavy ion doping implantation process so that The polycrystalline second layer 102, which is not covered by the photoresist layer 106, forms a heavily doped region 108, which is used as a source / drain region. Next, as shown in Fig. 1b, after removing the photoresist layer 106, a gate layer 1 2 0 is defined on the free insulating layer 104, and the gate layer 1 2 0 only covers

0773-9592twF (nl); P91264; Clarue.ptd "6 pages _ ---- 1221339 V. Description of the invention (2) __ f polycrystalline dream layer 102-part of the undoped region, structure: pattern. Then, the closed electrode layer 120 is used to form a lightly doped region to form a lightly doped region in the uncovered area that is not covered by the closed electrode layer 120. The mixed layer is coated on the gate electrode layer 1 20. "Xi Yue", light center hybrid drain structure, to the Tao. The area of 102a covered with polycrystalline stone layer is used as a general purpose to define the position of the lightly doped drain structure. The method of making a photoresist layer pattern using a photomask is required, and it is limited by the exposure technology. Not only the complicated steps of the drain structure, but also the difference in drift of the drain structure, and lightly doped. Will seriously affect the electrical properties of thin-film transistors = structural bias. SUMMARY OF THE INVENTION In view of this, the purpose of the present invention is to make thin-film transistors made of light-doped thin films] and as long as the mask can be made According to the above purpose, the first method of "transistor manufacturing method" includes a semiconductor layer formed on the surface of the light-duty J2 substrate. In this step: Provide-based into a gate insulation layer, the gate insulation layer covers Fengkun ^ V body layer in order to form an insulation layer Cover the semiconductor layer C; C; · Part of the gate insulation for the rest of the time; step: = = covered by the interlayer insulation layer; = line; sub-implantation step :: _-doped region, the exposed first Page 7 〇773-9592twF (nl); P9i264; Clarue.ptd 1221339 5. Description of the invention (3) The semiconductor layer on the surface forms a second doped region. According to the above purpose, the manufacturing method of the thin film transistor of the present invention is: sequentially formed on the self-aligned-slowly provided two-layer electrode insulation layer: placed on: using; using patterned photoresist as the engraving " For the subsequent formation of interlayers: the edge layer to the exposed semiconductor layer; and (the conductive layer is etched and 2 etched steps to expose a part of the conductive layer. The body-to-patterned photoresist ^ line #etching step 'to expose part of the open pole insect Engraving gas is used to conduct electricity and ion implantation steps are performed on the semiconductor layer to remove the patterned light half body layer formation-the second doped region is formed by the interlayer insulator layer to form a first doped region. The surface semiconductor of the present invention is another-B 丄 film transistor. According to the above purpose, a thin film with a structure of w 'structure provides a self-advancement ± Α Fu I: The pancreas and the Japanese body include: one by one, the semiconductor layers are layered on the lightly doped silicon, and the semiconductor doped layer is formed on the peripheral region of the ridge region; Extremely 浐 ^ 4 doped channels formed in the first doped drain region And the first dopant are formed on the surface of the semiconductor layer and cover the gate insulating layer. The product 'and a free electrode' are formed in the corresponding channel region in order to make the present invention easier to understand. The first and other purposes, features, and advantages can be more clearly described in the Father's Day embodiment, and with the accompanying drawings, details

Embodiments: Please refer to Figs. 2a-2§, and Figs. 2a-2g are schematic diagrams showing a method for manufacturing a thin film transistor having a light impurity structure according to the present invention. Please refer to FIG. 2a. First, a substrate 201 is provided. A buffer layer 2 0 2 ′ is formed on the substrate 201 and a semiconductor layer 203 such as a polycrystalline silicon layer is formed on the buffer layer 202. Among them, the substrate 201 is, for example, a transparent glass layer; the buffer layer 202 is, for example, a silicon oxide layer, and the buffer layer 202 can help the semiconductor layer 203 be formed on the substrate 201. Please refer to FIG. 2b for the semiconductor layer 2. A gate insulation layer, a flavor layer 204, a conductive layer 205, and a patterned photoresist layer 206 are sequentially formed on 3, and the position where the patterned photoresist layer 206 is formed is the position where the gate is subsequently formed. Wherein, the thickness of the gate insulating layer 204 is about 2000 to 10000a, and the material is, for example, an oxide layer (SiO), a nitride layer (SiN), or an oxynitride layer (SiON). The conductive layer 205 is, for example, a metal layer. Please use the patterned photoresist layer 206 as an etch mask in Figure 2c of McCaw, and sequentially perform the etching steps on the conductive layer 205 and the gate insulating layer 204 to Until the semiconductor layer 203 is exposed, a conductive layer 205a and a gate insulating layer 204a are formed. Among them, the method of etching may be plasma etching ( p lasma etching), etc. ^ Next, as shown in FIG. 2d, a mixed gas composed of an oxygen-containing gas and a chlorine (Cl2) gas is used as an etching reaction gas to conduct the remaining steps to form a conductive thin film. =: 20 = The surface of the gate insulation layer 204a of the output part. Among them, the oxygen-containing gas is in the same group 1221339. V. Description of the invention (5) The mixed gas is not limited to chlorine-containing gas, and the chlorine-containing gas may be replaced by other gases. .

= And 'In the present invention, when a mixed gas composed of an oxygen-containing gas and a chlorine (C 12) -containing gas is used as an etching reaction gas to perform the etching step f on the conductive layer 20 5a', the oxygen-containing gas and chlorine can be adjusted in a timely manner as required. Individual flow of gas: In this way, the steps shown in Figure 2c can be omitted, reducing the implementation time of this case. For example, in the step of sequentially etching the conductive layer 205 and the gate insulating layer 20 04 to expose the semiconductor layer 203, the flow rate of the oxygen-containing gas can be adjusted to be extremely small, and the conductive layer 205 is etched to form In the step of the gate, the flow rate of the s-oxygen gas is gradually adjusted to a maximum, that is, only the oxygen-containing gas is used as the etching gas; in this way, the shape of the gate above the gate is more prominent.

Please refer to FIG. 2e. After removing the patterned photoresist layer 206b, the guide layer 205b and the gate insulating layer 204a are used as a curtain, and the energy of 30 to 1001 ^ 乂 can be used. An ion implantation step is performed on the semiconductor layer 203 to form a second doped region 203b on the semiconductor layer 203 covered by the gate insulating layer 204a but not covered by the conductive layer 205bf, and on the non-conductive layer 2 〇5b and the gate insulating layer 20 ″ form a second doped region 203c by the semiconductor layer 203 of the silicon, and the semiconductor layer 203 covered by the conductive layer 205b forms a semiconductor layer, as shown in FIG. The first doped region 203b is used as a lightly doped drain (LDD); the second doped region 203c is used as a source / drain, S / D); and the semiconductor layer 203 & serves as a transport zone. The self-alignment formed by the manufacturing method provided by the present invention

1221339 V. Description of the invention (6) A thin-film transistor with a lightly doped structure, which includes a substrate 201, a semiconductor ΓΓμΓ, a gate insulating layer 208, and a gate 205b. The semiconductor layer is formed on a substrate. It has a -channel region 2G3a, a first-doped region 2 and a second doped region 203c; the first doped region 203b is formed in the channel region 2 and the second doped region 20c is formed 203b two U-domains in the first doped drain region. The gate insulating layer 20 is formed on the surface of the semiconductor layer, and is: t HT3a and the first doped region 2 ° 3b; and the gate 205b is formed on the gate insulating layer 204a corresponding to the through-force region 20 3a When the Di-I ion implantation step is performed to form the first doped region 203b, because 0, 竑 region 203b is covered by the gate insulating layer 204a, so The doping concentration will be less than that of the second doped region 203c (the conductive layer 2051 of the ion implantation mask) has a narrow top and a wide bottom as the concentration of a doped region 203b gradually increases from the inside to the outside. Therefore, the first example is to make a thin film transistor of C-MOS, which hinders the heavy ion doping of (P) or Kun (As) ions; it is performed as lx 10 "~ 1x1016cm-2 in the semiconductor Acoustic 2 impurities; the second doped region 20c, which is approximately the source doped region, θ— forms a drain and doped region 203b with a doping concentration of about 1 × 1012 ~ 1 × After the first doping is lightly doped and the source-drain region is doped, Cm, shape? Used for steps such as making a dielectric layer of a wire. Follow-up other: = Yu Xizhi Light manufacturing method in thin film transistor, the method provided by the present invention is only / miscellaneous, ',. The structure of the structure and the energy of the ion implantation, ^, ^, ', the width or thickness of the marginal layer, without the need for additional light: f control of the light-drain doped structure. First cover the pattern of the lightly doped structure, 0773-9592tWF (nl); P91264; CI— page Π) 77λ-QSQ? Tu, F ^ n-0010,:,. ~ &Quot; --- ------ Related PB 1221339 V. Description of the Invention (7) Therefore, it will not be limited by the exposure technology, which can effectively avoid the occurrence of alignment errors and improve the electrical performance of thin film transistors. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouches without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be determined by the scope of the attached patent application.

0773-9592twF (nl); P91264; Clarue.ptd Page 12 1221339 Brief Description of Drawings Figures 1 a-1 b are schematic diagrams showing a conventional method for manufacturing a thin film transistor with a lightly doped structure. Figure -2f is a schematic view showing a method for manufacturing a thin film transistor having a lightly doped structure according to the present invention. Explanation of symbols: 102, 102a ~ polycrystalline silicon layer 106 ~ photoresist layer; 120 ~ gate layer; 201 ~ substrate; 20 3, 02a ~ semiconductor layer 20 3c ~ second doped region; 1 0 1 ~ Transparent insulating substrate; 104 ~ Gate insulating layer; 108 ~ Heavily doped region; 122 ~ Lightly doped region; 202 ~ Buffer layer; 230b ~ First doped region; 2 0 4, 2 0 4 a ~ gate insulation layer; 2 5, 5 2a, 5 5b ~ conductive layer; 206, 206a, 206b ~ patterned photoresist layer _

0773-9592twF (nl); P91264; Clarue.ptd Page 13

Claims (1)

1221339 6. Application scope 1. A method for manufacturing a thin film transistor with a self-aligned lightly doped structure, comprising the following steps: providing a substrate, a semiconductor layer formed on the surface of the substrate; and forming a gate on the semiconductor layer A gate insulating layer covering the surface of the semiconductor layer; forming a conductive layer on the gate insulating layer; performing an etching step on the conductive layer to expose a part of the gate insulating layer; and the semiconductor The layer is subjected to an ion implantation step to form a first doped region on the semiconductor layer covered by the gate insulating layer, and a second doped region is formed on the exposed semiconductor layer. 2. The method for manufacturing a thin film transistor with a self-aligned lightly doped structure as described in item 1 of the scope of patent application, wherein the substrate is made of glass. · 3. The method for manufacturing a thin film transistor with a self-aligned lightly doped structure as described in item 1 of the scope of patent application, wherein the semiconductor layer is a polycrystalline silicon layer. 4. The method for manufacturing a thin film transistor with a self-aligned lightly doped structure as described in item 1 of the scope of patent application, wherein the substrate and the semiconductor _ further include a buffer layer. 5. The method for manufacturing a thin film transistor with a self-aligned lightly doped structure as described in item 1 of the scope of the patent application, wherein the thickness of the gate insulating layer is 2000 to 100 00 A. 6. Self-aligned light doping as described in item 1 of the patent application 0773-9592twF (nl); P91264; Clarue.ptd Page 14 1221339 VI. Method for manufacturing thin-film transistors with a patented structure, in which the gate insulating layer is a gate oxide layer. 7. The method for manufacturing a thin film transistor with a self-aligned lightly doped structure as described in item 1 of the scope of the patent application, wherein the conductive layer is a metal layer. 8. The method for manufacturing a thin film transistor with a self-aligned lightly doped structure as described in item 1 of the scope of the patent application, wherein the etching step is plasma etching. 9. The method for manufacturing a thin film transistor with a self-aligned lightly doped structure as described in item 1 of the scope of the patent application, wherein the energy of the ion implantation step is 10 to 100 keV. 10. The method for manufacturing a thin film transistor with a self-aligned lightly doped structure as described in item 1 of the scope of the patent application, wherein the concentration of the first doped region is less than the second doped region 1 The method for manufacturing a thin film transistor with a self-aligned lightly doped structure according to item 1 of the patent scope, wherein the first doped region is a light-drain doped region. 1 2. The method for manufacturing a thin film transistor with a self-aligned lightly doped structure as described in item 1 of the scope of the patent application, wherein the second doped region is a source-drain region. 1 3. A method for manufacturing a thin film transistor with a self-aligned lightly doped structure, including the following steps: providing an insulating transparent substrate; sequentially forming a buffer layer and a semiconductor layer on the surface of the substrate; A gate insulating layer and a conductive layer are sequentially formed on the layer surface. 0773-9592twF (nl); P91264; Clarue.ptd Page 15 1221339 VI. Patent application scope layer and a patterned photoresist layer, where the position of the circled photoresist layer is the position where the gate is subsequently formed; The patterned photoresist is an etching mask, and the conductive layer and the gate insulating layer are sequentially etched to expose the semiconductor layer; the conductive layer is etched with an etching gas to expose a part of the gate insulating layer; The patterned photoresist layer; and performing an ion implantation step on the semiconductor layer to form a second doped region in the semiconductor layer covered by the gate insulating layer, and forming a first doped region on the exposed semiconductor layer Doped region. 14. The method for manufacturing a thin-film transistor having a self-aligned lightly doped structure as described in item 13 of the scope of patent application, wherein the substrate is made of glass. 1 5. The method for manufacturing a thin film transistor with a self-aligned lightly doped structure as described in item i 3 of the scope of the patent application, wherein the semiconductor layer is a polysilicon layer. 16. The method for manufacturing a thin-film transistor having a self-aligned light-heterode structure as described in item 13 of the scope of the patent application, wherein the gate insulation layer 1 has a degree of 200 to 100 00 A. θ sub 1 7 · The method for manufacturing a thin film transistor with a self-aligned and lightly doped heterostructure as described in item 13 of the scope of the patent application, wherein the gate insulating layer is an oxide layer. … 1 8 · A method for manufacturing a thin film transistor with a heterostructure as described in item 13 of the scope of the patent application, wherein the conductive layer is made of gold 1221339 Sixth, the scope of patent application. 19 · The method for manufacturing a thin-film transistor having a self-aligned lightly doped structure as described in item 13 of the scope of patent application, wherein the silver-engraved gas is a mixed gas of an oxygen-containing gas. 20. The method for manufacturing a thin film transistor with a self-quasi-lightly doped structure as described in item 19 of the scope of patent application, wherein the coin-cut gas further includes a chlorine-containing gas. 2 1 · The method for manufacturing a thin film transistor with a self-aligned lightly doped structure as described in item 13 of the scope of the patent application, wherein the last name is etched by plasma or reactive ion. 22. The method for manufacturing a thin film transistor having a self-aligned lightly doped structure as described in item 3 of the patent application, wherein the energy of the ion implantation step is 10 to 100 keV. 2 3 · The method for manufacturing a thin film transistor with a self-aligned lightly doped structure as described in item 13 of the scope of patent application, wherein the first doped region is smaller than the second doped region. Multiply 24. The method for manufacturing a self-explanatory film transistor as described in item 3 of the scope of the patent application, wherein the first-doped region 7 is light and extremely doped. ~ Ping Gong 25. The method for manufacturing a thin film transistor with a self-doped heterostructure as described in item 13 of the scope of the patent application, wherein the second doped drain region. Dagger source 2 6. Thin film transistor with self-aligned lightly doped structure 1221339 Sixth, the scope of patent application is a substrate and a semiconductor layer formed on the substrate. The semiconductor layer has a south region, a first doped region formed in a peripheral region of the channel region, and a doped region formed on the substrate. A peripheral region of the first doped drain region; a gate insulation layer formed on the surface of the semiconductor layer, and covering the channel region and the gate doped region; and a gate formed On the gate insulating layer corresponding to the channel region, the thin film transistor having a self-to-hi exchange heterostructure as described in item 26 of the scope of patent application, wherein the substrate is composed of a chip. Gong Xi 28. The thin-film transistor having a self-aligned heterostructure as described in item 26 of the scope of the patent application, wherein the semiconductor layer is polycrystalline. 29. A thin film transistor having a self-aligning quasi-hybrid structure as described in item 26 of the scope of patent application, wherein a buffer layer is further included between the substrate and the semiconductor layer. 3 0 · The thin film transistor with a self-aligned lightly doped structure as described in item 26 of the scope of the patent application, wherein the thickness of the gate insulating layer is 2000 to 1 0 0 0 A 0 3 1. The thin film transistor having a self-aligned lightly doped structure as described in item 26 of the patent application scope, wherein the gate insulating layer is a gate oxide layer. 32. The thin-film transistor having a self-aligned lightly doped structure as described in item 26 of the application, wherein the gate insulating layer does not cover the second doped region. 3 3. The thin-film transistor having a self-aligned lightly doped structure as described in item 26 of the patent application scope, wherein the conductive layer is a metal layer. 1221339 VI. Scope of patent application 3 4. The thin film transistor having a self-aligned light doped structure as described in item 26 of the scope of patent application, wherein the concentration of the first doped region is smaller than that of the second doped region. 3 5. The thin film transistor having a self-aligned lightly doped structure as described in item 26 of the scope of the patent application, wherein the first doped region is a light-drain doped region. 36. The thin film transistor having a self-aligned lightly doped structure as described in item 26 of the patent application scope, wherein the second doped region is a source-drain region. 37. The thin film transistor with a self-aligned light doped structure as described in item 26 of the scope of the patent application, wherein the gate is a trapezoidal gate with a narrow upper and lower width. 0773-9592twF (nl); P91264; Clarue.ptd Page 19