JP3087363B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor formed on an insulating substrate or a conductive substrate and effective for application to a liquid crystal display device, a semiconductor integrated circuit, and the like, and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIGS. 2A to 2C are diagrams illustrating an example of a thin film transistor formed by a conventional technique, with reference to element cross-sectional views in each manufacturing process. First, FIG.
1A, a semiconductor layer 202 is stacked on a substrate 201, patterned into a desired shape, and then a gate insulating film 203 is formed by a thermal oxidation method. After that, the semiconductor layer 204 containing impurities is laminated and patterned to leave a portion serving as a gate electrode, and impurity ions 205 are implanted using the portion as a mask to form a source and drain region 2.
06 and a channel region 207 are formed as shown in FIG. Then, after laminating an interlayer insulating film 208 and opening a contact hole 209, the source and drain electrode terminals 2 are formed.
10 is formed and completed. This state is shown in FIG.

FIG. 3 illustrates another example of a thin film transistor formed by a conventional technique, with reference to a sectional view of an element in each manufacturing process. First, as shown in FIG. 3A, a semiconductor layer to which an impurity is added is laminated and patterned on a substrate 301 to form a source and drain region 302.
And Next, as shown in FIG. 3B, a semiconductor layer is stacked and patterned to form a channel region 303, a gate insulating film 304 is stacked, and then a gate electrode layer is stacked.
The gate electrode 305 is patterned into a desired shape. Then, an interlayer insulating film 306 is laminated, a contact hole 307 is opened, and the source and drain electrode terminals 30 are formed.
8 is formed, and a thin film transistor is completed as shown in FIG.

[0004]

In recent years, with the development of semiconductor integrated circuits in liquid crystal display devices, such thin film transistors are required to have higher speed, higher integration, and higher performance. When considering high integration, the problem is to reduce the resistance of the wiring. In the thin film transistor formed by the conventional technique shown in FIG. 2 described above, the ion implantation method is used for forming the source and drain regions, and there is a process of activating the impurities thereafter. Means that a semiconductor thin film having high heat resistance is used. However, when a semiconductor thin film is used for the gate electrode, it is necessary to form the wiring layer with another material in order to reduce the wiring resistance, which complicates the process. Conversely, if the gate electrode and the wiring layer are formed at the same time, the resistance of the wiring increases, and it is difficult to achieve high integration. Therefore, it is desired to simultaneously form the gate electrode and the wiring layer with a metal thin film having a low resistance. On the other hand, when a thin film transistor is formed by the conventional technique shown in FIG. 3, a metal thin film can be used as a gate electrode because ion implantation is not performed using the gate electrode as a mask. However, when this structure and manufacturing method are used, the overlap between the gate electrode and the source and drain regions forms a parasitic capacitance. This parasitic capacitance hinders high speed and high performance of the thin film transistor. Further, if the parasitic capacitance varies due to a mask shift or the like, the characteristics of the thin film transistor also vary. Therefore, it is necessary to reduce the parasitic capacitance in order to realize high speed, high performance, uniformity, and reproducibility of the thin film transistor. Further, when the source and drain regions are formed without using the ion implantation method, an increase in leakage current is observed due to a junction defect between the source and drain regions and the channel portion, and it is difficult to reduce power consumption. Therefore, in order to realize low power consumption of the thin film transistor, it is desired to form the source and drain regions by an ion implantation method.

The present invention solves the problems of the structure and the manufacturing method of such a thin film transistor. It is an object of the present invention to achieve high speed, high integration, high performance and low power consumption. And a method of manufacturing the same with less variation.

[0006]

According to a method of manufacturing a thin film transistor of the present invention, a silicon layer serving as a source / drain / channel is formed on a substrate, an insulating film is formed on the silicon layer, and a channel of the silicon layer is formed. A source / drain region is formed in the silicon layer by forming a resist on the region to be ion-implanted, an insulating film layer is formed on the silicon layer and the resist, and the resist and the resist The insulating film layer is removed, and a gate electrode is formed on the region where the resist and the insulating film layer are removed and on the insulating film layer.

[0007]

According to the structure and the manufacturing method of the thin film transistor of the present invention, the portion where the gate electrode and the channel portion overlap has a single insulating film, but the portion where the gate electrode overlaps the source and drain regions is the insulating film. Because the film is thicker,
The parasitic capacitance formed there is reduced, and the influence of the parasitic capacitance is reduced, so that the speed of the thin film transistor can be increased. In addition, since the source and drain regions are formed by the ion implantation method, the number of junction defects between the source and drain regions and the channel region is small, and the leakage current can be reduced. In addition, since the activation of the source and drain regions is performed before the formation of the gate electrode, a metal which is weak against heat can be used as the gate electrode. By forming the wiring layer at the same time, the resistance of the wiring layer can be reduced.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS.
The above will be described in detail with reference to element cross-sectional views for each manufacturing process. First, as shown in FIG.
After laminating the semiconductor layer 102 on 1 and patterning,
An insulating thin film serving as the gate insulating film 103 is stacked. In this embodiment, an insulating substrate is used as the substrate 101. However, the above process may be performed after an insulating film is laminated on the conductive substrate or the conductive substrate. The formation of the semiconductor layer 102 includes:
A semiconductor formed by a low-pressure CVD method or a plasma CVD method is used. The gate insulating film 103 may be formed by a thermal oxidation method, a thermal nitridation method, a normal pressure CVD method, a low pressure CVD method,
A silicon dioxide film, a silicon nitride film, or the like formed by a plasma CVD method, an ECR plasma CVD method, a sputtering method, or the like is used. Next, after applying and patterning a resist 104 on the entire surface, using this as a mask, an impurity 105 is introduced by an ion implantation method such as an ion implantation method or an ion doping method to form a source / drain region 106 and a channel region 107. , FIG.
(B). In this embodiment, as a mask for ion implantation when forming the source and drain regions 106,
Although the resist is used, any thin film, such as a semiconductor film or an insulating film, may be used as long as the thin film has a selectivity with respect to the gate insulating film 103 in etching.

Next, a sputtering method or an ECR plasma CV
Using an anisotropic device such as D method, the insulating film 10
When the resist 8 is formed, as shown in FIG.
At the stepped portion, the coverage is poor. Thereafter, when the resist 104 is removed, the insulating thin film 10 on the resist is removed.
8 is also removed at the same time.

After that, the source and drain regions are activated, and a conductive thin film is laminated and patterned to form a gate electrode 109. This state is shown in FIG. For the activation of the source and drain regions, a thermal annealing method, a laser annealing method, a lamp annealing method, or the like is used. In addition, a low-resistance metal thin film such as Cr or Al is formed on the gate electrode by a sputtering method or the like and used.

Thereafter, an interlayer insulating film 110 is laminated, a contact hole 111 is opened, and a source and drain electrode terminal 112 is formed. Thus, a thin film transistor is completed as shown in FIG. A film similar to the gate insulating film 103 is formed on the interlayer insulating film 110 by a similar method.
In addition to being used, an organic thin film such as polyimide may be used.

According to the structure of the thin film transistor formed as described above, the gate electrode is effectively applied with a gate voltage because the overlapping portion of the gate electrode and the channel portion is only the gate insulating film, and on the other hand, it becomes a parasitic capacitance. At the overlapping portion of the gate electrode and the source and drain regions, the parasitic capacitance can be reduced because of the thick insulating film. Further, since the source and drain regions are formed by the ion implantation method, the number of junction defects between the source and drain regions and the channel region is small, so that leakage current can be reduced. Since the activation of the source and drain regions is performed before the formation of the gate electrode, a metal thin film can be used as the gate electrode. By simultaneously forming the wiring layer, the process can be simplified and the wiring resistance can be reduced. Resistance can be realized at the same time.

[0013]

As described above, according to the structure of the thin film transistor formed by the method simply described for each manufacturing process,
The following many effects can be obtained.

1). Since the thickness of the insulating film in a portion where the gate electrode overlaps with the source and drain regions is large, parasitic capacitance can be reduced and high speed operation can be achieved.

2). Since the thickness of the insulating film in the overlapping portion between the gate electrode and the source and drain regions is large, the parasitic capacitance can be reduced, and the variation caused by mask displacement can be reduced.

[0016]

[0017]

[Brief description of the drawings]

1 (a) to 1 (e) of a thin film transistor of the present invention,
FIG. 6 is a sectional view of an element in each manufacturing process shown in the example.

FIGS. 2A to 2C are cross-sectional views of an element in each manufacturing process of a thin film transistor according to a conventional technique.

3 (a) to 3 (c) are cross-sectional views of elements in each manufacturing process of a thin film transistor according to a conventional technique.

[Explanation of symbols]

 101, 201, 301 ... substrates 102, 202 ... semiconductor layers 103, 203, 304 ... gate insulating film 104 ... resist 105, 205 ... impurities 106, 206, 302 ... source And drain region 107, 207, 303 channel region 108 insulating film 109, 204, 305 gate electrode 110, 208, 306 interlayer insulating film 111, 209, 307 contact hole 112, 210, 308... Source and drain electrodes

Claims (1)

(57) [Claims] 1. A silicon layer serving as a source / drain / channel is formed on a substrate, an insulating film is formed on the silicon layer, a resist is formed on a region of the silicon layer serving as a channel, and ion implantation is performed. Forming source / drain regions in the silicon layer; forming an insulating film layer on the silicon layer and the resist; removing the resist and the insulating film layer on the resist; A method for manufacturing a thin film transistor, comprising forming a gate electrode on the region where the film layer has been removed and on the insulating film layer.