JP3173486B2 - Digital CMOS circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital CMOS circuit whose threshold voltage can be controlled.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram of a conventional digital CMOS circuit. In the digital CMOS circuit shown in FIG.
When the threshold voltage at the input terminal 5 is
Is designed to fall within the range of 20% to 80% of the voltage Vdd of the
It is affected by the threshold voltages of the MOS transistor and the PMOS transistor.

In addition, since the power supply voltage has been reduced in recent years as the process has been miniaturized, the noise margin of so-called digital signals has been reduced, and the influence of the threshold voltage on the noise margin has been increased. ing.

Further, in a battery-driven system such as a portable telephone, low current consumption is required in order to use the battery for a long time with a single charge.

[0005]

As described above, in the conventional digital CMOS circuit, the threshold voltage at the input terminal is greatly influenced by the threshold voltages of the PMOS and NMOS transistors, As the voltage drops and the noise margin of digital signals is decreasing, the influence of the threshold voltage on the noise margin is increasing, and a circuit that can control the threshold voltage of the circuit is desired. I have. In addition, due to the demand for low current consumption, a circuit that does not require a constant current like an analog comparator is desired, although the accuracy is good.

An object of the present invention is to provide a digital CMOS circuit in which a threshold voltage can be controlled and a steady current does not flow.

[0007]

Means for Solving the Problems Digital CM of the present invention
The OS circuit includes a differential pair PMOS transistor having one differential input connected to the input terminal, the other differential input connected to the reference voltage input terminal, and one differential output connected to the output terminal; A PMOS transistor having a drain connected to the source of the differential pair PMOS transistor, a source connected to the first power supply, and a gate connected to the input terminal; a second differential output of the differential pair PMOS transistor; A first switch connected between the power supply;
A differential pair NMOS transistor having one differential input connected to the input terminal, the other differential input connected to the reference voltage input terminal, and one differential output connected to the output terminal; An NMOS transistor having a source connected to the source of the active pair NMOS transistor, a source connected to the second power supply, and a gate connected to the input terminal; the other differential output of the differential pair NMOS transistor;
A second switch connected between the power supply and a switch control circuit having an input connected to the output terminal and an output connected to respective control terminals of the first switch and the second switch; It is characterized by the following.

[0008]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a digital CMOS circuit showing a first embodiment of the present invention. In FIG. 1, a differential circuit including a PMOS transistor 10 and a differential pair PMOS transistor 100, an NMOS transistor 20 and a differential pair NMO
One differential input of the differential circuit constituted by the S transistor 200 is connected to the input terminal 5, and the other differential input is connected to the reference voltage input terminal 7.

One differential output of the differential pair PMOS transistor 100 and one differential output of the differential pair NMOS transistor 200 are interconnected and connected to the output terminal 6. Also, the differential pair PMOS transistor 10
The other differential output of 0 is connected to the second power supply 2 through the switch 30, and the other differential output of the differential pair NMOS transistor 200 is connected to the first power supply 1 through the switch 40.

The source of the PMOS transistor 10 is the first
The power supply 1 is connected, the drain is connected to the source of the differential pair PMOS transistor 100, and the gate is connected to the input terminal 5
The source of the NMOS transistor 20 is connected to the second power supply 2 and the drain is a differential pair NMOS.
The transistor 200 is connected to the source, and the gate is connected to the input terminal 5.

The input of the switch control circuit 300 is connected to the output terminal 6, and the output thereof is connected to the switch 30 and the switch 40.
Are connected to the respective control terminals.

FIG. 2 shows a differential pair PMOS transistor 1
It is a figure showing an example of 00. In the differential pair PMOS transistor, as shown in FIG. 2, the source sides of two PMOS transistors are connected to each other.

FIG. 3 shows a differential pair NMOS transistor 2
It is a figure showing an example of 00. In the differential pair NMOS transistor, as shown in FIG. 3, the source sides of two NMOS transistors are connected to each other.

Next, the operation of this embodiment will be described with reference to FIG.
This will be described with reference to FIG.

A state is assumed in which a voltage Vdd is applied to the first power supply 1, a zero voltage is applied to the second power supply 2, and Vdd / 2 is applied to the reference voltage input terminal 7. At this time,
Consider a case where a voltage that changes from zero to Vdd is applied to the input terminal 5.

First, consider the case where the voltage at the input terminal 5 is zero. In this state, the NMOS transistor 20
In the F state, the currents I20 and I200 are both zero, while the PMOS transistor 10 is in the ON state, and the differential pair PMOS transistor 100
Is turned on so that can be flowed. Therefore, output terminal 6
Has a voltage as high as Vdd.

At this time, the switch control circuit 300 detects that the output terminal 6 is at a high level,
Is turned off and the switch 40 is turned on. This is because the first power supply 1 → the PMOS transistor 10 → the differential pair PMO
This is to prevent a steady current from flowing from the S transistor 100 → the switch 30 → the second power supply 2.

Next, consider the case where the voltage of the input terminal 5 changes before and after Vdd / 2. In this state, the PMOS transistor 10, the NMOS transistor 20, the switch 4
0 indicates an ON state, the switch 30 indicates an OFF state, and currents I10 and I20 are flowing. Current I100
Since the switch 30 is OFF, the same current as the current I10 flows.

On the other hand, the current I200 is a value to which the current of I20 is distributed by comparing the voltage of the input terminal 5 and the voltage of the reference voltage input 7. The distribution of the current I200, i.e., I20, greatly changes when the voltage of the input terminal 5 is around Vdd / 2. The voltage of the input terminal 5 rises, and I200> I
When it reaches 100, the output terminal 6 tilts to the zero side.
When the voltage level of the output terminal 6 enters the low level range, the switch control circuit 300 operates to turn on the switch 30 and turn off the switch 40. Switch 30 is O
N further reduces the current in I100,
Is turned off, the current of I200 further increases, and the decrease in the voltage level of the output terminal 6 is accelerated.

Next, consider the case where the voltage of the input terminal 5 is Vdd. In this state, the PMOS transistor 10
In the F state, the currents I10 and I100 are both zero, while the NMOS transistor 20 is in the ON state, and the differential pair NMOS transistor 200 is
Is turned on so that can be flowed. Therefore, output terminal 6
Has a voltage as low as zero volts.

At this time, the switch 30 is ON and the switch 40 is OFF. This turns off the switch 40
And the first power supply 1 → switch 40 → differential pair NMOS
Transistor 200 → NMOS transistor 20 → Second
This is to prevent the current from constantly flowing to the power supply 2.

As described above, this embodiment operates as a circuit in which the input is compared with the reference voltage, the output changes, and the influence of the threshold value of the MOS transistor is hardly affected. Moreover, no current flows constantly.

FIG. 4 is a circuit diagram showing a specific example of the first embodiment of the present invention. The difference from FIG.
0 is a PMOS transistor and switch 40 is an NMOS transistor
That is, the switch control circuit is constituted by a non-inverting amplifier with a transistor. The operation is as described above.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention. Unlike the first embodiment, the switch control circuit 300 is configured by a non-inverting amplifier with hysteresis.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention. The third embodiment does not use the switch control circuit 300, but uses the signal of the output terminal directly to switch 30.
And the switch 40 are controlled.

[0027]

As described above, according to the present invention, unlike a conventional digital CMOS circuit, the degree to which the threshold voltage of a circuit is affected by the threshold voltages of PMOS and NMOS transistors is reduced. The variation range of the threshold voltage can be controlled. In particular, in a region where the power supply voltage is low, the influence of the threshold voltage on the noise margin increases. Therefore, controlling the threshold voltage as close to half of the power supply as possible has a great effect on the noise margin.

Further, according to the present invention, since the steady current flow is restricted, the current consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a digital C showing a first embodiment of the present invention.
FIG. 3 is a circuit diagram of a MOS circuit.

FIG. 2 is a diagram illustrating an example of a PMOS differential pair transistor.

FIG. 3 is a diagram illustrating an example of an NMOS differential pair transistor.

FIG. 4 is a circuit diagram showing a specific example of the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention.

FIG. 7 is a circuit diagram of a conventional digital CMOS circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st power supply 2 2nd power supply 5 Input terminal 6 Output terminal 7 Reference voltage input terminal 10, 50 PMOS transistor 20, 60 NMOS transistor 30, 40 Switch 100 Differential pair PMOS transistor 200 Differential pair NMOS transistor 300 Switch control circuit

Claims (6)

(57) [Claims] 1. A differential pair PMOS transistor having one differential input connected to an input terminal, the other differential input connected to a reference voltage input terminal, and one differential output connected to an output terminal. A PMOS transistor having a drain connected to the source of the differential pair PMOS transistor, a source connected to the first power supply, and a gate connected to the input terminal; A first switch connected between the two power supplies, one differential input is connected to the input terminal, the other differential input is connected to the reference voltage input terminal, and one differential output is connected to the output terminal. A connected differential pair NMOS transistor, a drain connected to the source of the differential pair NMOS transistor, a source connected to the second power supply, and a gate connected to the input terminal NMOS transistor, a second switch connected between the other differential output of the differential pair NMOS transistor and a first power supply, an input connected to an output terminal, and an output connected to the first switch. And a switch control circuit connected to each control terminal of the second switch. 2. A differential pair PMOS transistor having one differential input connected to an input terminal, the other differential input connected to a reference voltage input terminal, and one differential output connected to an output terminal. A first PMOS transistor having a drain connected to the source of the differential pair PMOS transistor, a source connected to the first power supply, and a gate connected to the input terminal; and a source connected to the other of the differential pair PMOS transistor. A second PMOS transistor connected to the differential output and having a drain connected to the second power supply; one differential input connected to the input terminal; the other differential input connected to the reference voltage input terminal; A differential pair NMOS transistor having a differential output connected to the output terminal; a drain connected to the source of the differential pair NMOS transistor; A first NMOS transistor having a gate connected to the input terminal, a second NMOS transistor having a source connected to the other differential output of the differential pair NMOS transistor, and a drain connected to the first power supply; And an input connected to the output terminal and an output connected to the second PMOS transistor.
And a switch control circuit including a non-inverting amplifier connected to the gates of the transistor and the second NMOS transistor. 3. The digital CMOS circuit according to claim 2, wherein said non-inverting amplifier is a non-inverting amplifier with hysteresis. 4. A differential pair PMOS transistor having one differential input connected to an input terminal, the other differential input connected to a reference voltage input terminal, and one differential output connected to an output terminal. A first PMOS transistor having a drain connected to the source of the differential pair PMOS transistor, a source connected to the first power supply, and a gate connected to the input terminal; and a source connected to the other of the differential pair PMOS transistor. A second PMOS transistor connected to the differential output, the drain connected to the second power supply, and the gate connected to the output terminal; one differential input connected to the input terminal; A differential pair NMOS transistor having one differential output connected to the voltage input terminal and one differential output connected to the output terminal; and a drain connected to the differential pair NMOS transistor. A first NMOS transistor having a source connected to the second power supply and a gate connected to the input terminal; a source connected to the other differential output of the differential pair NMOS transistor; A second NMOS transistor connected to one power supply and having a gate connected to the output terminal. 5. The digital CMOS circuit according to claim 1, wherein the digital CMOS circuit is used in an input stage of a low voltage drive LSI. 6. An L for a portable terminal, wherein the digital CMOS circuit according to claim 1 is used.
SI.