JPH0667739A - Semiconductor integrated device - Google Patents
Semiconductor integrated deviceInfo
- Publication number
- JPH0667739A JPH0667739A JP4217575A JP21757592A JPH0667739A JP H0667739 A JPH0667739 A JP H0667739A JP 4217575 A JP4217575 A JP 4217575A JP 21757592 A JP21757592 A JP 21757592A JP H0667739 A JPH0667739 A JP H0667739A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- supply voltage
- circuit
- voltage
- internal step
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Control Of Voltage And Current In General (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
- Dram (AREA)
- Direct Current Feeding And Distribution (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積装置に関し、
特に内部降圧電源回路を有する半導体集積装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated device,
In particular, it relates to a semiconductor integrated device having an internal step-down power supply circuit.
【０００２】[0002]
【従来の技術】従来の半導体集積装置の内部降圧電源回
路は、一例として図４に示すように、一端に外部からの
電源電圧Ｖｃｃを受ける第１の定電流源Ｉ１，ソースを
この定電流源Ｉ１の他端と接続しゲート及びドレインを
接地電位点を接続するＰ型の第１のトランジスタＱ１，
ソースを定電流源Ｉ１の他端と接続するＰ型の第２のト
ランジスタＱ２，並びに一端をトランジスタＱ２のゲー
ト及びドレインと接続し他端を接地電位点と接続する第
２の定電流源Ｉ２を備え定電流源Ｉ２とトランジスタＱ
２との接続点から内部基準電圧Ｖｉｒを出力する基準電
圧発生回路１１と、正入力端（＋）に内部基準電圧Ｖｉ
ｒを入力し電源電圧Ｖｃｃを受けて動作する差動増幅器
ＯＰ１，この差動増幅器ＯＰ１の負入力端（−）と接地
電位点との間に接続された抵抗Ｒ１，及び差動増幅器Ｏ
Ｐ１の出力端と負入力端との間に接続された可変抵抗器
Ｒ２を備え内部基準電圧Ｖｉｒを所定のレベルの内部基
準電圧Ｖｉｒｒに調整する調整回路１２と、正入力端
（＋）に内部基準電圧Ｖｉｒｒを入力し出力端と負入力
譚（−）とを直接接続して電源電圧Ｖｃｃを受けて動作
する差動増幅器ＯＰ２を備え所定の電流容量の内部降圧
電源電圧Ｖｉｐｏを出力する出力回路１３とを有する構
成となっている。2. Description of the Related Art A conventional internal step-down power supply circuit for a semiconductor integrated device, as shown in FIG. 4 by way of example, has a first constant current source I1 receiving a power supply voltage Vcc from the outside at one end as a constant current source. P-type first transistor Q1, which connects to the other end of I1 and connects the gate and drain to the ground potential point
A P-type second transistor Q2 whose source is connected to the other end of the constant current source I1 and a second constant current source I2 whose one end is connected to the gate and drain of the transistor Q2 and whose other end is connected to the ground potential point Provided constant current source I2 and transistor Q
The reference voltage generating circuit 11 that outputs the internal reference voltage Vir from the connection point with the reference voltage 2 and the internal reference voltage Vi at the positive input terminal (+).
A differential amplifier OP1, which receives r and operates by receiving a power supply voltage Vcc, a resistor R1 connected between a negative input terminal (-) of this differential amplifier OP1 and a ground potential point, and a differential amplifier O.
An adjusting circuit 12 including a variable resistor R2 connected between the output terminal of P1 and a negative input terminal, for adjusting the internal reference voltage Vir to an internal reference voltage Virr of a predetermined level, and an internal adjustment circuit 12 at the positive input terminal (+). An output circuit for inputting the reference voltage Virr, directly connecting the output terminal and the negative input terminal (-) and receiving the power supply voltage Vcc, and including the differential amplifier OP2 for outputting the internal step-down power supply voltage Vipo having a predetermined current capacity. 13 is included in the configuration.
【０００３】この内部降圧電源回路１では、電源電圧Ｖ
ｃｃがある程度高くなると、内部基準電圧Ｖｉｒがトラ
ンジスタＱ１，Ｑ２のしきい値の差となるので、出力さ
れる内部降圧電源電圧Ｖｉｐｏは温度依存性、外部電源
電圧依存性の極めて少ない安定した一定電圧となる（図
５参照）。In this internal step-down power supply circuit 1, the power supply voltage V
When cc becomes high to some extent, the internal reference voltage Vir becomes the difference between the threshold values of the transistors Q1 and Q2, so that the output internal step-down power supply voltage Vipo is a stable constant voltage with very little temperature dependence and external power supply voltage dependence. (See FIG. 5).
【０００４】[0004]
【発明が解決しようとする課題】この従来の半導体集積
装置では、トランジスタＱ１，Ｑ２のしきい値の差によ
り内部基準電圧Ｖｉｒを発生しているので、外部からの
電源電圧Ｖｃｃがある程度高くなると安定した一定電圧
の内部降圧電源電Ｖｉｐｏを得ることができるが、電源
電圧Ｖｃｃが低くなると不安定になるだけでなく、内部
降圧電源回路１により電力を消費されるという問題点が
あった。In this conventional semiconductor integrated device, since the internal reference voltage Vir is generated due to the difference in the threshold values of the transistors Q1 and Q2, the internal reference voltage Vir is stable when the external power supply voltage Vcc becomes high to some extent. Although the internal step-down power supply voltage Vipo having the constant voltage can be obtained, there is a problem that the internal step-down power supply circuit 1 consumes power as well as becoming unstable when the power supply voltage Vcc becomes low.
【０００５】本発明の目的は、外部からの電源電圧が低
く一定電圧の内部降圧電源電圧が得られないときには外
部からの電源電圧をそのまま出力して後段回路の動作を
安定させ、かつ内部降圧電源回路における消費電力をな
くすことができる半導体集積装置を提供することにあ
る。An object of the present invention is to output the power supply voltage from the outside as it is when the power supply voltage from the outside is low and an internal step-down power supply voltage of a constant voltage cannot be obtained, and to stabilize the operation of the latter stage circuit, It is an object of the present invention to provide a semiconductor integrated device capable of eliminating power consumption in a circuit.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体集積装置
は、外部からの電源電圧を受け、この電源電圧が内部基
準電圧より高いときこの内部基準電圧と対応した一定の
電圧の内部降圧電源電圧を発生する内部降圧電源回路
と、前記外部からの電源電圧を分圧する電源電圧分圧回
路と、この電源電圧分圧回路の出力電圧のレベルを調整
する調整手段と、この調整手段により調整された前記電
源電圧分圧回路の出力電圧を基準電圧と比較し前記外部
からの電源電圧が前記内部基準電圧に達したときレベル
変化する電源電圧判定信号を出力する電源電圧判定回路
と、前記電源電圧判定信号のレベル変化に応答して、前
記外部からの電源電圧が前記内部基準電圧より高いとき
前記内部降圧電源電圧を出力し、低いとき前記外部から
の電源電圧を出力すると共に前記内部降圧電源回路への
外部からの電源電圧の供給を停止する切換回路とを有し
ている。A semiconductor integrated device of the present invention receives a power supply voltage from the outside, and when the power supply voltage is higher than an internal reference voltage, an internal step-down power supply voltage of a constant voltage corresponding to the internal reference voltage. Generating an internal step-down power supply circuit, a power supply voltage dividing circuit for dividing the power supply voltage from the outside, adjusting means for adjusting the output voltage level of the power supply voltage dividing circuit, and the adjusting means. A power supply voltage determination circuit that compares the output voltage of the power supply voltage dividing circuit with a reference voltage and outputs a power supply voltage determination signal that changes in level when the power supply voltage from the outside reaches the internal reference voltage; In response to a signal level change, the internal step-down power supply voltage is output when the external power supply voltage is higher than the internal reference voltage, and the external power supply voltage is output when the external power supply voltage is low. And a switching circuit for stopping the supply of power supply voltage from outside to the internal step-down power supply circuit with.
【０００７】また、調整手段を、電源電圧分圧回路内に
設けて構成される。The adjusting means is provided in the power supply voltage dividing circuit.
【０００８】また、調整手段を基準電圧のレベルを調整
する回路とし、電源電圧判定回路を、電源電圧分圧回路
の出力電圧を前記調整手段により調整された基準電圧と
比較する回路として構成される。Further, the adjusting means is a circuit for adjusting the level of the reference voltage, and the power supply voltage judging circuit is constituted as a circuit for comparing the output voltage of the power supply voltage dividing circuit with the reference voltage adjusted by the adjusting means. .
【０００９】[0009]
【実施例】次に本発明の実施例について図面を参照して
説明する。Embodiments of the present invention will now be described with reference to the drawings.
【００１０】図１は本発明の第１の実施例を示す回路図
である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
【００１１】この実施例は、基準電圧発生回路１１，調
整回路１２，及び出力回路１３を備え、外部からの電源
電圧Ｖｃｃを受けこの電源電圧Ｖｃｃが内部基準電圧Ｖ
ｉｒｒより高いときこの、内部基準電圧Ｖｉｒｒと対応
した一定の電圧の内部降圧電源電圧Ｖｉｐｏを発生する
図４の従来例と同一構成の内部降圧電源回路１と、可変
抵抗Ｒ３，Ｒ４を備え、 外部からの電源電圧Ｖｃｃを
分圧すると共にこの分圧された電圧のレベルを調整する
調整手段を含む電源電圧分圧回路２と、差動増幅器ＯＰ
３及びインバータＩＶ１を備え、電源電圧分圧回路２の
出力電圧Ｖｐｄを基準電圧Ｖｒと比較し外部からの電源
電圧Ｖｃｃが内部基準電圧Ｖｉｒｒに達したときレベル
変化する電源電圧判定信号ＶＪを出力する電源電圧判定
回路３と、電源電圧判定信号ＶＪのレベル変化に応答し
てレベル変化する制御信号ＳＣを発生する切換制御回路
４と、スイッチ回路ＳＷ１，ＳＷ２を備え、制御信号Ｓ
Ｃのレベルに応答して外部からの電源電圧Ｖｃｃが内部
基準電圧Ｖｉｒｒより高いとき内部降圧電源回路１へ電
源電圧Ｖｃｃを供給すると共に電圧Ｖｉｐｏを出力し、
低いとき外部からの電源電圧Ｖｃｃを出力すると共に、
内部降圧電源回路１への外部からの電源電圧Ｖｃｃの供
給を停止する切換回路５とを有する構成となっている。This embodiment comprises a reference voltage generating circuit 11, an adjusting circuit 12, and an output circuit 13, and receives a power supply voltage Vcc from the outside, and this power supply voltage Vcc is an internal reference voltage Vcc.
An internal step-down power supply circuit 1 having the same configuration as that of the conventional example of FIG. 4, which generates an internal step-down power supply voltage Vipo having a constant voltage corresponding to the internal reference voltage Virr when higher than irr, and variable resistors R3 and R4 are provided. The power supply voltage dividing circuit 2 including an adjusting means for dividing the power supply voltage Vcc from the device and adjusting the level of the divided voltage, and a differential amplifier OP.
3 and an inverter IV1 and compares the output voltage Vpd of the power supply voltage dividing circuit 2 with the reference voltage Vr, and outputs the power supply voltage determination signal VJ whose level changes when the external power supply voltage Vcc reaches the internal reference voltage Virr. The control signal S includes a power supply voltage determination circuit 3, a switching control circuit 4 that generates a control signal SC that changes its level in response to a level change of the power supply voltage determination signal VJ, and switch circuits SW1 and SW2.
When the external power supply voltage Vcc is higher than the internal reference voltage Virr in response to the level of C, the power supply voltage Vcc is supplied to the internal step-down power supply circuit 1 and the voltage Vipo is output.
When the power source voltage Vcc is output from the outside when the voltage is low,
A switching circuit 5 for stopping the supply of the power supply voltage Vcc from the outside to the internal step-down power supply circuit 1.
【００１２】次にこの実施例の動作について説明する。
図２はこの実施例の動作を説明するための各部電圧のレ
ベル関係を示す特性図である。Next, the operation of this embodiment will be described.
FIG. 2 is a characteristic diagram showing the level relation of the voltage of each part for explaining the operation of this embodiment.
【００１３】まず、可変抵抗Ｒ３，Ｒ４を調整して、Ｖ
ｐｄ＝Ｖｒとなる点Ｐを、電源電圧Ｖｃｃが内部基準電
圧Ｖｉｒｒと等しくなる点に一致させる。この結果、電
源電圧判定信号ＶＪ及び制御信号ＳＣは、Ｖｐｄ＝Ｐｒ
すなわちＶｃｃ＝Ｖｉｒｒのときレベル変化し、電源電
圧Ｖｃｃが低くＶｐｄ＜Ｖｉ（Ｖｃｃ＜Ｖｉｒｒ）のと
きは例えば低レベル、電源電圧Ｖｃｃが高くなりＶｐｄ
＞Ｖｒ（Ｖｃｃ＞ｖｉｒｒ）のときは例えば高レベルと
なる。First, the variable resistors R3 and R4 are adjusted to V
The point P where pd = Vr is matched with the point where the power supply voltage Vcc becomes equal to the internal reference voltage Virr. As a result, the power supply voltage determination signal VJ and the control signal SC are Vpd = Pr
That is, when Vcc = Virr, the level changes, and when the power supply voltage Vcc is low and Vpd <Vi (Vcc <Virr), for example, the low level, the power supply voltage Vcc increases and Vpd
When> Vr (Vcc> virr), the level becomes high, for example.
【００１４】そして、制御信号ＳＣが低レベルのとき
は、スイッチ回路ＳＷ１により内部降圧電源回路１への
電源電圧Ｖｃｃの供給を停止し、スイッチ回路ＳＷ２に
より電源電圧Ｖｃｃを内部降圧電源電圧Ｖｉｐｏの代り
に出力し、高レベルのときは、スイッチ回路ＳＳＷ１に
より内部降圧電源回路１へ電源電圧Ｖｃｃを供給してこ
れを動作させ、スイッチ回路ＳＷ２により内部降圧電源
回路１からの内部降圧電源電圧Ｖｉｐｏを出力する。When the control signal SC is at a low level, the switch circuit SW1 stops the supply of the power supply voltage Vcc to the internal step-down power supply circuit 1, and the switch circuit SW2 replaces the power supply voltage Vcc with the internal step-down power supply voltage Vipo. When it is at a high level, the switch circuit SSW1 supplies the power supply voltage Vcc to the internal step-down power supply circuit 1 to operate it, and the switch circuit SW2 outputs the internal step-down power supply voltage Vipo from the internal step-down power supply circuit 1. To do.
【００１５】すなわち、電源電圧Ｖｃｃが内部基準電圧
Ｖｉｒｒより高く内部降圧電源電圧Ｖｉｐｏが安定した
一定電圧であるときはこの内部降圧電源電圧Ｖｉｐｏを
出力し、電源電圧Ｖｃｃが内部基準電圧Ｖｉｒｒより低
く内部降圧電源電圧Ｖｉｐｏが不安定になる領域のとき
は、最終的な内部降圧電源電圧Ｖｉｐとして電源電圧Ｖ
ｃｃをそのまま出力すると共に、内部降圧電源回路１へ
の電源電圧Ｖｃｃの供給も停止するようになっている。That is, when the power supply voltage Vcc is higher than the internal reference voltage Virr and the internal step-down power supply voltage Vipo is a stable constant voltage, the internal step-down power supply voltage Vipo is output, and the power supply voltage Vcc is lower than the internal reference voltage Virr. When the step-down power supply voltage Vipo becomes unstable, the power supply voltage Vip is set as the final internal step-down power supply voltage Vip.
While outputting cc as it is, the supply of the power supply voltage Vcc to the internal step-down power supply circuit 1 is also stopped.
【００１６】従って、電源電圧Ｖｃｃが低く、安定した
一定電圧の内部降圧電源電圧が得られないときには、電
源電圧Ｖｃｃをそのまま出力して後段の回路の動作を安
定化し、また、内部降圧電源回路１への電源供給を停止
して消費電力の削減をはかることができる。Therefore, when the power supply voltage Vcc is low and a stable and constant internal step-down power supply voltage cannot be obtained, the power supply voltage Vcc is output as it is to stabilize the operation of the subsequent circuit, and the internal step-down power supply circuit 1 is also provided. It is possible to reduce power consumption by stopping the power supply to the.
【００１７】図３は本発明の第２の実施例を示す回路図
である。FIG. 3 is a circuit diagram showing a second embodiment of the present invention.
【００１８】この実施例は、電源電圧判定回路３に入力
される電圧の調整手段を独立した基準電圧調整回路６と
し、電源電圧分圧回路２ａを固定の分圧電圧Ｖｐｄｆを
出力する回路とし、基準電圧調整回路６により調整され
た基準電圧（Ｖｒ）と固定の分圧電圧Ｖｐｄｆとを電源
電圧判定回路３で比較，判定する構成となっている。In this embodiment, the adjusting means for adjusting the voltage input to the power supply voltage judging circuit 3 is an independent reference voltage adjusting circuit 6, and the power supply voltage dividing circuit 2a is a circuit for outputting a fixed divided voltage Vpdf. The reference voltage (Vr) adjusted by the reference voltage adjustment circuit 6 and the fixed divided voltage Vpdf are compared and determined by the power supply voltage determination circuit 3.
【００１９】この実施例の基本的な動作及び効果は第１
の実施例と同一であるのでこれ以上の説明は省略する。The basic operation and effect of this embodiment are as follows:
Since it is the same as the embodiment described above, further description will be omitted.
【００２０】[0020]
【発明の効果】以上説明したように本発明は、電源電圧
が低く安定した一定電圧の内部降圧電源電圧が得られな
い領域では、電源電圧をそのまま最終的な内部降圧電源
電圧として出力すると共に、内部降圧電源回路への電源
電圧の供給を停止する構成としたので、電源電圧が低い
ときでも後段回路の動作を安定化し、かつ消費電力の削
減をはかることができる効果がある。As described above, according to the present invention, in a region where the power supply voltage is low and a stable and constant internal step-down power supply voltage cannot be obtained, the power supply voltage is directly output as the final internal step-down power supply voltage. Since the configuration is such that the supply of the power supply voltage to the internal step-down power supply circuit is stopped, it is possible to stabilize the operation of the latter-stage circuit and reduce the power consumption even when the power supply voltage is low.
【図１】本発明の第１の実施例を示す回路図である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
【図２】図１に示された実施例の動作を説明するための
各部電圧のレベル関係を示す特性図である。FIG. 2 is a characteristic diagram showing a level relationship of voltage of each part for explaining the operation of the embodiment shown in FIG.
【図３】本発明の第２の実施例を示す回路図である。FIG. 3 is a circuit diagram showing a second embodiment of the present invention.
【図４】従来の半導体集積装置の一例を示す回路図であ
る。FIG. 4 is a circuit diagram showing an example of a conventional semiconductor integrated device.
【図５】図４に示された半導体集積装置の動作を説明す
るための各部電圧のレベル関係を示す特性図である。FIG. 5 is a characteristic diagram showing a level relationship of voltages of respective parts for explaining the operation of the semiconductor integrated device shown in FIG.
１ 内部降圧電源回路 ２，２ａ 電源電圧分圧回路 ３ 電源電圧判定回路 ４ 切換制御回路 ５ 切換回路 ６ 基準電圧調整回路 １１ 基準電圧発生回路 １２ 調整回路 １３ 出力回路 1 internal step-down power supply circuit 2, 2a power supply voltage dividing circuit 3 power supply voltage determination circuit 4 switching control circuit 5 switching circuit 6 reference voltage adjusting circuit 11 reference voltage generating circuit 12 adjusting circuit 13 output circuit
Claims (3)
圧が内部基準電圧より高いときこの内部基準電圧と対応
した一定の電圧の内部降圧電源電圧を発生する内部降圧
電源回路と、前記外部からの電源電圧を分圧する電源電
圧分圧回路と、この電源電圧分圧回路の出力電圧のレベ
ルを調整する調整手段と、この調整手段により調整され
た前記電源電圧分圧回路の出力電圧を基準電圧と比較し
前記外部からの電源電圧が前記内部基準電圧に達したと
きレベル変化する電源電圧判定信号を出力する電源電圧
判定回路と、前記電源電圧判定信号のレベル変化に応答
して、前記外部からの電源電圧が前記内部基準電圧より
高いとき前記内部降圧電源電圧を出力し、低いとき前記
外部からの電源電圧を出力すると共に前記内部降圧電源
回路への外部からの電源電圧の供給を停止する切換回路
とを有することを特徴とする半導体集積装置。1. An internal step-down power supply circuit for receiving an external power supply voltage and generating an internal step-down power supply voltage of a constant voltage corresponding to the internal reference voltage when the power supply voltage is higher than an internal reference voltage; A power supply voltage dividing circuit for dividing the power supply voltage of the device, adjusting means for adjusting the level of the output voltage of the power supply voltage dividing circuit, and the output voltage of the power supply voltage dividing circuit adjusted by the adjusting means for the reference voltage. And a power supply voltage determination circuit that outputs a power supply voltage determination signal that changes in level when the power supply voltage from the outside reaches the internal reference voltage, and from the outside in response to a level change in the power supply voltage determination signal. The internal step-down power supply voltage is output when the power supply voltage is higher than the internal reference voltage, the external power supply voltage is output when the power supply voltage is low, and the internal step-down power supply circuit receives an external power supply voltage. A semiconductor integrated device, comprising: a switching circuit for stopping the supply of a power supply voltage.
た請求項１記載の半導体集積装置。2. The semiconductor integrated device according to claim 1, wherein the adjusting means is provided in the power supply voltage dividing circuit.
回路とし、電源電圧判定回路を、電源電圧分圧回路の出
力電圧を前記調整手段により調整された基準電圧と比較
する回路とした請求項１記載の半導体集積装置。3. The adjusting means is a circuit for adjusting the level of the reference voltage, and the power supply voltage judging circuit is a circuit for comparing the output voltage of the power supply voltage dividing circuit with the reference voltage adjusted by the adjusting means. 1. The semiconductor integrated device according to 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4217575A JP2853469B2 (en) | 1992-08-17 | 1992-08-17 | Semiconductor integrated device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4217575A JP2853469B2 (en) | 1992-08-17 | 1992-08-17 | Semiconductor integrated device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0667739A true JPH0667739A (en) | 1994-03-11 |
| JP2853469B2 JP2853469B2 (en) | 1999-02-03 |
Family
ID=16706430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4217575A Expired - Lifetime JP2853469B2 (en) | 1992-08-17 | 1992-08-17 | Semiconductor integrated device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2853469B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7327277B2 (en) | 2001-08-22 | 2008-02-05 | Sony Corporation | Information transmission apparatus, information transmission method, and monitoring apparatus |
| JP2008065672A (en) * | 2006-09-08 | 2008-03-21 | Nec Electronics Corp | Power circuit |
| JP2011054175A (en) * | 2009-09-03 | 2011-03-17 | Samsung Electronics Co Ltd | Boosting circuit for wide range power supply, electronic device including the same and voltage boosting method |
-
1992
- 1992-08-17 JP JP4217575A patent/JP2853469B2/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7327277B2 (en) | 2001-08-22 | 2008-02-05 | Sony Corporation | Information transmission apparatus, information transmission method, and monitoring apparatus |
| JP2008065672A (en) * | 2006-09-08 | 2008-03-21 | Nec Electronics Corp | Power circuit |
| JP2011054175A (en) * | 2009-09-03 | 2011-03-17 | Samsung Electronics Co Ltd | Boosting circuit for wide range power supply, electronic device including the same and voltage boosting method |
| US8836683B2 (en) | 2009-09-03 | 2014-09-16 | Samsung Electronics Co., Ltd. | Boosting circuit for wide range supply voltage, electronic device including the same and voltage boosting method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2853469B2 (en) | 1999-02-03 |
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