JPH05313762A - Voltage regulator - Google Patents

Abstract

PURPOSE:To suppress the overshoot in the power-on of a voltage regulator which has a power-on/off circuit. CONSTITUTION:A signal line from the power-on/off circuit is provided with a differentiating circuit 7, and a MOS transistor added to an error amplifier 8 is turned on by the signal, which is generated in the differentiating circuit 7 at the moment of power-on, to increase the current flowing to the error amplifier 8 of the voltage regulator, and the response characteristic is improved, thereby suppressing the overshoot of the voltage regulator at the time of power-on.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage regulator formed into a CMOS monolithic IC.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG.
_The current value flowing in the error amplifier 8 composed of _{1 to} M ₅ is
When the power is OFF (the voltage of power ON / OFF terminal 2 is L
At the time of ow), the output terminal 3 of the reference voltage circuit 1 becomes Low, and thus becomes zero. Conversely, when the power is ON (power ON / O
When the voltage of the FF terminal 2 is High), a constant voltage is generated at the output terminal 3 of the reference voltage circuit 1, so that a constant current flows through the transistor M ₅ .

[0003]

However, in the case of the conventional technique, the power ON / OFF terminal 2 is changed from Low to High.
When switched to, a large overshoot (increase in the output voltage of the regulator in the steady state) is generated at the output terminal 4 of the regulator. In order to suppress this overshoot, it is necessary to increase the response speed of the error amplifier 8 composed of the transistors M _{1 to} M ₅ . When the current value of the transistor M ₅ is I ₅ and the gate capacitance of the output transistor M _{6 which} is a load of the error amplifier 8 is C, the slew rate SR which is an index showing the response speed of the error amplifier 8 is shown.
Is expressed by equation (1).

SR = I ₅ / C (1) As is clear from the equation (1), in order to increase the response speed of the error amplifier 8, I ₅ should be increased and C should be decreased. However, making C smaller means making the gate area of the output transistor M ₆ smaller, which causes a decrease in the output current of the voltage regulator, and I
Increasing the value of ₅ will increase the current consumption of the voltage regulator, and both will reduce the performance of the voltage regulator.

That is, unless the performance of the voltage regulator is deteriorated, the power ON / OFF terminal 2 is set to Lo.
There is a problem that it is not possible to suppress the overshoot of the output terminal 4 of the regulator when switching from w → High. Therefore, an object of the present invention is to solve the conventional problems as described above, and to suppress the overshoot when the power ON / OFF terminal is switched from Low to High without degrading the performance of the voltage regulator. Is.

[0006]

In order to solve the above-mentioned problems, the present invention is a voltage monolithic IC CMOS integrated circuit including an error amplifier and a power ON / OFF circuit.
In the regulator, a differentiating circuit is provided in the signal line from the power ON / OFF circuit, and a signal generated from the differentiating circuit at the moment of power ON is used to increase the current of the error amplifier, thereby the voltage at the time of power ON.・ The regulator's overshoot is suppressed and the current consumption is reduced in the steady state.

[0007]

In the voltage regulator configured as described above, only when the power is turned on, the voltage regulator
The current value of the error amplifier of the regulator increases, the overshoot at the time of power-on is suppressed, and in the steady state, the current consumption is low.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, when the power ON / OFF terminal 2 is set to High (when the power is ON), the output V _{5 of the} inverter 5 becomes Low, the transistor M ₇ is ON, the transistor M ₈ is OFF, and the output of the inverter 6 is Hig
Since it becomes h, the transistor M ₉ is turned off and the voltage regulator operates. Conversely, power ON / OFF
When the terminal 2 is set to Low (power OFF), ON / OFF of the transistors M _{7 to} M ₉ is inverted and the voltage
The regulator will stop working.

In the circuit of FIG. 1, the output terminal capacitor C ₁ of the inverter 6 which changes according to the voltage of the power ON / OFF terminal 2 is connected, and the resistor R ₃ is connected to the other end of the capacitor C ₁ and the resistor R ₃ is connected. The other end of ₃ is a transistor M ₅
The differential circuit composed of the capacitor C ₁ and the resistor R ₃ and the source / drain of the transistor M ₅ is connected to the source of the capacitor C ₁ and the resistor R ₃
A transistor M ₁₀ having a gate at the connection point is added.

[0010] Here, the output voltage V ₆ of the inverter 6 in a steady state, because it is fixed to High or Low, no current flows to the resistor R _3, the fact that no current flows through the resistor R ₃ is the gate-source voltage of the transistor M ₁₀ is zero, no current flows through the transistor M _10. That is, in the steady state, the current consumption of the voltage regulator of FIG. 1 is equal to the current consumption of the conventional voltage regulator of FIG.

As shown in FIG. 3, the power ON / OFF terminal 2
Voltage V_PWhen Low goes to High, inverter 6
Output voltage V₆Also goes from Low to High. At this time,
C Densa C₁Since the electric charge of the₁
And resistance R₃Voltage at the connection point of _CRRises and then C₁
× R₃Time constant (eg C₁= 10 pF, R₃= 10
If it is MΩ, it falls with a time constant of 0.1 msec).

This power ON / OFF terminal 2 is Low
The transistor M ₁₀ is turned on and its current I ₁₀ flows through the error amplifier 8 from the time when the voltage becomes High until the voltage V _CR decreases. The slew rate SR of the error amplifier 8 at this time is represented by the equation (2) as in the equation (1).

SR = (I ₅ + I ₁₀ ) / C (2) As is apparent from the equation (2), the slew rate is improved by the current I ₁₀ of the transistor M ₁₀ . That is, by increasing the response characteristic of the error amplifier 8 only at the moment of turning on the power, the overshoot of the voltage regulator at the time of turning on the power can be suppressed to a small level, and in the steady state, it operates with the low current consumption as before. be able to.

In FIG. 1, the resistor R ₃ and the capacitor C ₁
Although a differentiating circuit is configured with, the same effect can be obtained even if the drain of the depletion transistor is connected to the gate of M ₁₀ instead of the resistor R ₃ and the gate and the source are connected to the source of M _10. it is obvious.

[0015]

As described above, according to the present invention, the current value flowing in the error amplifier of the voltage regulator is increased only at the moment of power ON, so that the overshoot of the voltage regulator at the time of power ON is suppressed, In addition, in the steady state, there is an effect that it can be operated with the same low current consumption as the conventional one.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a voltage regulator with a power ON / OFF circuit of the present invention.

[Figure 2] Voltage with conventional power ON / OFF circuit
It is a circuit diagram of a regulator.

FIG. 3 is a time chart showing the operation of the voltage regulator of the present invention.

[Explanation of symbols]

 1 Reference voltage circuit 2 Power ON / OFF terminal 3 Reference voltage output terminal 4 Voltage regulator output terminal 5, 6 Inverter circuit 7 Differentiation circuit 8 Error amplifier

Claims (1)

[Claims] 1. An error amplifier, a reference voltage circuit connected to one input terminal of the error amplifier, and an output transistor connected between a voltage supply terminal and a voltage output terminal.
A signal from a power ON / OFF terminal is input, and a dividing resistor composed of first and second resistors which are sequentially connected to the voltage output terminal and whose connection point is connected to another input terminal of the error amplifier. A differential circuit and a MOS that is added to the error amplifier and inputs the output signal from the fine one circuit to the gate.
A voltage regulator consisting of a transistor.