JP2621140B2 - Sense amplifier circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier circuit, and more particularly to a current mirror type sense amplifier circuit for detecting and amplifying a small signal voltage of a data line in a highly integrated memory device.

[Prior art] In recent years, dynamic or static MOSRAM
(Metal Oxide Semiconductor Random Access Mem
In highly integrated memory devices such as ory), an amplifier for detecting and amplifying a small signal voltage on a data line of the memory with high speed and high sensitivity, that is, a sense amplifier circuit, is increasing in importance.

FIG. 4 is a circuit diagram of a conventional high sensitivity sense amplifier circuit of a current mirror type constituted by a CMOS (Complementary MOS) circuit system.

First, the configuration of a conventional current mirror type sense amplifier will be described with reference to FIG. In FIG.
Left N-channel MOS transistor Q _N1 and P-channel MOS
The transistor Q _P1 is the first static inverter 1
And the right N-channel MOS transistor Q _N2 and P-channel MOS transistor Q _P2 form a second static inverter 2. The P-channel MOS transistors Q _P1 and Q _{P2 form} a current mirror (load side). MOS transistor to the gate electrodes of the MOS transistor Q _N2 of Q _N1, respectively, and the input data D _IN ▲ ▼ and is applied in a complementary relationship with each other.
Further, the MO constituting the first static inverter 1
The S transistor Q _P1 and the MOS transistor Q _N1 are connected to the ground potential and V _CC via an N-channel MOS transistor Q _N3.
(= 5.0 V), and the MOS transistor Q _P2 and the MOS transistor Q _N2 constituting the second static inverter 2 are also connected to the ground potential and V _CC (= 5.0 V) via the MOS transistor Q _N3. Is connected between. This M
OS transistor Q _N3 is turned on in response to a sense start signal phi _S for a high level applied from the outside, for connecting the first static inverter 1 and a second static inverter 2 to the ground potential. Moreover, it applied to the gate electrode of the first output voltage V ₁ of the static inverter 1 as the reference potential second static inverter 2 of the MOS transistor Q _P2. Then, this reference potential V ₁ and ▲
▼ voltage difference between the output from the sense output D _OUT as the second static inverter 2.

Next, FIG. 5 is a diagram showing load characteristics and driver characteristics of each inverter stage constituting the conventional sense amplifier circuit shown in FIG. FIG. 6 is a diagram showing the input / output characteristics of the conventional sense amplifier circuit shown in FIG. 4, and FIG. 7 is a diagram showing the total current consumption of the sense amplifier circuit.

Next, referring to FIG. 5, FIG. 6 and FIG.
The operation of the illustrated sense amplifier circuit will be described. In the sense amplifier circuit of FIG. 4, first, at the detection start of the input data, the sense start signal phi _S goes high level
The MOS transistor _QN3 conducts, the first static inverter 1 is connected in series between V _CC and ground potential,
The second static inverter 2 will be connected in series between V _CC and ground potential. And the gate electrode of the MOS transistor Q _N1 of the static inverter 1 is inputted one of the input data D _IN, and the other input data ▲ ▼ is input to the gate electrode of the MOS transistor Q _N2 static inverter 2. Here, since the MOS transistor Q _P1 operates in the saturation region, the load curve of the first static inverter 1 including the MOS transistors Q _P1 and Q _N1 is as shown by a curve a in FIG. Here, the driver characteristic of the MOS transistor Q _N1 of the first static inverter 1 is as shown by a curve b in FIG. 5, and these characteristic curves a and b intersect at V ₁ = A. Further, since the gate voltage of the MOS transistor Q _P2 of the second static inverter 2 is the same as the gate voltage of Q _P1 , A = V ₁ , the load curve of the second static inverter 2 including the MOS transistors Q _P2 and Q _N2 is , And the curve c in FIG. When D _IN = ▲, the driver characteristic of the MOS transistor Q _N2 becomes a curve b as in the case of Q _N1 , and therefore, the characteristic curves b and c intersect at D _OUT = A. However, curves b and c
And in the pentode region, the driver characteristic curve b of the MOS transistor _QN2 changes like the curve d or e in FIG. The intersection of the static inverter 2 with the load curve c also greatly varies from D _OUT = B to D _OUT = C in FIG.
Therefore, as shown in input-output characteristic diagram of FIG. 6, a first static inverter 1 the reference voltage such that the second logical threshold value of the static inverter 2 is D _IN
V ₁ can be said that has been adjusted. As shown in FIG. 6, when the input voltage D _IN is lower, the slope of the input / output characteristic curve is larger, so that the sensitivity of the sense amplifier circuit is better. Further, as shown in FIG. Low current consumption. On the other hand, when the input voltages D _IN and ▲ ▼ are both relatively high, that is, in the range of 2 V to 3 V, as shown in FIG. 6, the slope of the input / output characteristic curve, that is, the sensitivity of the sense amplifier circuit rapidly decreases. In addition, as shown in FIG. 7, the total current consumption of the circuit is significantly increased. This phenomenon is caused by the first static inverter 1 composed of MOS transistors Q _P1 and Q _{N1 in} the region where D _IN , ▲ ▼ is in the range of 2 V to 3 V
Current mirror constant current is increased, and lowered to the ground potential by the MOS transistor Q _N2 becomes strong in the MOS transistor Q _P2 and Q _N2 second static inverter 2 consisting of, a MOS transistor Q _P1 and Q _P2 flowing through the Deviates from the operation in the saturation region.

[Problems to be Solved by the Invention] Since the conventional sense amplifier circuit is configured as described above, high-sensitivity detection is possible under a low bias condition. When the level of the voltage D _IN , ▲ ▼ becomes high, there is a problem that the sensitivity of the sense amplifier is remarkably deteriorated and the power consumption is increased, so that the input voltage range in which the operation is performed well is narrow.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a sense amplifier circuit having good sensitivity over a wide input voltage range and low power consumption.

[Means for Solving the Problems] The sense amplifier circuit according to the present invention includes a first load transistor connected between a first potential node to which a first potential is applied and a first potential node. A second load transistor connected between the first potential node and the second node and forming a current mirror circuit with the first load transistor; a second load transistor to which a second potential different from the first potential is applied; A first input transistor connected between the second potential node and the third node and having a first input potential input to the control electrode; and a first input transistor connected between the second potential node and the fourth node. A second input transistor to which a second input potential is input to the control electrode, a MOS transistor connected between the first node and the third node, and having a gate applied with a constant potential, First load transistor And the first
And a first current limiting transistor for limiting the current flowing between the first node and the third node, and having a conductance smaller than that of the input transistor of A MOS transistor connected to the gate and having a constant potential applied to the gate,
And a second current limiting transistor that has a smaller conductance than the load transistor and the second input transistor and limits the current flowing between the second node and the fourth node. An output potential is output from a node between the input transistors.

[Operation] In the sense amplifier circuit according to the present invention, the first and second current limiting transistors are provided so that the first node and the third node are connected to each other.
And the current between the second node and the fourth node, and the current flowing through the first and second load transistors in the current mirror circuit. It is possible to keep the operating point within the saturation region and prevent an increase in power consumption.

FIG. 1 is a circuit diagram showing a sense amplifier circuit according to an embodiment of the present invention.

First, the configuration of an embodiment of the present invention will be described with reference to FIG. In Figure 1, MOS transistor Q _N3 of the N-channel in response to a sense start signal phi _S for a high level applied from the outside in the same manner as Q _N3 of FIG. 1 conducts, left static inverter 3 and the right Is connected between V _CC and the ground potential. The static inverter 3 on the left side includes a P-channel MOS transistor Q _P1 provided on the V _CC side and an N-channel MOS transistor Q _P provided on the ground potential side, similarly to the static inverter 1 in the conventional sense amplifier circuit of FIG. _N1 and these two M
It differs from the conventional sense amplifier circuit of FIG. 4 in that a P-channel MOS transistor _QP3 is newly inserted between the OS transistors in series. On the other hand, the right side of the static inverter 4, like the static inverter 2 in the conventional sense amplifier circuit of FIG. 4, a P-channel MOS transistor Q _P2 provided on the V _CC side, N-channel provided on the ground potential side MOS transistor _QN2, and is different from the conventional sense amplifier circuit of FIG. 4 in that a P-channel MOS transistor _QP4 is newly inserted in series between these two MOS transistors. . The gate electrode of the MOS transistor Q _P3 and Q _P4 added these newly, reference potential becomes Vref (3.0~4.0V) is applied. The P-channel MOS transistors Q _P1 and Q _{P2 form} a current mirror (load side). Input data D _IN and ▲ ▼ which are complementary to each other are applied to the gate electrode of the MOS transistor Q _{N1 and} the gate electrode of the MOS transistor Q _N2 , respectively, as in the sense amplifier circuit of FIG. , the output voltage V ₁ of the static inverter 3 is supplied to the gate electrode of the MOS transistor Q _P2 static inverter 4 as the reference potential, and a static inverter voltage difference between the reference potential V ₁ with ▲ ▼ and as a sense output D _OUT 4 is output.

Next, FIG. 2 is a diagram showing input / output characteristics of the sense amplifier circuit according to one embodiment of the present invention shown in FIG.
FIG. 3 shows the total current consumption of the sense amplifier circuit.

Next, the operation of the embodiment of the present invention shown in FIG. 1 will be described with reference to FIG. 2 and FIG. First,
At the detection start of the input data, MOS transistor Q _N3 conducts sense start signal phi _S goes high level, static inverter 3 on the left is connected between the V _CC and the ground potential, the right of the static inverter 4 It will be connected between V _CC and ground potential. Then, the gate electrode of the MOS transistor Q _N1 of the static inverter 3 is supplied with the first input data D _IN, and the other input data ▲ ▼ is applied to the gate electrode of the MOS transistor Q _N2 static inverter 4. Where D _IN ,
When both ▲ and ▼ are at relatively low voltage levels, as in the case of the conventional sense amplifier circuit shown in FIGS. 4 to 7, the current mirror including the MOS transistors Q _P1 and Q _P2 becomes Operates in the saturation region. Therefore, as is clear from FIGS. 2 and 3, when the level of the input data D _IN , ▲ ▼ is low, the slope of the input / output characteristics is large, and the sense amplifier sensitivity is good. The flowing steady current is also small, and therefore the total current consumption of the circuit is also small. On the other hand, D _IN , ▲
When both ▼ s are at relatively high voltage levels, that is, in the range of 2 V to 3 V, the conventional sense amplifier circuit shown in FIG. 4 uses the conventional sense amplifier circuit shown in FIG. 2 or FIG. The sense amplifier sensitivity was sharply reduced, and at the same time the total current consumption was significantly increased. However, according to the embodiment shown in FIG. 1, the gate electrode of the MOS transistor Q _P3 and Q _P4 that are newly added, Vref = 3.0~4.0V an intermediate potential between V _CC and the ground potential is applied Therefore, the MOS transistors Q _P3 and Q _P4 operate in the saturation region even under the input condition where a large power supply current flows conventionally, that is, even when D _IN and ▼ are both at relatively high levels. Therefore, these MOS transistors Q
_P3 and _QP4 function as current limiting elements that keep the current flowing through themselves at a substantially constant value. That is,
Conductance of the MOS transistor Q _P3 is smaller than the conductance of the conductance and MOS transistor Q _N1 of the MOS transistor Q _P1, the conductance of the MOS transistor Q conductance of _P4 the transistor Q _P2 and MOS
Since it is smaller than the conductance of transistor Q _N2 ,
Even if the transistor Q _P1 and the MOS transistor Q _N1 can flow more current, the current is limited by the MOS transistor Q _P3 , and similarly, even if the MOS transistor Q _P2 and the MOS transistor Q _N2 can flow more current, the MOS transistor
The current is limited by Q _P4 . by this,
Irrespective of the level of the input data level, the current flowing through the circuit is kept below a certain value, and it is possible to suppress an increase in the total current consumption.

In FIG. 1, when the threshold voltage of the MOS transistor _QP3 is V _TH , the reference potential V ₁ is equal to the input data.
Even if the level of D _IN and ▲ ▼ is high, it does not _drop below Vref + V _TH . Therefore, the MOS transistors Q _P1 and Q _P2
The current mirror consisting of is hardly deviated from the saturation region even when the input condition becomes high, and therefore, as shown in FIG. 2, the input / output characteristics are rapidly deteriorated and the sense amplifier sensitivity is lowered. There is no.

In the above-described embodiment, the case where the load side of the current mirror is constituted by P-channel MOS transistors Q _P1 and Q _P2 has been described. However, the same effect can be obtained when these are constituted by N-channel MOS transistors. Obtainable. In this case, the current limiting element must be an N-channel MOS transistor.

[Effect of the Invention] As described above, according to the present invention, by providing the first and second current limiting transistors between the current mirror circuit and the first and second input transistors,
Good input / output characteristics, that is, sense amplifier sensitivity can be obtained over a wide range of the levels of the first and second input potentials, and the total power consumption of the circuit can be obtained even for the high-level first and second input potentials. Can be suppressed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a sense amplifier circuit according to one embodiment of the present invention. FIG. 2 is a diagram showing input / output characteristics of the sense amplifier circuit shown in FIG. FIG. 3 is a diagram showing the total current consumption of the sense amplifier circuit shown in FIG. FIG. 4 is a circuit diagram showing a conventional sense amplifier circuit. FIG. 5 is a diagram showing load characteristics and driver characteristics of the conventional sense amplifier circuit shown in FIG. FIG. 6 is a diagram showing input / output characteristics of the conventional sense amplifier circuit shown in FIG. FIG. 7 is a diagram showing the total current consumption of the conventional sense amplifier circuit shown in FIG. In the figure, 1, 2, 3, and 4 are static inverters, and Q _N1 and Q
_N2 and _QN3 are N-channel MOS transistors, _QP1 , _QP2 , _QP3 and _QP4
Denotes a P-channel MOS transistor.

Claims (3)

(57) [Claims] A first load transistor connected between a first potential node to which a first potential is applied and a first node; and a first load transistor connected between the first potential node and a second node. A second load transistor connected to form a current mirror circuit with the first load transistor; a second load transistor supplied with a second potential different from the first potential
A first input transistor connected between the potential node and a third node, and a first input potential is input to the control electrode, connected between the second potential node and a fourth node A second input transistor having a second input potential input to the control electrode, a second input transistor connected between the first node and the third node, and a MOS transistor having a gate applied with a constant potential. A first current limiting transistor having a conductance smaller than that of the first load transistor and the first input transistor, and limiting a current flowing between the first node and the third node; and A MOS transistor connected between the second node and the fourth node and having a gate applied with a constant potential, wherein the second load transistor and the second A second current limiting transistor having a conductance smaller than that of the force transistor and limiting a current flowing between the second node and the fourth node, the second load transistor and the second input; A sense amplifier circuit that outputs an output potential from a node between the transistor and a transistor. 2. The first and second current limiting transistors are connected to a second potential node via a disabling transistor for disabling a sense amplifier circuit to reduce current consumption to zero. 2. The sense amplifier circuit according to claim 1. 3. The method according to claim 1, wherein the constant potential is a potential between the first potential and the second potential.
The sense amplifier circuit described in the paragraph.