JPH0559520B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A test mode determination circuit characterized by using a P channel transistor and an N channel transistor.

[Industrial application field]

The present invention relates to a voltage determination circuit, and particularly to a test mode determination circuit for a semiconductor memory device.

[Conventional technology]

1M DRAM has a test terminal, and when a voltage _VTE higher than the power supply Vcc is applied to this test terminal, the chip goes into test mode, which can shorten test time. In other words, once the DRAM chip has been manufactured, it is tested for writing/reading, etc.
Checks whether it is a good product or not, but writing/reading is 1
Since data is processed bit by bit, it takes time for large volumes. Therefore, a test mode is provided in which simultaneous writing/reading of multiple bits is performed in an attempt to shorten the time. This type of DRAM is provided with a circuit that determines whether the voltage at the test terminal is sufficient to enter the test mode (whether the voltage is higher than Vcc by a predetermined value or more). An example of a conventional circuit of this type is shown in FIG.

In this figure, 10 is a test terminal, Tr ₁ to Trm are N-channel MOS transistors whose gates are connected to the drains, Tr _L is N-channel MOS transistors whose gates are connected to the power supply Vcc, and these transistors Tr ₁ to Trm, Tr _L are connected in series to test terminal 1.
0 and ground Vss, and connect the transistor Trm
The input end of an inverter 12 is connected to the connection point P between and Tr _L , and the output of the inverter is used as the judgment output.
When the test voltage V _TE is not applied to the test terminal 10, the transistors Tr ₁ to Trm are off and the transistor Tr _L is on, so the potential at point P is L (low) level and the output of the inverter 12 is H (high).
level, which indicates normal mode. Test voltage V _TE higher than power supply Vcc at terminal 10
When is applied, transistors Tr ₁ to Trm turn on, but each causes a voltage drop by the threshold value Vth, so the potential at point P becomes V _TE −mVth, and the inverter 12 determines this to be an H level (its (Determine the number of transistors Tr ₁ to Trm and the H/L determination threshold of the inverter as follows) Set the output to L level. This indicates test mode. Note that when V _TE is applied to terminal 10, the transistor Tr _L
is on, but gm of Tr _L is small, so node P
The potential of becomes V _TE −mVth. The transistors Tr ₁ to Trm connected as shown are equivalent to diodes and function as constant voltage (mVth) drop elements.

[Problem that the invention seeks to solve]

To determine whether the voltage V _TE applied to the test terminal is sufficient to enter the test mode, the voltage V _TE must be higher than the power supply Vcc by a margin α, and the α As shown in Figure 3, Vcc
It is desirable that the value remain constant even if the value changes. However, in the circuit of FIG. 2, as shown in FIG. 4, α tends to become large in a range where Vcc is a low voltage, and the requirement that α=constant is not satisfied. During normal operation, the power supply Vcc is
Although it is kept constant at 5V and the allowable fluctuation range is small, Vcc may change significantly in test mode. It is desirable that α remains constant even in this state.

Furthermore, in the circuit of Fig. 2, the transistors Tr ₁ to Trm
may consist of 10 or more depending on the value of Vth, requiring a large area. Also, when V _TE is at a potential that is not in test mode, the current consumption of this circuit and the current flowing to the test terminal become a problem. In other words, it is unstable in a floating state where the test voltage V _TE is not applied to terminal 10, and if a noise voltage enters terminal 10 for some reason, current will flow from that terminal, and in some cases, the inverter output will be reversed. Sometimes.

The present invention aims to provide a test mode determination circuit that has a certain margin α with respect to the power supply voltage Vcc, is less likely to malfunction, and consumes less current.

[Means for solving problems]

The semiconductor memory device of the present invention includes constant voltage drop elements Tr ₁ to Trn and P channel transistors Trp and N
The channel transistors Tr _L are connected in series between the input terminal 10 to which the voltage to be detected is applied and the ground (Vss), and the gates of the P channel and N channel transistors are connected to the power supply (Vcc).
Further, a unidirectional conduction element Tr _N is connected between the connection point (Q) between the constant voltage drop element and the P-channel transistor and the power supply (Vcc), and the P-channel transistor is formed at the connection point (Q). Connect to the well,
The potential of the connection point (Q) is set to the value (Vcc - Vth) obtained by subtracting the threshold voltage (Vth) from the power supply voltage (Vcc), and the voltage (V _TE ) applied to the input terminal is equal to the power supply voltage ( Vcc), the voltage is changed according to the value, and the connection point (P) of the P channel transistor and the N channel transistor is connected to the inverter 12, and the voltage judgment output is taken out from the inverter. It is characterized by

[Effect]

In this test mode determination circuit, the test voltage is
Even if the voltage of the power supply Vcc changes, it can always be set to a constant value higher than the power supply Vcc, and it also prevents malfunctions and
It is possible to output a reliable test mode judgment without fear of latch-up.

〔Example〕

FIG. 1 shows an embodiment of the present invention. Tr ₁ to Trn are n N channels with gates connected to drains.
MOS transistor, Trp is a P-channel MOS transistor whose gate is connected to the power supply Vcc, Tr _L is an N-channel MOS transistor whose gate is connected to the power supply Vcc, and these are connected in series to the test terminal 1.
Connected between 0 and ground Vss. Tr _N is an N-channel MOS transistor whose gate and drain are connected to the power supply Vcc (in this example, it works as a unidirectional conduction element), and whose source is the transistor Trn
and Trp are connected to the connection point Q. The N-channel transistors Tr ₁ to Trn, etc. are formed on a P-type semiconductor substrate, and the P-channel transistor Trp is formed in an N-type well formed on the substrate, and the well is connected to the connection point Q. and transistor
The input terminal of an inverter 12 is connected to the connection point Q between Trp and Tr _L , and the output of the inverter becomes the output of this circuit.

When the test voltage V _TE is not applied to the test terminal 10, the transistor Tr _L is on, Trp is off, the point P is at the L level, and therefore the output is at the H level, which indicates the normal mode. Further, in this state, the current i _T flowing from the test terminal 10 is 0, and the current i _N flowing into the node Q through the transistor Tr _N is also 0. When V _TE is increased with Vcc constant,
At the point when V _TE −nVth=Vcc+Vthp, that is, the potential of the Q point is lower than the gate voltage Vcc of the transistor.
When the threshold voltage Vthp of Trp becomes higher, the transistor Trp is turned on, the node P becomes H level, and the output becomes L level. This indicates test mode. The current i _T flowing at this time is limited by the transistor Tr _L.

In this circuit, α=nVth+Vthp is constant,
The ideal state shown in FIG. 3 is obtained. Also, even if the test terminal 10 is floating, the transistor
Node Q is maintained at Vcc-Vth by Tr _N , and transistor Trp is off, so no malfunction occurs. In addition, the well that forms the P-channel transistor Trp is connected to the node Q and has the same potential as the source of Trp, thereby avoiding current outflow from the source of Trp to the well and latch-up that occurs when the Q point potential rises above Vcc. be able to.

FIG. 5 shows the characteristics of Vcc versus _VTE and _iT in the test mode. Figure 6 also shows V _TE with Vcc constant.
The potentials and outputs of nodes P and Q are shown when the voltage is increased. The lower limit of the potential of node Q is Vcc−Vth
When V _TE increases beyond Vcc-Vth+α'(α'=nVth), the potential at node Q increases together with V _TE . Then, when the potential at the Q point exceeds Vcc+Vthp, the transistor Trp turns on, and the node P goes high.
The level and output become L level.

〔Effect of the invention〕

As explained above, according to the present invention, the test voltage can always be set to a higher value by a certain value even if the voltage of the power supply Vcc changes, and it is possible to provide a reliable test mode judgment output without fear of malfunction or latch-up. We can provide circuits that can generate

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional example, and FIGS. 3 to 6 are characteristic diagrams for explaining operation. In Figure 1, Tr ₁ to Trn are constant voltage drop elements, Trp
is a P-channel transistor, Tr _L is an N-channel transistor, and Tr _N is a unidirectional conduction element.

Claims (1)

[Claims] 1 Constant voltage drop elements Tr ₁ to Trn, P channel transistor Trp, and N channel transistor Tr _L
are connected in series between the input terminal 10 to which the voltage to be detected is applied and the ground (Vss), the gates of the P channel and N channel transistors are connected to the power supply (Vcc), and further connected to the constant voltage drop element and the P channel. A unidirectional conduction element Tr _N is connected between the connection point (Q) with the channel transistor and the power supply (Vcc), and the connection point (Q) is connected to the well where the P channel transistor is formed. When the potential of the connection point (Q) is set to the value (Vcc - Vth) obtained by subtracting the threshold voltage (Vth) from the power supply voltage (Vcc), the voltage (V _TE ) applied to the input terminal is equal to )
When the voltage exceeds the value, the voltage is changed according to the value, and a voltage judgment output is obtained from the inverter by connecting an inverter 12 at the connection point (P) between the P channel transistor and the N channel transistor. voltage determination circuit.