JP2944337B2 - Level conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit which takes in a digital signal and converts a voltage corresponding to a binary value of the signal into a value suitable for a circuit arranged at a subsequent stage.

[0002]

2. Description of the Related Art In an electronic apparatus which processes a digital signal output from a digital circuit by giving it to an analog circuit,
Generally, a level conversion circuit is used which converts a voltage corresponding to the binary value of the digital signal into a value suitable for an operating point of an analog circuit, a level tiregram, and other operating conditions.

FIG. 5 is a diagram showing a configuration example of a conventional level conversion circuit. In the figure, a digital signal is given to a level conversion circuit 51, and an output thereof is connected to a load 53 via a differential amplifier 52 which is an analog circuit.

In the level conversion circuit 51, a digital signal is applied to the gate of the FET 54, and the drain is grounded. The source of the FET 54 is connected to the first DC power supply line via the constant current source 55 and to the input of the differential amplifier 52.

In the differential amplifier 52, a level conversion circuit 51
Output is connected to the gate of FET 56 _1, its drain connected to one terminal of the resistor 57 ₁ and the load 53. FET56 given the _second gate reference voltage V _ref
It is given, and its drain is connected to the other terminal of one terminal and the load 53 of the resistor 57 _2. FET56
_1, 56 ₂ of the source are both grounded via a constant current source 58, the other terminal of the resistor 57 _1, 57 ₂ is connected to a second DC power supply line.

In the level conversion circuit having such a configuration, the DC voltage V _DD1 supplied from the first DC power supply line has a value suitable for the operating point of the differential amplifier 52 and the waveform of the signal to be obtained at the output terminal thereof. It is set in advance. The FET 54 and the constant current source 55 form a source follower circuit, and convert two values which the input digital signal can take into 0 volt and V _DD1 volt, respectively, and output them.

In the differential amplifier 52, FETs 56 ₁ and 56
₂ amplifies the difference between the instantaneous value of the digital signal thus converted and the above-described reference voltage _Vref, and amplifies the load 5
Give to 3.

[0008]

By the way, in such a conventional level conversion circuit, the value of the current supplied by the constant current source 55 generally depends on the demand for lower power consumption of the equipment equipped with such a circuit. Was set to a small value to accommodate. However, for example, when the bit rate of the digital signal to be inputted when 20~150Mbps and high, are formed by the capacitance and stray capacitance included in FET54,56 ₁ of parameters for the period of the signal constant Has a value that is not negligible, and as shown in FIG. 6, the waveform of the signal supplied to the differential amplifier 52 is deteriorated because the rise time and the fall time are large. As a method for solving such a problem, the above-described current value is increased (the level conversion circuit 5).
1 is set to be small) or the input impedance of the differential amplifier 52 is set to be small. However, these methods are applied because the above-mentioned requirement of low power consumption cannot be satisfied together. could not.

An object of the present invention is to provide a level conversion circuit capable of faithfully responding to a high-speed digital signal while suppressing power consumption.

[0010]

FIG. 1 is a block diagram showing the principle of the present invention. The present invention provides a voltage dividing means 11 for dividing a constant reference voltage in one of two predetermined voltage dividing ratios by a combination of resistance elements, and a non-inductive and non-capacitive type for a binary input signal. A voltage dividing ratio variable means for setting one corresponding to the instantaneous value of the signal to the voltage dividing means 11 and converting the voltage corresponding to the two values into a desired value through the switching element regarded as 13 is provided.

[0011]

In the level conversion circuit according to the present invention, the voltage dividing means 11 divides a constant reference voltage by the voltage dividing means 11 according to the voltage dividing ratio switched and set according to the instantaneous value of the input signal. The binary voltage level of the input signal is converted to a desired value.

In the voltage dividing means 11, the above-mentioned voltage dividing ratio is set by a combination of the resistance elements, and in the voltage dividing ratio varying means 13, a switching element which is regarded as non-inductive and non-capacitive with respect to the frequency component of the input signal. As a result, the above-described partial pressure ratio is switched, so that the transient response accompanying the switching quickly converges. Further, the resistance value of the above-described resistance element can be set to a large value as long as an error due to the input impedance of a circuit arranged at a subsequent stage is allowed.

Therefore, a level conversion circuit which responds to a high-speed input signal while suppressing power consumption is realized.

[0014]

FIG. 2 is a diagram showing an embodiment of the present invention.
In the figure, the gates of FET21 and FET22 are
Is provided with a digital signal. Source of FET21
Is connected to the first DC power supply line, and the source of the FET 22 is
Grounded. The first DC power line is individually
23 constituting a constant current source by current₁, 23_Two, 24
₁, 24_TwoGrounded. FET23 ₁And FET2
3_TwoIs connected to the drain of the FET 21 and
ET23_TwoAnd FET24₁Is connected to the differential amplifier 52
Of the FET 24₁And FET24_TwoContact with
The connection point is connected to the drain of the FET 22.

The function and configuration shown in FIG.
The same items are indicated by the same reference numbers, and
Here, the description is omitted. In addition, this embodiment and FIG.
For the correspondence with the block diagram, see FET23 ₁,
23_Two, 24₁, 24_TwoCorresponds to the voltage dividing means 11 and the FET
Reference numerals 21 and 22 correspond to the partial pressure ratio varying means 13.

Hereinafter, the operation of this embodiment will be described. FET
P-channel elements are used for 21, 23 ₁ and 23 ₂ in accordance with the direction of current passing therethrough.
4 _1, 24 ₂ elements of the N-channel in the same manner as in is used. Therefore, these FETs form a voltage dividing circuit according to the source-drain voltage V _DSS in the gate cutoff current described above.

On the other hand, when the logical value of the digital signal input to the level conversion circuit changes from the low level to the high level, the FET 22 is quickly turned on and the FE is turned on.
Since T21 will quickly off state, between the FET 24 ₂ of the drain-source is a steady state which is substantially short-circuited by the FET 22. That is, FET 24 ₁ and FET 2
4 ₂ and the connecting point because it is grounded through the FET22 of low impedance, the voltage level V _H of the signal applied to the differential amplifier 52, first in FET 23 _1, 23 _2, 24 voltage divider _{circuit 1} is formed It is given as a value obtained by dividing the DC voltage V _DD1 supplied from one DC power supply line, and corresponds to the equivalent resistance values R ₁ , R ₂ , and R _{3 of} these FETs.

[0018]

(Equation 1)

It is given by the following equation. Further, in a voltage dividing circuit formed in such a state, an FET forming the circuit is used.
Since the currents defined by the gate cutoff currents of 23 ₁ , 23 ₂ , and 24 ₁ flow, useless power consumption is regulated.

Also, when the logical value of the digital signal is high level,
When the level changes from low to low, the FET 21 is turned on.
And the FET 22 is turned off.
23 ₁And FET23_TwoConnection point with low impedance
Connected to the first DC power supply line via the FET 21
The crab enters a steady state. Therefore, in such a state
Is the voltage level V of the signal applied to the differential amplifier 52._L
Is FET23_Two, 24₁, 24_TwoIn the voltage divider circuit formed by
DC voltage V supplied from the first DC power supply line_DD1The partial pressure
The value of the equivalent resistance R_Two, R_ThreeYou
And FET24_TwoOf the equivalent resistance R_FourAgainst

[0021]

(Equation 2)

It is given by the following equation. Further, in a voltage dividing circuit formed in such a state, an FET forming the circuit is used.
Since 23 _2, 24 _1, 24 ₂ of the current defined by the gate blocking current flows, the wasteful power consumption is restricted.

Therefore, according to the present embodiment, a power level can be reduced and a level conversion circuit faithfully responding to a high-speed digital signal can be realized as shown in FIG. FIG. 4 is a diagram showing another embodiment of the present invention.

In the figure, components having the same functions and configurations as those shown in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted here. The difference between the present embodiment and the embodiment shown in FIG. 2 is that the FETs 21 and 22 switch the voltage dividing circuit to the FET 24 _1.
Was removed, lies in giving an output signal to the differential amplifier 52 from the connection point of the FET 23 ₂ and FET 24 _1.

In this embodiment, an FET 42 for interrupting the drive current of the laser diode 41 is connected to the subsequent stage of the level conversion circuit having such a configuration. In this embodiment, when the level of the digital signal is low,
In order to set the voltage of the signal to be applied to the ET 42 to a value smaller than that of the embodiment shown in FIG. 2, a voltage dividing circuit whose voltage dividing ratio is controlled by the FETs 21 and 22 is formed without including the FET 24 ₁ . Therefore, when the digital signal is at the high level, the voltage level V _H 'of the signal applied to the FET 42 is about 0 volt, and when it is at the low level, the voltage level V _L ' of the signal applied to the FET 42 is

[0026]

(Equation 3)

Is given by the following equation. In each of the embodiments described above, the voltage division ratio is switched by combining P-channel and N-channel FETs that are alternately turned on in accordance with the two values of the digital signal. If the voltage divider and the switching means for switching the voltage dividing ratio of the voltage divider are considered to be non-inductive and non-capacitive with respect to such digital signals, the structure of the voltage divider and the above-mentioned voltage dividing ratio are not limited. Any switching method may be used.

[0028]

As described above, according to the present invention, the voltage dividing means switches between two voltage dividing ratios set in advance by a combination of resistive elements via a switching element which is regarded as non-inductive and non-capacitive. The binary voltage level of the high-speed input signal is converted into a desired value while the high-speed convergence of the transient response accompanying the switching is achieved.

That is, by setting the resistance value of the above-described resistance element to a large value within an allowable range of an error caused by a circuit arranged at a subsequent stage, a level conversion circuit capable of suppressing power consumption and responding at high speed can be provided. Is achieved.

Therefore, the performance of the electronic apparatus to which the present invention is applied is improved.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram showing one embodiment of the present invention.

FIG. 3 is a diagram illustrating a waveform of a signal applied to a differential amplifier.

FIG. 4 is a diagram showing another embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration example of a conventional level conversion circuit.

FIG. 6 is a diagram illustrating a waveform of a signal output from a conventional level conversion circuit.

[Explanation of symbols]

 11 voltage dividing means 13 voltage dividing ratio variable means 21, 22, 23, 24, 42, 54, 56 FET 41 laser diode 51 level conversion circuit 52 differential amplifier 53 load 55, 58 constant current source 57 resistor

Claims (1)

(57) [Claims] 1. A voltage dividing means (11) for dividing a constant reference voltage at one of two predetermined voltage dividing ratios determined by a combination of resistance elements, and a non-inductive and non-inductive binary signal. Via a switching element considered non-capacitive, of the two voltage division ratios:
One of the signals corresponding to the instantaneous value of the signal is divided by the voltage dividing means (1).
A voltage dividing ratio varying means (13) configured to convert the voltage corresponding to the two values into a desired value by setting the value to 1).