JP3170519B2 - Memory card - Google Patents

Memory card

Info

Publication number
JP3170519B2
JP3170519B2 JP11913392A JP11913392A JP3170519B2 JP 3170519 B2 JP3170519 B2 JP 3170519B2 JP 11913392 A JP11913392 A JP 11913392A JP 11913392 A JP11913392 A JP 11913392A JP 3170519 B2 JP3170519 B2 JP 3170519B2
Authority
JP
Japan
Prior art keywords
semiconductor device
lead
resin
memory card
upward
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP11913392A
Other languages
Japanese (ja)
Other versions
JPH05309983A (en
Inventor
伸仁 大内
仁志 宮崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP11913392A priority Critical patent/JP3170519B2/en
Publication of JPH05309983A publication Critical patent/JPH05309983A/en
Application granted granted Critical
Publication of JP3170519B2 publication Critical patent/JP3170519B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、高密度実装可能な樹脂
封止型半導体装置を用いて構成したメモリカードに関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory card constituted by using a resin-encapsulated semiconductor device capable of high-density mounting.

【0002】[0002]

【従来の技術】現在、広く用いられているキャッシュカ
ード、クレジットカード等は、プラスチックカードに磁
気ストライプを塗布し、これに記録された情報を読み取
ることで、本人であるか否かの確認が行なえるようにし
たものである。このような磁気記録方式のものでは、第
3者によって情報が解読され易く、記録可能な情報量が
少ない。
2. Description of the Related Art At present, cash cards, credit cards and the like are widely used. A magnetic stripe is applied to a plastic card, and the information recorded on the magnetic card is read to confirm the identity of the person. That's what I did. In such a magnetic recording system, information is easily read by a third party, and the amount of recordable information is small.

【0003】そこで、近年、メモリ、CPU等の機能を
有するICをカード状基体に実装した、いわゆるICカ
ードが開発され、実用化されている。
Therefore, in recent years, a so-called IC card in which an IC having functions such as a memory and a CPU is mounted on a card-shaped base has been developed and put into practical use.

【0004】また、ICのそのものの代わりに、きわめ
て薄い半導体装置を搭載したメモリカードが提案されて
いる。図12は従来のメモリカードを示す一部破断した
斜視図である。図において、1はカバー、2はフレー
ム、3は金属シャッタ、4はその詳細を図13および図
14に示すように、複数個の樹脂封止型半導体装置5お
よび複数個のチップコンデンサ6を搭載したプリント基
板、7は接続パッドである。
[0004] In addition, a memory card on which an extremely thin semiconductor device is mounted instead of the IC itself has been proposed. FIG. 12 is a partially broken perspective view showing a conventional memory card. In the drawing, 1 is a cover, 2 is a frame, 3 is a metal shutter, and 4 is a plurality of resin-encapsulated semiconductor devices 5 and a plurality of chip capacitors 6 as shown in FIGS. The printed circuit board 7 is a connection pad.

【0005】なお、前記樹脂封止型半導体装置5は図1
3に示すように、そのリード8が半田9によりプリント
基板4に固定される。
The resin-sealed semiconductor device 5 is shown in FIG.
As shown in FIG. 3, the lead 8 is fixed to the printed circuit board 4 by the solder 9.

【0006】また、この樹脂封止型半導体装置5は図1
4に示すように構成されており、10はシリコン表面に
回路が形成された半導体素子、11はこの半導体素子1
0を接着剤12を用いて固着したダイパッドであり、図
示せぬダイパッドサポートによって支持されている。1
3は半導体素子10上に形成されたワイヤボンディング
パッドとリード8とを電気的に接続するAu線、14は
リード8の一端が露出するように封止した封止樹脂であ
る。
The resin-sealed semiconductor device 5 is similar to that shown in FIG.
Reference numeral 10 denotes a semiconductor element having a circuit formed on a silicon surface, and reference numeral 11 denotes a semiconductor element 1
Reference numeral 0 denotes a die pad fixed using an adhesive 12, and is supported by a die pad support (not shown). 1
Reference numeral 3 denotes an Au wire for electrically connecting a wire bonding pad formed on the semiconductor element 10 to the lead 8, and reference numeral 14 denotes a sealing resin in which one end of the lead 8 is sealed.

【0007】この構成による樹脂封止型半導体装置を製
造工程順に説明すると、半導体素子10をダイパッド1
1に接着剤12を用いて固着する。そして、この半導体
素子10上に形成されているワイヤボンディングパッド
とリード8をAu線13により電気的に接続する。その
後、リード8の一端が露出するように、全体を封止樹脂
14により封止する。そして、この封止樹脂14より突
出したリード8および図示せぬダイパッドサポートを切
り曲げ加工し、樹脂封止型半導体装置を得ることができ
る。そして、このリード8を熱によってプリント基板4
に半田9で接合し、カバー1をかけることにより、一枚
のメモリカードができあがる。
The resin-encapsulated semiconductor device having this configuration will be described in the order of manufacturing steps.
1 is fixed using an adhesive 12. Then, a wire bonding pad formed on the semiconductor element 10 and the lead 8 are electrically connected by the Au wire 13. Thereafter, the whole is sealed with a sealing resin 14 so that one end of the lead 8 is exposed. Then, the lead 8 protruding from the sealing resin 14 and a die pad support (not shown) are cut and bent to obtain a resin-sealed semiconductor device. Then, the leads 8 are connected to the printed board 4 by heat.
Then, a single memory card is completed by bonding with a solder 9 and covering the cover 1.

【0008】この構成によるメモリカードは、ICカー
ドよりはカード厚が厚くなるが、1つ1つの機能そのも
のが、樹脂封止型半導体装置5を使用していることか
ら、信頼性が高く、機械的強度も強く、また製造の容易
さから量産性もすぐれ、情報の容量が多いという利点が
ある。
[0008] The memory card of this configuration has a card thickness larger than that of an IC card. However, since each function itself uses the resin-encapsulated semiconductor device 5, the memory card has high reliability. It has the advantages of high target strength, excellent mass productivity due to ease of manufacture, and a large amount of information.

【0009】また、近年、メモリカードの発展をはじめ
として、電子機器の小型化、薄型化が進んでいるが、現
在、メモリカードに搭載されているTSOP(Thin
−Small−Outline−Package)、T
QFP(Thin−Quad−Flat−Packag
e)など、実装高さ1.2mmMaxという薄型樹脂封止
型半導体装置が主に使用されている。
In recent years, electronic devices have been reduced in size and thickness, including the development of memory cards, but the TSOP (Thin) currently mounted on the memory cards has been developed.
-Small-Outline-Package), T
QFP (Thin-Quad-Flat-Packag)
e) A thin resin-sealed semiconductor device having a mounting height of 1.2 mm Max is mainly used.

【0010】また、近年メモリカードの情報量は驚異的
に伸びており、しかも、メモリカードは厚み3.3mm、
縦85.6mm、幅54.0mmという規格中におさまって
いる。そして、このメモリカードに搭載される半導体装
置はより薄く、ますます高密度化が進む。
In recent years, the amount of information of a memory card has been increasing remarkably, and the memory card has a thickness of 3.3 mm.
It is within the standard of 85.6 mm long and 54.0 mm wide. The semiconductor devices mounted on the memory card are thinner and more and more dense.

【0011】[0011]

【発明が解決しようとする課題】しかしながら、上記構
成の樹脂封止型半導体装置およびそのメモリカードで
は、半導体装置の薄型化に伴い、それに使用されている
リードも薄くなり(0.15mmから0.125mmあるい
は0.1mm)、外部リードの曲がりが生じ易く、基板実
装の妨げとなっていること、また、メモリカードの情報
量の拡大化から、半導体素子におけるメモリ容量の増加
に伴ない、素子が平面状に大きくなり、高密度化が十分
に図れないこと、という問題点があった。
However, in the resin-encapsulated semiconductor device and the memory card having the above-described structure, the leads used in the semiconductor device have become thinner (from 0.15 mm to 0.1 mm) as the semiconductor device becomes thinner. 125 mm or 0.1 mm), the external leads are likely to bend, hindering the mounting on the board, and the increase in the amount of information in the memory card has led to an increase in the memory capacity of the semiconductor element. There is a problem in that it becomes large in a planar shape, and it is not possible to sufficiently increase the density.

【0012】本発明は、半導体装置の平面状の拡大に伴
う実装個数の減少、および半導体装置のリード曲がりに
よる基板実装への弊害をなくすために、樹脂封止型半導
体装置のリードの形状および樹脂封止部を改良して、樹
脂封止型半導体装置の高密度な実装を可能にした優れた
メモリカードを提供することを目的とする。
The present invention is intended to reduce the number of mountings due to the planar expansion of a semiconductor device, and to eliminate the adverse effects on the substrate mounting due to bending of the leads of the semiconductor device. An object of the present invention is to provide an excellent memory card in which a sealing portion is improved to enable high-density mounting of a resin-sealed semiconductor device.

【0013】[0013]

【課題を解決するための手段】本発明に係るメモリカー
は、第1の電極が形成された第1の半導体素子と、表
面及び裏面とを有し前記第1の電極に電気的に接続され
た第1のリードと、前記第1のリードの表面の一部が露
出するように前記第1のリード及び前記第1の半導体素
子を覆う封止樹脂とを有する第1の樹脂封止型半導体装
置と、第2の電極が形成された第2の半導体素子と、表
面及び裏面とを有し前記第2の電極に電気的に接続され
た第2のリードと、前記第2のリードの裏面の一部が露
出するように前記第2のリード及び前記第2の半導体素
子を覆う封止樹脂とを有する第2の樹脂封止型半導体装
置と、前記第1の樹脂封止型半導体装置と前記第2の樹
脂封止型半導体装置とが搭載される基板とを含むメモリ
カードであって、前記第1の樹脂封止型半導体装置と前
記第2の樹脂封止型半導体装置は、前記第1のリードの
前記露出した表面と前記第2のリードの前記露出した裏
面とが接続された状態で前記基板に搭載されていること
を特徴とするものである。
A memory card according to the present invention comprises: a first semiconductor element having a first electrode formed thereon;
Having a surface and a back surface, and electrically connected to the first electrode.
The first lead and a part of the surface of the first lead are exposed.
The first lead and the first semiconductor element
And a first resin-encapsulated semiconductor device having an encapsulation resin for covering the element.
Device, a second semiconductor element on which the second electrode is formed, and a table.
A surface and a back surface, and electrically connected to the second electrode.
The second lead and a part of the back surface of the second lead are exposed.
The second lead and the second semiconductor element
A second resin-sealed semiconductor device having a sealing resin covering
And the first resin-encapsulated semiconductor device and the second tree.
A memory including a substrate on which a fat-sealed semiconductor device is mounted
A card, wherein the first resin-encapsulated semiconductor device is
The second resin-encapsulated semiconductor device is provided with the first lead.
The exposed surface and the exposed back of the second lead
Mounted on the board with the surface connected
It is characterized by the following.

【0014】[0014]

【0015】[0015]

【作用】本発明に係るメモリカード中の樹脂封止型半導
体装置はリード形状および樹脂封止部により、プリント
基板上に高密度に実装することができる。
According to the present invention, the resin-encapsulated semiconductor device in the memory card according to the present invention can be mounted at high density on a printed circuit board by the lead shape and the resin-encapsulated portion.

【0016】[0016]

【実施例】図1は本発明に係るメモリカードの樹脂封止
型半導体装置の一実施例を示す断面図である。図におい
て、15はその詳細な構成を図1(A)に示すように、
内部リードの半田付面を下側にして形成した下向リード
16を備えた下向リード付き樹脂封止型半導体装置(以
下単に下向半導体装置と言う)、17はその詳細な構成
を図1(B)に示すように、内部リードの半田付面を上
側にして形成した上向リード18を備えた上向リード付
き樹脂封止型半導体装置(以下単に上向半導体装置と言
う)である。
FIG. 1 is a sectional view showing one embodiment of a resin-sealed semiconductor device of a memory card according to the present invention. In the figure, reference numeral 15 denotes the detailed configuration as shown in FIG.
FIG. 1 shows a detailed configuration of a resin-encapsulated semiconductor device (hereinafter simply referred to as a “downward semiconductor device”) having downward leads 16 having downward leads 16 formed with the soldering surfaces of the internal leads facing downward. As shown in FIG. 1B, a resin-encapsulated semiconductor device with upward leads (hereinafter simply referred to as upward semiconductor device) having upward leads 18 formed with the soldering surfaces of the internal leads facing upward.

【0017】この構成による下向半導体装置15および
上向半導体装置17ではリードが外に出ない分、実装面
積を小さくすることができる。
In the downward semiconductor device 15 and upward semiconductor device 17 having this configuration, the mounting area can be reduced because the leads do not go outside.

【0018】なお、製造方法については、従来どうりの
工程により製造することができることはもちろんである
が、樹脂で形取る金型の型状を図1に示すようにし、す
べてリードカットをするだけである。
As for the manufacturing method, it goes without saying that it can be manufactured by the same process as the conventional method, but the shape of the mold to be molded with resin is as shown in FIG. It is.

【0019】図2および図3は本発明に係るメモリカー
ドの一実施例を示す一部詳細な断面図およびA矢視方向
の断面図である。この構成によるメモリカードでは、プ
リント基板4の両面に図示せぬ接合パッドを設け、この
接合パッドに、下向半導体装置15の下向リード16お
よび上向半導体装置17の上向リード18を半田9によ
り固定するものである。この結果、実装高さが非常に低
くなるうえ、高密度でかつ薄型のメモリカードを作るこ
とができる。このとき、下向リード16および上向リー
ド18は、樹脂にはまっているので、リード曲りも生じ
ず、基板実装をスムーズに行なうことができる。
FIGS. 2 and 3 are a partially detailed cross-sectional view and a cross-sectional view taken in the direction of the arrow A showing an embodiment of the memory card according to the present invention. In the memory card having this configuration, bonding pads (not shown) are provided on both surfaces of the printed circuit board 4, and the downward leads 16 of the downward semiconductor device 15 and the upward leads 18 of the upward semiconductor device 17 are soldered to the bonding pads. It is fixed by. As a result, the mounting height is extremely low, and a high-density and thin memory card can be manufactured. At this time, since the downward lead 16 and the upward lead 18 are fitted in the resin, the lead does not bend and the board can be mounted smoothly.

【0020】また、図4〜図8はリードの基板実装時の
半田接合強度を増すための種々の方法を示す。図4
(A)および図4(B)は、各リード16の3面をむき
出しにして、若干リード強度を犠牲にし、半田接合強度
を増加させることができる。図5(A)および図5
(B)は、各リード16の側面を半分だけむき出しにし
て、半田接合強度を若干犠牲にし、リード強度を増加さ
せたものである。この図4および図5は、いずれも金型
設計で製造可能である。
FIGS. 4 to 8 show various methods for increasing the solder joint strength when the leads are mounted on the substrate. FIG.
4 (A) and FIG. 4 (B), the three surfaces of each lead 16 are exposed, so that the lead strength is slightly sacrificed and the solder bonding strength can be increased. FIG. 5 (A) and FIG.
(B) shows that the side surface of each lead 16 is exposed by half, and the solder joint strength is slightly sacrificed to increase the lead strength. 4 and 5 can be manufactured with a mold design.

【0021】また、通常、リードは半田メッキ後に、リ
ード切り曲げが行なわれるため、切断面には半田メッキ
がされておらず、もちろん、基板実装時にも、半田はつ
かず、接合としては不十分であるため、図6に示す実施
例では、切断する部分のリード16をハーフエッジ16
Aにしておき(図6(A)参照)、半田メッキ後に切断
すると、リード16の断面の半分には半田9がつき(図
6(B)参照)、接合強度を増すことができる。
Further, since the lead is usually cut and bent after the solder plating, the cut surface is not plated with solder. Of course, the solder is not attached even at the time of board mounting, and the bonding is insufficient. Therefore, in the embodiment shown in FIG.
A (see FIG. 6A) and cutting after solder plating, solder 9 is attached to half of the cross section of the lead 16 (see FIG. 6B), and the bonding strength can be increased.

【0022】同様に、半田接合形状を生む方法として、
図7を示す。この実施例では、リード切りを、リード厚
の2〜3倍長くし、後に、リードを上曲げし、半田接合
を行なう。このとき、リード厚分だけ、実装面積は大き
くなることはもちろんである。
Similarly, as a method of producing a solder joint shape,
FIG. 7 is shown. In this embodiment, the lead cutting is made two to three times longer than the lead thickness, and then the lead is bent upward and soldered. At this time, the mounting area is naturally increased by the lead thickness.

【0023】図8はあらかじめ、リード16をアップセ
ット19(図8(A)参照)することにより、そのアッ
プセット19の部分にも半田接合(図8(B)参照)
し、強度を増すことができる。
FIG. 8 shows that the lead 16 is previously set up (see FIG. 8 (A)) and soldered to the upset 19 (see FIG. 8 (B)).
And the strength can be increased.

【0024】なお、以上の説明は下向リード16の半田
接合について説明したが、上向リード18の半田接合に
ついても同様にできることはもちろんである。
In the above description, the solder bonding of the downward lead 16 has been described. However, it is needless to say that the solder bonding of the upward lead 18 can be similarly performed.

【0025】図9は本発明に係る樹脂封止型半導体装置
の他の実施例を示す断面図である。図において、20は
その詳細な構成を図9(A)に示すように、ノーマルリ
ード21および上向リード18を有するノーマル・上向
リード付き樹脂封止型半導体装置(以下単にノーマル・
上向半導体装置と言う)、22はその詳細な構成を図9
(B)に示すように、上向リード18およびノーマルリ
ード23を有する上向・ノーマルリード付き樹脂封止型
半導体装置(以下単に上向・ノーマル半導体装置と言
う)である。
FIG. 9 is a sectional view showing another embodiment of the resin-sealed semiconductor device according to the present invention. In the figure, reference numeral 20 denotes a detailed configuration of a resin-encapsulated semiconductor device having a normal lead 21 and an upward lead 18 as shown in FIG.
FIG. 9 shows the detailed structure of the semiconductor device 22 in FIG.
As shown in FIG. 2B, a resin-encapsulated semiconductor device with upward and normal leads having upward leads 18 and normal leads 23 (hereinafter simply referred to as upward and normal semiconductor device).

【0026】なお、図9(C)は下向半導体装置15を
示し、図9(D)は上向半導体装置17を示す。
FIG. 9C shows the downward semiconductor device 15 and FIG. 9D shows the upward semiconductor device 17.

【0027】この構成によるノーマル・上向半導体装置
20、上向・ノーマル半導体装置22、下向半導体装置
15および上向半導体装置17では、リードが外へ出な
い分(当然ノーマルリード21および23分は除く)だ
け、実装面積を小さくすることができる。
In the normal / upward semiconductor device 20, the upward / normal semiconductor device 22, the downward semiconductor device 15, and the upward semiconductor device 17 having this configuration, the lead does not go out (of course, the normal leads 21 and 23 minutes). ), The mounting area can be reduced.

【0028】なお、製造方法については、従来通りの工
程により製造することができることはもちろんである。
As for the manufacturing method, it goes without saying that it can be manufactured by the conventional steps.

【0029】図10は本発明に係るメモリカードの一実
施例を示す断面図であり、図9(A)〜図9(D)に示
す樹脂封止型半導体装置を搭載したメモリカードであ
る。この場合、下向半導体装置15の下向リード16と
上向半導体装置17の上向リード18とを図11に示す
ように半田24により互に直接接続する。この接続部分
は半導体装置外形内であるので、実装面積をおさえるこ
とができる。そして、下向半導体装置15と上向半導体
装置17を複数個一体に接続したものの一方に、ノーマ
ル・上向半導体装置20を接続し、他方に、上向・ノー
マル半導体装置22を接続し、プリント基板4に固定す
るものである。このとき、下向リード16とその上部の
封止樹脂14の厚さと、上向リード18とその下部の封
止樹脂14の厚さをたした厚さが樹脂封止型半導体装置
15,17の厚さと同一になる様にすれば、無駄な空間
が減少して、必要最小限の厚さで実装することができ
る。
FIG. 10 is a sectional view showing an embodiment of the memory card according to the present invention, which is a memory card on which the resin-sealed semiconductor device shown in FIGS. 9A to 9D is mounted. In this case, the downward lead 16 of the downward semiconductor device 15 and the upward lead 18 of the upward semiconductor device 17 are directly connected to each other by solder 24 as shown in FIG. Since this connection portion is within the outer shape of the semiconductor device, the mounting area can be reduced. Then, a normal / upward semiconductor device 20 is connected to one of a plurality of downward semiconductor devices 15 and upward semiconductor devices 17 which are integrally connected, and an upward / normal semiconductor device 22 is connected to the other. It is to be fixed to the substrate 4. At this time, the sum of the thickness of the downward lead 16 and the sealing resin 14 on the upper part thereof and the thickness of the upward lead 18 and the thickness of the sealing resin 14 on the lower part thereof are equal to those of the resin-encapsulated semiconductor devices 15 and 17. If the thickness is the same as the thickness, useless space is reduced, and the mounting can be performed with the minimum necessary thickness.

【0030】このように、メモリカードに多数の樹脂封
止型半導体装置を実装することができるので、容量を大
幅に増加することができる。
As described above, since a large number of resin-sealed semiconductor devices can be mounted on the memory card, the capacity can be greatly increased.

【0031】[0031]

【発明の効果】以上詳細に説明したように、本発明に係
る樹脂封止型半導体装置を使用したメモリカードによれ
ば、内部リードの上側あるいは下側の封止樹脂部を取り
除き、むき出しになった内部リードの下側あるいは上側
を半田付面として形成した樹脂封止型半導体装置、ある
いは、一方がノーマルリードで、他方が内部リードであ
る樹脂封止型半導体装置により、プリント基板への実装
時のリード曲りをなくすことができ、スムーズにかつ確
実に実装することができる。しかも、これらの樹脂封止
型半導体装置をプリント基板に実装し、メモリカードと
したとき、その厚さを、より薄くすることができ、しか
も高密度化することができるなどの効果がある。
As described in detail above, according to the memory card using the resin-encapsulated semiconductor device according to the present invention, the encapsulation resin portion above or below the internal leads is removed to expose the internal leads. When mounting on a printed circuit board using a resin-encapsulated semiconductor device in which the lower or upper side of the internal lead is formed as a soldering surface, or a resin-encapsulated semiconductor device in which one is a normal lead and the other is an internal lead Can be eliminated, and mounting can be performed smoothly and reliably. Moreover, when these resin-encapsulated semiconductor devices are mounted on a printed circuit board to form a memory card, the thickness can be reduced and the density can be increased.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係るメモリカードの樹脂封止型半導体
装置の一実施例を示す断面図である。
FIG. 1 is a cross-sectional view showing one embodiment of a resin-sealed semiconductor device of a memory card according to the present invention.

【図2】本発明に係るメモリカードの一実施例を示す一
部詳細な断面図である。
FIG. 2 is a partially detailed sectional view showing one embodiment of a memory card according to the present invention.

【図3】図2のA矢視方向の断面図である。FIG. 3 is a sectional view in the direction of arrow A in FIG. 2;

【図4】図2における半田接合部の他の例を示す要部断
面図である。
FIG. 4 is a cross-sectional view of a principal part showing another example of the solder joint in FIG. 2;

【図5】図2における半田接合部の更に他の例を示す要
部断面図である。
FIG. 5 is a cross-sectional view of a principal part showing still another example of a solder joint in FIG. 2;

【図6】図2における半田接合部の更に他の例を示す要
部断面図である。
FIG. 6 is a cross-sectional view of a principal part showing still another example of the solder joint in FIG. 2;

【図7】図2における半田接合部の更に他の例を示す要
部断面図である。
FIG. 7 is a cross-sectional view of a principal part showing still another example of the solder joint in FIG. 2;

【図8】図2における半田接合部の更に他の例を示す要
部断面図である。
FIG. 8 is a cross-sectional view of a principal part showing still another example of the solder joint in FIG. 2;

【図9】本発明に係るメモリカードの樹脂封止型半導体
装置の他の実施例を示す断面図である。
FIG. 9 is a cross-sectional view showing another embodiment of the resin-sealed semiconductor device of the memory card according to the present invention.

【図10】本発明に係るメモリカードの他の実施例を示
す要部断面図である。
FIG. 10 is a cross-sectional view of a main part showing another embodiment of the memory card according to the present invention.

【図11】図10の一部詳細な断面図である。FIG. 11 is a partially detailed sectional view of FIG. 10;

【図12】従来のメモリカードの一部破断した斜視図で
ある。
FIG. 12 is a partially cutaway perspective view of a conventional memory card.

【図13】図12の一部詳細な断面図である。FIG. 13 is a partially detailed sectional view of FIG. 12;

【図14】図12の樹脂封止型半導体装置の断面図であ
る。
14 is a cross-sectional view of the resin-sealed semiconductor device of FIG.

【符号の説明】[Explanation of symbols]

15 下向リード付き樹脂封止型半導体装置 16 下向リード 17 上向リード付き樹脂封止型半導体装置 18 上向リード 20 ノーマル・上向リード付樹脂封止型半導体装置 21 ノーマルリード 22 下向・ノーマルリード付樹脂封止型半導体装置 23 ノーマルリード 15 Resin-sealed semiconductor device with downward lead 16 Downward lead 17 Resin-sealed semiconductor device with upward lead 18 Upward lead 20 Normal / upward lead resin-sealed semiconductor device 21 Normal lead 22 Downward Resin-sealed semiconductor device with normal leads 23 Normal leads

フロントページの続き (56)参考文献 特開 昭62−298146(JP,A) 特開 平2−239651(JP,A) 特開 平4−171856(JP,A) 実開 平3−17644(JP,U) 実開 昭60−45447(JP,U) (58)調査した分野(Int.Cl.7,DB名) G06K 19/077 B42D 15/10 H01L 23/28 - 23/50 Continuation of front page (56) References JP-A-62-298146 (JP, A) JP-A-2-239651 (JP, A) JP-A-4-171856 (JP, A) JP-A-3-17644 (JP) (U, U) Sho 60-45447 (JP, U) (58) Fields investigated (Int. Cl. 7 , DB name) G06K 19/077 B42D 15/10 H01L 23/28-23/50

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 第1の電極が形成された第1の半導体素
子と、 表面及び裏面とを有し前記第1の電極に電気的に接続さ
れた第1のリードと、 前記第1のリードの表面の一部が露出するように前記第
1のリード及び前記第1の半導体素子を覆う封止樹脂と
を有する第1の樹脂封止型半導体装置と、 第2の電極が形成された第2の半導体素子と、 表面及び裏面とを有し前記第2の電極に電気的に接続さ
れた第2のリードと、 前記第2のリードの裏面の一部が露出するように前記第
2のリード及び前記第2の半導体素子を覆う封止樹脂と
を有する第2の樹脂封止型半導体装置と、 前記第1の樹脂封止型半導体装置と前記第2の樹脂封止
型半導体装置とが搭載される基板とを含むメモリカード
であって、 前記第1の樹脂封止型半導体装置と前記第2の樹脂封止
型半導体装置は、前記第1のリードの前記露出した表面
と前記第2のリードの前記露出した裏面とが接続された
状態で前記基板に搭載されていることを特徴とするメモ
リカード。
1. A first semiconductor element on which a first electrode is formed.
And a front and back surface, and electrically connected to the first electrode.
The first lead and the first lead so that a part of the surface of the first lead is exposed.
A sealing resin covering the first lead and the first semiconductor element;
A first resin-encapsulated semiconductor device having a first electrode, a second semiconductor element on which a second electrode is formed, and a front surface and a back surface, which are electrically connected to the second electrode.
And the second lead so that a part of the back surface of the second lead is exposed.
A sealing resin covering the second lead and the second semiconductor element;
A second resin-sealed semiconductor device having the same, the first resin-sealed semiconductor device, and the second resin-sealed
Card including a semiconductor device and a substrate on which the semiconductor device is mounted
In a, the second resin sealing the first resin-encapsulated semiconductor device
Semiconductor device, wherein the exposed surface of the first lead is
And the exposed back surface of the second lead was connected
Memo characterized by being mounted on the substrate in a state.
Ricardo.
JP11913392A 1992-05-12 1992-05-12 Memory card Expired - Fee Related JP3170519B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11913392A JP3170519B2 (en) 1992-05-12 1992-05-12 Memory card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11913392A JP3170519B2 (en) 1992-05-12 1992-05-12 Memory card

Publications (2)

Publication Number Publication Date
JPH05309983A JPH05309983A (en) 1993-11-22
JP3170519B2 true JP3170519B2 (en) 2001-05-28

Family

ID=14753757

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11913392A Expired - Fee Related JP3170519B2 (en) 1992-05-12 1992-05-12 Memory card

Country Status (1)

Country Link
JP (1) JP3170519B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09260538A (en) 1996-03-27 1997-10-03 Miyazaki Oki Electric Co Ltd Resin sealed semiconductor device manufacturing method and its mounting structure
JP2003092380A (en) * 2001-09-18 2003-03-28 Mitsubishi Electric Corp Semiconductor device

Also Published As

Publication number Publication date
JPH05309983A (en) 1993-11-22

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