KR100300266B1 - Thin semiconductor device, module structure using the same, and board mounting method of the semiconductor device - Google Patents

Abstract

The tip of the inner lead is arranged in the vicinity of the peripheral end of the semiconductor chip, a part of the insulating tape is attached to the main surface of the semiconductor chip with an adhesive, and another part of the insulating tape is attached to the part of the inner lead with an adhesive.

The electrode pads provided on the main surface of the semiconductor chip and the tip portions of the inner leads corresponding thereto are electrically connected by bonding wires, and the semiconductor chips, inner leads, electrode pads, insulating tapes, and bonding wires are sealed by mold resins. It is done.

The thickness of the insulating tape is equal to or less than a height from the main surface of the semiconductor chip to the apex of the bonding wire, the front end surface of the inner lead to which the bonding wire is connected is located below the main surface of the semiconductor chip, and the inner The lead is located between the main surface and the opposite surface of the semiconductor chip.

Description

Thin semiconductor device, module structure using same, and substrate mounting method of the semiconductor device

1 is a plan view of a state in which the upper half of the mold resin showing the structure of the thin semiconductor device of the TOC package according to the first embodiment of the present invention is removed.

2 is a cross-sectional view taken along the line II-II in FIG.

3 is a cross-sectional view taken along the line III-III in FIG.

4 is a view showing another example of the support form by the insulating tape in FIG.

FIG. 5 is a sectional view showing a configuration of a modification in which light incidence blocking means such as aluminum foil is provided on the main surface of the semiconductor chip of the first embodiment. FIG.

6 is a cross-sectional view showing a state in which the main surface of the semiconductor chip is mounted against the mounting substrate in order to block light incidence to the main surface of the semiconductor chip in the first embodiment.

7 is a cross-sectional view showing a laminate according to a second embodiment in which the semiconductor device of the first embodiment is stacked in two stages.

8 is a cross-sectional view for explaining a method for mounting the semiconductor device of the first embodiment to a substrate.

9 is a cross-sectional view for explaining a method for mounting the semiconductor device of the first embodiment on a substrate in two stages.

10 is a cross-sectional view illustrating another example in which the semiconductor device of the present invention is mounted on a substrate.

11 is a cross-sectional view for explaining another method for mounting the semiconductor device of the present invention on a substrate in two stages.

12 is a perspective view showing an embodiment of a module structure using the semiconductor device of the present invention.

13 is a perspective view showing another embodiment of the module structure using the semiconductor device of the present invention.

* Explanation of the main symbols for the drawings

1: semiconductor chip. 1a: electrode pad.

2: lead. 2a: inner lead.

2b: Outstanding. 3: insulating film tape.

4: adhesive. 5: Support lead.

6: bonding wire. 7: mold resin.

10: aluminum foil.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin semiconductor device, a module structure using the same, and a method of mounting the semiconductor device on a substrate, and in particular, an ultra-thin semiconductor device applied to a large-capacity memory device in a small package including a memory card or a semiconductor device in multiple stages, A module structure and a method for mounting the semiconductor device on a substrate.

As a small package of a conventional thin semiconductor device, a 1.2 mm thick thin small outline package (TSOP) type employing a tabbed lead frame and a wire bonding method has been developed. This is described, for example, in GAIN 83, November, 1990, pages 30 to 31 of Hitachi, Ltd., issued.

In addition, in a 3.3-mm-thick memory card, a large-capacity memory card has been developed in which a TSOP type thin semiconductor device is mounted on both sides and the mounting efficiency is maximized. However, since the demand for a thinner TSOP type is strong, a 0.5 mm thick TCP (Tape Carrier Package) type having the same outer size as the TSOP type has been proposed. This is described, for example, in Nikkei Micro Devices, Feb. 1991, pages 65-66. This TCP-type thin semiconductor device has a structure in which the semiconductor chip is made thin by about 0.2 mm, and the semiconductor chip and the inner lead are electrically connected by TAB (Tape Automated Bonding) bonding to electrically connect the semiconductor chip.

In addition, a semiconductor device in which the package thickness is made thin by adhesively fixing an element holder made of a thin heat-resistant resin formed of polyimide to a part of the diffusion surface and a part of the inner lead of the semiconductor element It is shown by Unexamined-Japanese-Patent No. 4-106941. In this device, when connecting the electrode and the inner lead of the semiconductor element with a metal wire, the distance between the end of the semiconductor element and the metal wire is increased so as not to cause a short defect, and the main surface of the semiconductor element and the upper surface of the inner lead are the same. It is made flat.

Further, a semiconductor device in which a metal film lead is disposed on an insulating tape and the main surface of the semiconductor element is supported on a lower surface of a portion of the insulating tape is shown in Japanese Patent Laid-Open No. 3-261153.

Moreover, the semiconductor device which arrange | positions the tab part (die pad part) of a lead frame on the main surface of a semiconductor element, and supports the semiconductor element at the said step part is shown by Unexamined-Japanese-Patent No. 1-286342.

MEANS TO SOLVE THE PROBLEM As a result of examining the thin semiconductor device of the TCP structure of a plastic mold by the said TAB system bonding, the present inventor discovered the following problem.

(1) Since the outright is made of copper foil, the strength of the outward is weak. As a result, the lead is bent, resulting in poor contact.

(2) Since the strength of the outlier is weak, it is difficult to select the socket.

(3) Since the bonding of the TAB method is used, it is expensive compared with the bonding of the lead frame method.

In Japanese Patent Laid-Open No. 4-106941, since the main surface of the semiconductor element and the upper surface of the inner lead are coplanar, when the electrode and the inner lead of the semiconductor element are connected by metal wires, the semiconductor element is a semiconductor element. The height at the main surface of the film becomes high, and a thin package cannot be obtained. Further, even when the metal wires are connected by wire reverse bonding, the main surface of the semiconductor element and the upper surface of the inner lead are coplanar, so that the package cannot be made sufficiently thin.

In addition, in Japanese Unexamined Patent Publication No. 3-261153, since the upper surface of the inner lead is located above the main surface of the semiconductor element, the height (hereinafter referred to as a "loop height") at the main surface of the semiconductor element of the bonding wire vertex becomes high, and thus a thin package. Is not obtained.

Further, in Japanese Patent Laid-Open No. 1-286342, the die pad portion thicker than the resin tape is on the main surface of the semiconductor element, and the upper surface of the inner lead is located above the main surface of the semiconductor element. Therefore, the loop height is high and a thin package cannot be obtained.

An object of the present invention is to provide a thin semiconductor device in a package such as a tape on chip (TOC) type having a thickness of about 0.5 mm, a module structure using the same, and a method of mounting the same on a substrate.

Another object of the present invention is to provide a thin semiconductor device of about 0.5 mm thickness having a high outstretch strength using a lead frame, a module structure using the same, and a method of mounting the same on a substrate.

According to one aspect of the present invention, an inner lead having an end portion arranged in the vicinity of a peripheral end portion of a semiconductor chip, and an insulating tape in which a part of the insulating film is attached with an adhesive to a main surface of the semiconductor chip, the other part of the insulating tape is formed of the inner lead. Bonding wires, which are attached to a portion of the semiconductor chip and electrically connected to the electrode pads provided on the main surface of the semiconductor chip, and the tip of the inner lead corresponding thereto, the semiconductor chip, inner lead, electrode pad, insulating film tape, and bonding wire And a thickness of the insulating tape, the thickness of the insulating tape being less than or equal to a height from the main surface of the semiconductor chip to the apex of the bonding wire, and the surface of the tip of the inner lead to which the bonding wire is connected is formed. Located below the main surface of the semiconductor chip, the inner lead is opposite to the main surface of the semiconductor chip It provides a thin type semiconductor device which is located between the side.

As such, the thickness of the insulating tape for supporting the chip is equal to or less than the height from the main surface of the semiconductor chip to the apex of the bonding wire, and the surface of the tip portion of the inner lead to which the bonding wire is connected is the main surface of the semiconductor chip. Since the inner lead is located between the main surface and the opposite surface of the semiconductor chip, the inner lead is placed in a package such as a tape on chip (TOC) type with a high strength of neighboring 0.5 mm thickness. A thin semiconductor device can be obtained.

According to one embodiment of the present invention, a thick mold resin is provided on the upper side of the bonding wire by having the ball side by the ball bonding method in the structure of the bonding wire and the non-ball side in the semiconductor chip. Since it is possible to do so, a thinner ultra-thin semiconductor device is obtained.

According to one embodiment of the present invention, a part of the inner lead to which the insulating film tape is attached is located on the same surface as the main surface of the semiconductor chip. Therefore, the insulating film tape can be easily attached to the inner lead.

According to one embodiment of the present invention, each of the inner leads forms an outwardly extending outward from a substantially central portion of the thickness in the direction perpendicular to the main surface of the mold resin. Therefore, the thickness of the mold resin can be made thin.

According to one embodiment of the present invention, each of the outounds has a width in a direction perpendicular to the main surface than a width in a direction perpendicular to the main surface of the mold resin. Therefore, since a part of each outward protrusion protrudes from the mold resin, soldering can be performed satisfactorily even if the substrate is bent or the like during soldering to the substrate.

According to one embodiment of the present invention, each of the outlets may include a first portion extending substantially parallel to the main surface in the mold resin, and an opposite surface substantially parallel to the main surface of the mold resin in the first portion. A second portion bent to one side of the second portion, a third portion extending outward so as to be substantially flush with one side of the opposite surface, and a fourth portion bent from the third portion to the other side of the opposite surface, The fourth portion has a fifth portion extending inward to be substantially flush with the other side of the opposite surface. In this manner, by bending the outwards to lengthen the dimension of the outwards and making them elastic, the stress caused by the temperature cycle during soldering can be absorbed, so that the cracks in the soldering of the mounting portion can be prevented. .

According to one embodiment of the present invention, each of the outounds has a plating layer around its outside. Therefore, soldering can be performed collectively, and in particular, in the case where a plurality of semiconductor devices are stacked, the soldering process can be performed at once, so that the assembly process can be significantly reduced.

According to another aspect of the present invention, an inner lead having an end portion arranged in the vicinity of a peripheral end portion of a semiconductor chip, and an insulating tape in which a portion of the insulating film is attached to the main surface of the semiconductor chip with an adhesive, wherein the other portion of the insulating tape is the inner lead. A bonding wire attached to a portion of the semiconductor chip and electrically connected to an electrode pad provided on a main surface of the semiconductor chip and an end portion of the inner lead corresponding thereto; the semiconductor chip, inner lead, electrode pad, insulating film tape, and bonding wire. And a mold resin for sealing the film, wherein the thickness of the insulating tape is equal to or less than a height from a main surface of the semiconductor chip to the apex of the bonding wire, and each of the inner leads forms an outward extending out of the mold resin. And each of the inner leads is opened substantially parallel to the main surface in the mold resin. An elongated first portion, a second portion bent to one side of the opposite side substantially parallel to the main surface of the mold resin at the first portion, and extending out to be substantially flush with one side of the opposite side at the second portion; A thin semiconductor device having a third portion, a fourth portion bent from the third portion to the other side of the opposite side, and a fifth portion extending inward from the fourth portion to be substantially flush with the other side of the opposite side; to provide.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In addition, in the whole figure for demonstrating an embodiment, the same code | symbol is attached | subjected and the repeated description is abbreviate | omitted.

FIG. 1 is a plan view of a film type semiconductor device of a tape on chip (TOC) package according to a first embodiment of the present invention, and shows a plan view of a state in which the upper half of the mold resin is removed to explain the configuration. 2 and 3 are cut along the lines II-II and III-III of FIG. 1, respectively.

In the thin semiconductor device (TOC package) of the first embodiment, as shown in FIGS. 1 and 2, the tip of the inner lead 2A of the lead 2 is planar in the vicinity of the peripheral end of the semiconductor chip 1. It is arranged in a shape. A portion of the stripe-shaped insulating tape 3 is attached to the main surface of the semiconductor chip 1 with an adhesive 4, and another portion of the insulating tape 3 is attached to some of the inner leads 2A or the like. When the support lead 5 is provided, it is attached to the at least one with the adhesive agent 4, for example. The tip portions of the electrode pads 1A provided on the main surface of the semiconductor chip 1 and the corresponding inner leads 2A are electrically connected to the bonding wires 6, respectively, and these are sealed with the mold resin 7. It is structured.

In addition, the insulating tape 3 for supporting the semiconductor chip 1 is preferably at least four points or at least three points such that the semiconductor chip is not twisted (tilted) or moved during the mold. Support 2A). However, when supporting at four points, as shown by the dotted line in FIG. 4, for example, the inner lead may be supported at the four leading ends by using a + -shaped insulating tape 3, and at three points. The inner lead may be supported by the three leading ends thereof, for example, using a T-shaped insulating tape, as shown by the solid line in FIG. In this case, when at least one support lead 5 is provided, the support lead may be supported by at least one tip of the insulating tape.

As the insulating film tape 3, for example, a polyimide resin is used, and as the adhesive agent 4, for example, a polyimide resin or an epoxy resin is used. The thickness of the insulating film tape 3 is equal to or less than a height (hereinafter referred to as a loop height) from the main surface of the semiconductor chip 1 to the apex of the bonding wire 6, for example, in FIG. 2. As shown, the thickness of the adhesive agent 4 is also 0.05 mm. The thickness of each part other than the insulating film tape 3 is, for example, 0.10 mm in thickness from the bottom surface of the mold resin 7 to the semiconductor chip 1, 0.28 mm in thickness of the semiconductor chip 1, and the semiconductor chip 1. Is 0.12 mm in thickness from the main surface of the mold) to the top surface of the mold resin 7, and the distance between the mounting substrate surface and the bottom surface of the mold resin 7 is 0.03 mm.

The mold resin 7 uses, for example, an epoxy resin to which a phenolic curing agent, a silicone rubber, and a filler are added in order to achieve low stress.

The bonding of the said bonding wire 6 is a ball bonding method, the ball side of the bonding wire 6 is provided in the inner lead 2A, and the non-ball side is provided in the semiconductor chip 1. Since the amount of the mold resin 7 on the bonding wire 6 is increased by the reverse bonding in this way, if the same thickness is achieved, the reliability is improved, and if the problem is a problem in terms of reliability, the mold resin on the bonding wire 6 is Since the amount of (7) can be reduced, it is possible to make it thinner. Therefore, the reverse bonding or the normal bonding may be selected in accordance with the thickness demand of the semiconductor device.

Further, as evident in FIG. 2, the bonding surface of the inner lead is located below the main surface of the semiconductor chip, and the surface opposite to the bonding surface of the inner lead is located above the surface opposite to the main surface of the semiconductor chip. have. As a result, the roof height can be made lower, and the length of the bonding wire can be made shorter.

Further, the tip portion of the inner lead having the insulating film 3 attached thereto is bent, and as shown in FIG. 3, the insulating film tape is easily attached since the tip portion is flush with the main surface of the semiconductor chip.

Further, as shown in FIG. 2, the lead protrudes from the mold resin, i.e., almost the center portion in the thickness direction of the package.

The outer 2B includes a portion 2B1 protruding substantially parallel to the main surface of the semiconductor chip at a substantially center portion in the thickness direction of the package, a portion 2B2 bent to the main surface side thereafter, and a rear surface side thereof. Part 2B3 almost flush with the surface of the package, the surface 2B4 nearly bent perpendicularly to the main surface of the semiconductor chip, and then perpendicular to the main surface, and then packaged on the side opposite to the main surface toward the package. It is formed of the part 2B5 which becomes substantially the same height as the surface. Further, preferably, the lower surface of the portion 2B5 protrudes about 0.3 mm from the lower surface of the mold resin (package). Thereby, the part 2B5 can be reliably soldered to the board | substrate even if a board | substrate is bent or bent at the time of soldering at the time of the mounting of the semiconductor device to the board | substrate.

In the case where the semiconductor devices shown in FIGS. 9 and 11 are soldered onto a substrate and stacked upward, the surface 2B4 of the outlier 2B does not need to be substantially perpendicular to the main surface, and is perpendicular to the main surface. You may tilt it more than the face.

The outlier 2B may be formed to be bent toward the main surface side of the semiconductor chip symmetrically with FIG. 2 in the thickness direction of the package symmetrically (see FIG. 6). Such an outlier is referred to herein as an outward bent outward, and the second one is called an outwardly bent outward.

In this manner, since the bent 2B is curved in a nearly J-band shape, the entire length of the beaded 2B can be lengthened and elasticity can be provided. In this configuration, since the elasticity of the outer 2B absorbs the stress caused by the temperature cycle during soldering at the time of mounting the substrate, cracking occurs in the soldering of the connecting portion with the wiring pad on the mounting substrate. Can be prevented.

Each of the inner lead 2A and the outer lead 2B is integrally formed with a lead frame before the cutting process. The lead frame is made of, for example, a Fe-Ni (eg Ni content 42 or 50% [5]) alloy, Cu, or the like.

Next, the assembly process of the thin semiconductor device of this embodiment will be briefly described.

The assembling process of the thin semiconductor device of the present embodiment is performed in the following process order.

(1) The insulating tape 3 is attached and fixed to some of the inner leads 2A of the lead frame by the thermoplastic adhesive 4.

(2) The semiconductor chip 1 is fixed to the insulating film tape 3 by the thermoplastic adhesive 4 (with a pellet).

(3) The semiconductor chip 1 is fixed by making the lower base into a vacuum, and wire bonding is performed.

(4) The whole is molded with resin (resin) and sealed.

(5) A solder plating treatment is performed on each of the outlets 2B, and for example, a solder plating layer (not shown) having a total thickness of about 10 μm is provided.

(6) The lead frame 2B is cut in the lead frame.

(7) Each outward 2B is molded into a substantially J band shape as described above. This process is 5 steps.

(8) A mark is attached and sorted.

As can be seen from the above description, according to the present embodiment, since the lead frame is used as the lead, the strength of the output 2B can be strengthened.

In addition, a part of the insulating film 3 is attached to the main surface of the semiconductor chip 1 with an adhesive agent 4, and another part of the insulating film 3 is attached to the inner lead 2A or the supporting lead 5. ), The tip of the electrode pad 1A and the inner lead 2A provided on the main surface of the semiconductor chip 1 are electrically connected to the bonding wire 6, and the mold resin ( 7), the thickness of the insulating film tape 3 is less than or equal to the loop height of the bonding wire 6, so that a thin semiconductor device of a TOC package having a thickness of about 0.5 mm can be obtained.

The wire bonding has a reverse bonding wire structure in which the ball side of the bonding wire 6 is provided on the inner lead 2A and the non-ball side is provided on the semiconductor chip 1 using the ball bonding method. In addition, since the bonding surface of the inner lead is located below the main surface of the semiconductor chip, the mold resin provided on the upper side of the bonding wire 6 can be reduced, whereby a thinner ultra-thin semiconductor device can be obtained.

Further, by bending the outer 2B to have the above-described portion 2B2 to lengthen the entire length of the outer 2B and making it elastic, the stress caused by the temperature cycle can be absorbed. Cracks can be prevented from occurring.

In the above embodiment, as shown in FIG. 5, light incidence blocking means such as aluminum foil 10 is provided on the main surface of the semiconductor chip 1, or as shown in FIG. ) Is mounted so as to face the mounting substrate 11 so as to block light incidence to the main surface of the semiconductor chip 1. Since light incidence to the main surface of the semiconductor chip 1 can be prevented by providing such light incidence blocking means, deterioration of characteristics such as data retention due to light can be prevented even in an ultra-thin semiconductor device. Can be.

7 is a cross-sectional view of an essential part for explaining the structure of a laminate according to a second embodiment of the present invention.

As shown in Fig. 7, the laminate of the present embodiment has a structure in which the thin semiconductor device of the TOC package of the first embodiment is stacked in two stages.

In the memory device of this embodiment, in both semiconductor devices, although the ball side of the bonding wire 6 is provided with the inner lead 2A and the non-ball side is the reverse bonding wire provided with the semiconductor chip 1, The bonding wire 6 of the thin semiconductor device may have a reverse bonding wire structure, and the bonding wire 6 of the upper thin semiconductor device may have a bonding wire structure.

As can be seen from the above description, according to the present embodiment, a large-capacity memory device as thin as 1 mm can be obtained even when the ultra-thin semiconductor devices are stacked together.

In addition, although the laminated body of the structure which laminated | stacked the two-stage semiconductor device was demonstrated in this Example, what can be made into the laminated body of the structure laminated | stacked in multiple stages can be easily estimated.

In addition, as a laminated body, you may laminate | stack the semiconductor device shown in FIG. 5 in multiple stages.

Next, a method of configuring a module structure by mounting the semiconductor device and the laminated body of each of the above embodiments on a substrate will be described. First, a method of mounting the semiconductor device of the first embodiment or the fifth embodiment, for example, the semiconductor device of the first embodiment, on a substrate will be described with reference to FIG.

(1) First, a solder paste is applied to a portion of the surface L of the printed board 1 corresponding to the M portion (outer surface of 2B5) of the semiconductor device or the outer package 2B of the semiconductor package.

(2) The semiconductor device is mounted on a printed board and soldered (for example, reflow soldering). In this way, the semiconductor device is mounted on a substrate.

Next, a case where the semiconductor device is stacked in two stages will be described with reference to FIG.

(1) First, a solder paste is applied to the N portion (outer surface of 2B3) of the outlet 2B of the semiconductor device A mounted on the substrate as described above.

(2) Then, the other semiconductor device B is mounted on the semiconductor device A, and soldered. By performing such a process in opposition, it becomes possible to laminate | stack a semiconductor device two or more steps on a board | substrate. In addition, after mounting the semiconductor device B on the semiconductor device A and soldering the N part, the semiconductor device in which these are integrated may be mounted on a substrate.

Next, as a semiconductor device, as shown in FIG. 10, for example, the mounting method on the substrate of the solder plating layers 12A and 12B having a thickness of, for example, 20 mu m in the entirety of the outer portion will be described. do. In this case, the semiconductor device is mounted on the substrate as shown in FIG. 10, and then heated to a temperature (for example, 195 ° C. or higher) at which the solder plating layer can be melted so that the plating layer of the M portion is melted and soldered. In addition, the thickness of the solder plating layer is preferably about 20 μm so that the formation of the outlier is easily performed.

The case where the semiconductor device provided with such a solder plating layer is laminated | stacked in two stages is demonstrated. In this case, as shown in FIG. 11, two semiconductor devices are mounted on the substrate 11 in two stages, and then heated at the above temperature, whereby the solder plating layers of the N and M portions are melted and soldered. In such a method, the soldering process can be completed in one step regardless of the number of stages of the semiconductor device. In addition, when laminating a semiconductor device, after mounting a semiconductor device on a board | substrate, preheating about 190 degreeC may melt | dissolve a solder plating layer slightly, and after fixing these semiconductor devices and board | substrates, you may make it heat above 195 degreeC.

In the case where two stages of semiconductor memory devices such as DRAM are stacked as semiconductor devices, two lead pins for the chip selector are increased (added) to each semiconductor device. Therefore, when N semiconductor devices of the above embodiments are stacked as a memory, N lead pins for the chip selector are increased for each semiconductor device.

As described above, as shown in FIGS. 2, 3, 5 to 9, 10, and 11 except for FIG. It is omitted from the illustration in which the plating layer is provided at a thickness.

In each of the embodiments, the plating layer of each of the outliers may be provided only at the portion where the outward soldering is performed, or may be provided only at the outer side (for example, 12B in the example of FIG. 10).

In each embodiment, the silver plating layer 12C as shown in Figs. 10 and 11 is provided in the portion where the inner leads are bonded.

Next, some embodiments of the module structure in which the semiconductor device of the above embodiment is mounted on a substrate with high density will be described.

12 is an embodiment of a modular structure in which semiconductor devices stacked in multiple stages, for example, two stages, are arranged in multiple rows, for example, two rows. The semiconductor devices A and B in one of the two rows have positively bent outwards as shown in FIG. 9 or 11, and the semiconductor devices C and D in the other row are As shown in Fig. 6, it has an outward bend outward. In this case, the pin numbers of the outliers of the semiconductor devices A and B and the outliers of the semiconductors C and D facing the same are, for example, 1 pin to 10 pin. Therefore, for example, the wiring length when connecting 1 pin of the semiconductor devices A and B and 1 pin of the semiconductor devices C and D can be shortened, thereby reducing noise and simultaneously reducing data. This speeds up the processing. In addition, high-density mounting of the semiconductor device becomes possible, and therefore the memory capacity can be increased in the same space as in the prior art.

Next, a method of assembling such a module structure will be described. First, the case where the outdent of each semiconductor device is a normal thing like FIG. 8, FIG. 9 is demonstrated.

As one method, first, the semiconductor devices A and B in one row are soldered as in the assembly method of the laminate of FIG. 9, and then the semiconductor devices C and D in the other row are Soldering is performed to solder these two rows of laminates to the substrate 11, and at the same time, two surface rows of the semiconductor devices 2B4 facing each other. In this case, a solder paste is applied to the surface P of FIG. 8 of the outward solder.

Alternatively, after soldering the semiconductor devices B and D to the substrate, the semiconductor devices A and C may be laminated and soldered onto the semiconductor devices B and D, respectively. .

On the other hand, when the outward of each semiconductor device has the solder plating layers 12A and 12B as shown in Fig. 10, the entire semiconductor devices A to D are made as in the embodiment of Fig. 11 as shown in Fig. 11. After arranging together with a tile, soldering can be performed collectively.

In addition, although the laminated body laminated | stacked in two layers was arrange | positioned in two rows in the Example of FIG. 12, you may apply this Example to having arrange | positioned multiple rows of the semiconductor device of one layer, and in that case, it may be a ball | bowl inverse. It is good to alternately arrange the semiconductor device which has a bent outward. The present embodiment can also be applied to a case where a plurality of stacks of three or more semiconductor devices are stacked, and in this case, a stack having an outward bent or reversed bend is alternately arranged laterally. Do it.

FIG. 13 shows an embodiment of a module structure in which semiconductor devices stacked in multiple stages, for example four stages, are arranged in multiple rows, for example, two rows. Each of the semiconductor devices (A) to (D) and (E) to (H) of the two rows of stacked bodies is soldered to the substrates 21 and 31. Preferably, all the outliers of each of the semiconductor devices (A) to (D) and (E) to (H) are tennis bent or reverse bent. In this case, 1 pin to 10 pins of the outliers of the semiconductor devices A to E are soldered to the same substrate, for example, the substrate 31, as 1 pin to 10 pins of the outlets of the semiconductor devices E to H. For example, the wiring length when connecting 1 pin of the semiconductor devices A to D and 1 pin of the semiconductor devices E to H can be shortened. Therefore, as in the embodiment of Fig. 12, the noise can be reduced and the data can be speeded up. In addition, high-density mounting of the semiconductor device becomes possible, and therefore the memory capacity can be increased in the same space as in the prior art.

Next, a method of assembling such a module structure will be described. First, the case where the outdent of each semiconductor device is a normal thing like FIG. 8, FIG. 9 is demonstrated.

As one method, first, the semiconductor devices (A) to (D) in one row are soldered as in the method of assembling the laminate of FIG. 9, and then the semiconductor devices (E) to (H) in the other row are connected in the same manner. The two-row laminates are soldered to the substrates 21 and 31, respectively. When soldering to the substrates 21 and 31, soldering paste is applied to the surface P of FIG.

On the other hand, when the outliers of the semiconductor devices have the solder plating layers 12A and 12B as shown in FIG. 10, all semiconductor devices A to H are removed as in the case of the embodiment of FIG. After arranging as shown in 13 degree | times, soldering can be performed collectively.

In addition, although each of the above embodiments applies the present invention to a TOC package, the present invention can also be applied to fixing a semiconductor chip and an inner lead directly with an adhesive without using an insulating film tape.

As mentioned above, although the invention made by this inventor was demonstrated concretely based on the said Example, this invention is not limited to the said Example, Of course, various changes are possible in the range which does not deviate from the summary.

Claims (39)

A semiconductor chip having an upper side and a lower main surface and a side surface extending between the upper and lower main surfaces, wherein the upper main surface includes an electrode pad, and first and second portions disposed around the semiconductor chip. An inner lead having two portions, each having a first surface and a second surface, the second surface having an adhesive portion attached to the upper main surface of the semiconductor chip, and each of the first portions of the inner lead; An insulating tape including a portion attached to the substrate by an adhesive, the electrode pad disposed on the upper main surface of the semiconductor chip, and the second portions of the inner leads corresponding to the electrode pads. And a mold resin for sealing the semiconductor chip, the inner lead, the electrode pad, the insulating film tape, and the bonding wire. The height from the upper main surface to the first surface of the insulating film tape is lower than the height from the upper main surface of the semiconductor chip to the apex of the bonding wire and each of the inner leads connected to the bonding wire. The surface of the second portion is located lower than the upper main surface of the semiconductor chip, and is located between the upper main surface of the semiconductor chip and the lower main surface of the semiconductor chip opposite the upper main surface, each of the inner leads. And the first portion is disposed around the side of the semiconductor chip and separated from the semiconductor chip. The bonding wire of claim 1, wherein the bonding wire is attached to the inner lead by a ball bonding method, and each ball of the bonding wire is provided on the inner lead, and each end of the bonding wire facing the ball is formed. The thin semiconductor device, characterized in that provided in the corresponding one electrode pad. The thin semiconductor device according to claim 1, wherein the surface of each of the first portions of the inner lead to which the insulating film tape is attached is located at substantially the same level as the upper main surface of the semiconductor chip. The thin semiconductor device according to claim 1, wherein each of the inner leads extends outward in a direction perpendicular to the main surface of the mold resin at substantially a central portion thereof. The thin semiconductor device according to claim 1, wherein the insulating film tape has a thickness thinner than the thickness of the inner layer. The thin semiconductor device according to claim 1, wherein the insulating film tape is made of polyimide resin. A semiconductor chip having an upper main surface, a lower main surface facing the upper main surface, and a side surface extending between the upper main surface and the lower main surface, wherein the upper main surface includes an electrode pad; A first inner lead and a second inner lead, a first surface, and a second surface opposite to the first surface, wherein the second surface is a portion attached to the upper main surface of the semiconductor chip; An insulating film including a portion attached to a first inner lead, a bonding wire electrically connecting the electrode pad of the upper main surface of the semiconductor chip to the second inner lead, the semiconductor chip, and the first And a mold resin sealing a sealing of the insulating tape and the insulating wire, and a second inner lead, wherein the first surface of the insulating tape is formed on the upper main surface of the semiconductor chip. The height of the edge is lower than the height from the upper main surface of the semiconductor chip to the apex of the bonding wire, and the surface of the second inner lead connected to the bonding wire is located lower than the upper main surface of the semiconductor chip. And the first and second inner leads are arranged around the side surface of the semiconductor chip and separated from the semiconductor chip. 8. The thin semiconductor device according to claim 7, wherein the insulating film tape has a thickness thinner than the thicknesses of the first and second inner leads. 8. The thin semiconductor device according to claim 7, wherein the insulating tape is made of polyimide resin. A main surface, a back surface facing the main surface, and a side surface extending from the main surface to the back surface, wherein the main surface has a semiconductor chip and an inner lead and an outer lead respectively having a semiconductor element and an external terminal, and the inner The lead includes a plurality of leads arranged adjacent to the side surface of the semiconductor chip, a bonding wire for electrically connecting the external terminal and the inner lead, a first portion disposed on the main surface of the semiconductor chip, and the semiconductor. Means for supporting said semiconductor chip having a second portion external to said chip, said second portion having a top surface and a bottom surface opposite said top surface, said bottom surface being adhesively attached to said main surface of said semiconductor chip; And a mold resin for sealing the semiconductor chip, the inner lead of the plurality of leads, the bonding wire, and the means. The inner lead of the semiconductor chip is disposed in the thickness direction of the semiconductor chip between the main surface and the rear surface of the semiconductor chip, and the height from the main surface of the semiconductor chip to the upper surface of the means is the main surface of the semiconductor chip. And lower than a height to a vertex of the bonding wire in the semiconductor device. The semiconductor device according to claim 10, wherein said means comprises a chip support lead. 12. The semiconductor device according to claim 11, wherein one end of the chip support lead terminates at an interface between the inside and the outside of the mold resin. The semiconductor device according to claim 12, wherein the chip support lead has a step portion between the side surface of the semiconductor chip and the interface of the mold resin. The semiconductor device according to claim 13, wherein said one end of said chip support lead is located at substantially the same level as said plurality of leads in said thickness direction of said semiconductor chip. The semiconductor device according to claim 10, wherein the back surface of the semiconductor chip is in contact with the mold resin. It has a main surface, a back surface facing the main surface and a side extending from the main surface to the back surface, and has a pair of long edge and a pair of short edge, the main surface of the rectangular shape having a semiconductor element and an external terminal A plurality of leads arranged along a pair of long edges, each having an inner lead and an outer lead, wherein the inner lead is disposed adjacent to the side surface of the rectangular semiconductor chip; Bonding wires for electrically connecting an external terminal to the inner lead, and first and second means for supporting the rectangular semiconductor chip, wherein the first means is a pair of one pair of shorter ones outside the rectangular semiconductor chip. Extends through the edge to the main surface of the rectangular semiconductor chip, the second means being a peninsula of the rectangular shape Extends from the outside of the sieve chip to the main surface of the rectangular semiconductor chip past the pair of other short edges, each of the first and second means disposed on the main surface of the rectangular semiconductor chip A first portion and a second portion external to the rectangular semiconductor chip, each of the first means and the first portion of the second means has an upper surface and a lower surface opposite the upper surface, the first means and Each of said bottom surface of said second means is attached to said main surface of said rectangular shape semiconductor chip with an adhesive, said first means and said second means, said rectangular shape semiconductor chip, said inner lead of said plurality of leads. A rectangular mold resin for sealing a bonding wire and the first and second means, the pair of long along the pair of long edges of the rectangular semiconductor chip A rectangular mold resin having a side and a pair of short sides along the pair of short edges of the rectangular-shaped semiconductor chip, wherein the plurality of leads and the outer leads protrude out from the pair of long sides of the rectangular mold resin And the inner leads of the plurality of leads are disposed in a thickness direction of the rectangular semiconductor chip between the main surface and the rear surface of the rectangular semiconductor chip, and the first lead on the main surface of the rectangular semiconductor chip. The height to each said upper surface of a 1st and 2nd means is a semiconductor device lower than the height from the said main surface of the said rectangular semiconductor chip to each vertex of the said bonding wire. 17. The semiconductor device according to claim 16, wherein said first means comprises a first chip support lead and said second means comprises a second chip support lead. 18. The method of claim 17, wherein one end of the first chip support lead ends at one of the pair of short sides of the mold resin, and one end of the second chip support lead is formed of the pair of mold resins. A semiconductor device characterized by ending on the other of the short sides. 19. The second chip support according to claim 18, wherein the first chip support lead has a stepped portion between the one of the pair of short side faces of the mold resin and the side face of the rectangular semiconductor chip. And a lead has a stepped portion between the other one of the pair of short side faces of the mold resin and the side face of the rectangular semiconductor chip. 20. The semiconductor device according to claim 19, wherein each of said one end of said first and second chip support leads is located at substantially the same level as said plurality of leads in said thickness direction of said rectangular semiconductor chip. Semiconductor device. The semiconductor device according to claim 16, wherein the back surface of the rectangular semiconductor chip is in contact with the mold resin. And a main surface, a back surface facing the main surface and a side surface extending from the main surface to the back surface, wherein the main surface has a semiconductor chip and an inner lead and an outer lead each having a semiconductor element and an external terminal. An inner lead is disposed adjacent to the side surface of the semiconductor chip, each of the inner leads has a plurality of leads having an upper surface and a lower surface opposite the upper surface, the external terminals and the inner leads are electrically connected to each other; A bonding wire in contact with the upper surface of the inner lead, a first portion disposed on the main surface of the semiconductor chip, and a second portion external to the semiconductor chip, wherein the first portion includes the upper surface and the Means for supporting the semiconductor chip having a lower surface opposite the upper surface, wherein the lower surface is attached to the main surface of the semiconductor chip with an adhesive; A sieve chip, a mold resin for sealing the inner lead, the bonding wire, and the means of the plurality of leads, wherein the upper surface of the inner lead of the plurality of leads is formed in the thickness direction of the semiconductor chip. And a height from the main surface of the semiconductor chip to the upper surface of the means is lower than a height from the main surface of the semiconductor chip to the apex of the bonding wire. 23. A semiconductor device according to claim 22, wherein said means comprises a chip support lead. 24. The semiconductor device according to claim 23, wherein one end of the chip support lead terminates at an interface between an inside and an outside of the mold resin. The semiconductor device according to claim 24, wherein the chip support lead has a stepped portion between the side surface of the semiconductor chip and the interface of the mold resin. The semiconductor device according to claim 25, wherein said one end of said chip support lead is located at substantially the same level as said plurality of leads in said thickness direction of said semiconductor chip. 27. The semiconductor device according to claim 26, wherein the back surface of the semiconductor chip is in contact with the mold resin. And a main surface, a back surface facing the main surface and a side surface extending from the main surface to the back surface, wherein the main surface has a semiconductor chip and an inner lead and an outer lead each having a semiconductor element and an external terminal. Inner leads are arranged adjacent to the side surface of the semiconductor chip, a bonding wire for electrically connecting the external terminal and the inner lead, and the main surface of the semiconductor chip is disposed on the main surface A member extending outwardly of the semiconductor chip and having a top surface and a bottom surface opposite the top surface, wherein the bottom surface is attached to the main surface of the semiconductor chip with an adhesive; An inner lead, a bonding wire, and a mold resin for sealing the member, wherein the inner leads of the plurality of leads are formed of the semiconductor chip. And a height from the main surface of the semiconductor chip to the upper surface of the member, the height being lower than the height from the main surface of the semiconductor chip to the apex of the bonding wire in the thickness direction. 29. A semiconductor device according to claim 28, wherein said member comprises a chip support lead. 30. The semiconductor device according to claim 29, wherein one end of the chip support lead terminates at an interface between the inside and the outside of the mold resin. The semiconductor device according to claim 30, wherein the chip support lead has a stepped portion between the side surface of the semiconductor chip and the boundary surface of the mold resin. 32. The semiconductor device according to claim 31, wherein said one end of said chip support lead is located at substantially the same level as said plurality of leads in said thickness direction of said semiconductor chip. The semiconductor device according to claim 28, wherein a back surface of the semiconductor chip is in contact with the mold resin. (New) A resin sealing body and a to-be-sealed body to be sealed by the resin sealing body, comprising: a first surface, a second surface facing the first surface, a plurality of semiconductor elements formed on the first surface, and A plurality of leads each having a sealed body having a plurality of external terminals, each of the inner lead and the outer lead formed integrally with the inner lead, the end portion of the inner lead of the inner lead is opposite to the outer lead of the sealed body. And a plurality of leads positioned in the periphery, and a first portion and a second portion integrally formed with the first portion, wherein the sealed portion supporting means for supporting the sealed body is the first portion. Sealed body support means disposed on a first surface of the sieve and wherein the second portion is disposed outside the sealed body, and end portions of the inner leads of the plurality of leads and the plurality of external terminals. Accessing A plurality of bonding wires, the sealed body, the inner lead, the plurality of bonding wires, and the sealed body supporting means are sealed by the resin sealing body, and the outliers of the plurality of leads are sealed. Protrudes outward from the sieve, and an end portion of the inner lead is located in the thickness direction of the sealed body such that the upper surface of the inner lead is located below the first surface of the sealed body. Is disposed between the first surface and the second surface of the sealed body so that the lower side of the inner lead is positioned above the second surface of the sealed body in the thickness direction of the The lower side of the first portion is adhered to the first surface of the sealed body by an adhesive, and the upper side of the first portion of the sealed body supporting means is lower than the vertices of the plurality of bonding wires. A semiconductor device, characterized in that positioned. (New) The semiconductor device according to claim 34, wherein the sealed body supporting means includes a support lead of a chip constituting the sealed body. (New) The semiconductor device according to claim 35, wherein one end of the chip support lead terminates at an interface between the inside and the outside of the resin sealing member. (New) The semiconductor device according to claim 36, wherein the chip support lead has a stepped portion between a side surface of the resin sealing member and the boundary surface of the resin sealing member. (New) The semiconductor device according to claim 37, wherein said one end of said chip support lead is located at substantially the same height as said inner lead in the thickness direction of said sealed body. (New) The semiconductor device according to claim 34, wherein the second surface of the resin sealing body is in contact with the resin sealing body.