JP2934119B2 - Semiconductor device, laminate, and module structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
It relates to a micro-module structure, in particular, a memory card, or a thin semiconductor device which is applied to the semiconductor device in the mass memory device such as a compact package stacked in multiple stages, it
Laminated body and module structure using the same
Things.

[0002]

As a small package of a conventional thin semiconductor device, the 1.2mm was adopted tabbed lead frame and wire bonding thickness TSOP (T hin S moll
O ut-line P ackege) type have been developed. This is described in, for example, GINE83 issued by Hitachi, Ltd.

A large-capacity memory card has been developed in which a TSOP type thin semiconductor device is mounted on both sides of a 3.3 mm thick memory card to maximize the mounting efficiency.
However, due to strong demand for thinner TSOP type,
0.5mm thick TCP with the same external size as OP type
(T ape C arrier P ackege) type have been proposed. Regarding this, for example, Nikkei Microdevice, 1991
February, pp. 65-66. This TCP
Type thin semiconductor device, a semiconductor chip is thinner about 0.2 mm, the semiconductor chip and the inner lead are electrically connected by bonding TAB (T ape A utmated B ondenge ) method, is composed of a plastic molded structure You.

Further, the thickness of the package is reduced by bonding an element holder made of a thin heat-resistant resin molded from polyimide to a part of the main surface (element forming surface) of the semiconductor chip and a part of the inner lead, respectively. Is disclosed in Japanese Patent Application Laid-Open No. 4-109694. In this device, when the electrodes of the semiconductor chip and the inner leads are connected by a bonding wire (thin metal wire), the distance between the end of the semiconductor chip and the bonding wire is increased so as not to cause a short circuit. And the upper surface of the inner lead are flush with each other.

Japanese Patent Laid-Open Publication No. Hei 3-261153 discloses a semiconductor device in which inner leads made of a metal film are arranged on an insulating tape, and a lower surface of a part of the insulating tape supports a main surface of a semiconductor chip. It is described in.

A semiconductor device in which a tab portion (die pad portion) of a lead frame is arranged on a main surface of a semiconductor chip and the semiconductor chip is supported by the tab portion is disclosed in Japanese Patent Laid-Open Publication No. HEI 1 (1993) -1995.
No. 286342.

[0007]

The present inventor has studied the TCP type thin semiconductor device adopting the above-mentioned TAB method, and has found the following problems.

(1) Since the outer leads are made of copper (Cu) foil, the strength of the outer leads is low. Therefore, the lead is bent and a contact failure occurs.

(2) Since the strength of the outer lead is weak,
Sorting sockets is difficult.

[0010] (3) Since the use of carbon Dinh grayed the TAB method, more expensive as compared to the bonding of the lead frame method.

In Japanese Patent Application Laid-Open No. 4-109694, since the main surface of the semiconductor chip and the upper surface of the inner lead are flush with each other, when connecting the electrode of the semiconductor chip and the inner lead with a bonding wire, The loop height of the bonding wires (the height from the main surface of the semiconductor chip to the vertex in the vertical direction) is increased, and a thin package cannot be obtained. Further, even if the bonding wires are connected by wire reverse bonding, the package cannot be made sufficiently thin because the main surface of the semiconductor chip and the upper surface of the inner lead are on the same plane.

In JP-A-3-261153, since the upper surface of the inner lead is located above the main surface of the semiconductor chip, the loop height of the bonding wire is increased, and a thin package cannot be obtained.

In Japanese Patent Application Laid-Open No. 1-286342, a die pad portion thicker than a resin tape is provided on a main surface of a semiconductor chip, and an upper surface of an inner lead is positioned above a main surface of a semiconductor chip. Therefore, the loop height of the bonding wire is increased, and a thin package cannot be obtained.

An object of the present invention, 0.5 mm thickness of about thin type semiconductor device is to provide a laminate and module structure using it using the same.

Another object of the present invention is to provide a lead frame outer lead high strength 0.5mm thickness of about thin semiconductor device using the laminate and the module structure using it using the same is there.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A semiconductor chip, a plurality of inner leads each having a tip portion facing a side surface of the semiconductor chip, a plurality of electrode pads formed on one main surface of the semiconductor chip, and the plurality of inner leads. A plurality of wires connecting the semiconductor chip and the plurality of electrode pads; a chip supporting means having a semiconductor chip suspension lead connected to one main surface of the semiconductor chip; the semiconductor chip; and the plurality of inner leads And a resin sealing body for sealing the wires and the chip supporting means, wherein one main surface of the semiconductor chip and the semiconductor chip hanging lead supporting surface are supported on the same plane, and the upper surface of the inner lead connecting the wires is the semiconductor than one main surface of the chip located on another major surface of one main surface facing the semiconductor chip, the inner leads of the resin sealing body thickness of half I and the outer lead projecting from the release line
That is a semiconductor device.

(2) A semiconductor chip, a plurality of inner leads each having a tip portion facing a side surface of the semiconductor chip, a plurality of electrode pads formed on one main surface of the semiconductor chip, and the plurality of inner leads. A plurality of wires connecting the semiconductor chip and the plurality of electrode pads; a chip supporting means having a semiconductor chip suspension lead connected to one main surface of the semiconductor chip; the semiconductor chip; and the plurality of inner leads And a resin sealing body for sealing the wires and the chip supporting means, wherein one main surface of the semiconductor chip and the semiconductor chip hanging lead supporting surface are supported on the same plane, and the upper surface of the inner lead connecting the wires is The semiconductor chip is located on another main surface side opposite to the one main surface of the semiconductor chip with respect to the one main surface of the semiconductor chip, and the wire is a bonding wire.
Set the ball side on the inner lead (1st bond),
Is provided on the semiconductor chip (second bond),
Narido is a semiconductor device comprising a collision <br/> out to outer leads from half the distance line of the resin sealing body thickness.

(3) A semiconductor chip, a plurality of inner leads each having a tip portion facing a side surface of the semiconductor chip, a plurality of electrode pads formed on one main surface of the semiconductor chip, and the plurality of inner leads. A plurality of wires connecting the semiconductor chip and the plurality of electrode pads; a chip supporting means having a semiconductor chip suspension lead connected to one main surface of the semiconductor chip; the semiconductor chip; and the plurality of inner leads , and a resin sealing body which seals the wires and the chip support means, said one main surface of the semiconductor chip suspension leads supporting surface of the semiconductor chip is supported in the same plane, the upper surface of the inner lead connecting the wire The one inner surface of the semiconductor chip is located on the other main surface side opposite to the one main surface of the semiconductor chip ;
Externally protruding from the side or half the thickness line
The outer lead includes a first portion protruding from the resin sealing body, a second portion bent upward from the first portion, and a first portion bent from the second portion. A third portion extending in the same direction as the extending direction, a fourth portion bent downward from the third portion, and a fifth portion extending from the fourth portion toward the resin sealing body.
Is a semiconductor device made.

(4) A semiconductor chip, a plurality of inner leads each having a tip portion facing a side surface of the semiconductor chip, a plurality of electrode pads formed on one main surface of the semiconductor chip, and the plurality of inner leads. A plurality of wires connecting the semiconductor chip and the plurality of electrode pads; a chip supporting means having a semiconductor chip suspension lead connected to one main surface of the semiconductor chip; the semiconductor chip; and the plurality of inner leads , and a resin sealing body which seals the wires and the chip support means, said one main surface of the semiconductor chip suspension leads supporting surface of the semiconductor chip is supported in the same plane, the upper surface of the inner lead connecting the wire The semiconductor chip is located on another main surface side opposite to the one main surface of the semiconductor chip with respect to the one main surface of the semiconductor chip, and the wire is a bonding wire.
Set the ball side on the inner lead (1st bond),
Is provided on the semiconductor chip (second bond),
The knurled lead protrudes from a line half the thickness of the resin seal.
Out and become an outer lead, the outer lead is
A first portion protruding from the resin sealing body, a second portion bent upward from the first portion, and a second portion extending from the second portion in the same direction as the extending direction of the first portion. 3 portion and a fourth portion bent downwardly from a portion of the third is a semi-conductor device Do that from the fifth portion extending toward the resin sealing body from a portion of the fourth.

(5) A semiconductor chip, a plurality of inner leads each having a tip portion facing a side surface of the semiconductor chip, a plurality of electrode pads formed on one main surface of the semiconductor chip, and the plurality of inner leads. A plurality of wires connecting the semiconductor chip and the plurality of electrode pads; a chip supporting means having a semiconductor chip suspension lead connected to one main surface of the semiconductor chip; the semiconductor chip; A resin sealing body for sealing the leads, the wires and the chip supporting means, wherein the upper surface of the inner lead to which the wires are connected faces one main surface of the semiconductor chip more than one main surface of the semiconductor chip located in the other main surface, wherein in
The knurled lead is a side line of the resin sealing body or a distance line of half the thickness
An outer lead protruding from above, wherein the outer lead includes a first portion protruding from the resin sealing body, a second portion bent upward from the first portion, and the second portion.
A third portion extending in the same direction as the extension direction of the first portion from the third portion, a fourth portion bent downward from the third portion, and the resin sealing body from the fourth portion. A stacked body in which a plurality of semiconductor devices each having a fifth portion extending therefrom is stacked.

(6) In the laminate, the upper semiconductor
Fifth portion of outer lead of device and underlying semiconductor device
Is connected to the third part of the outer lead of
It is a laminated body laminated.

(7) A plurality of semiconductor devices are mounted on a substrate.
Mount the mounted module structure or the laminate on a substrate
It is a mounted module structure.

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for explaining the embodiments, parts having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

FIG. 1 shows a TOC according to a first embodiment of the present invention.
FIG. 2 is a plan view showing a schematic configuration of a thin semiconductor device employing a package structure in which an upper portion of a mold resin is removed;
Is a cross-sectional view taken along the line II-II shown in FIG. 1, and FIG.
FIG. 4 is a cross-sectional view taken along the line III-III shown in FIG. 1; FIG. 4 is a view showing a modification of the first embodiment in which the supporting form by the insulating film tape is changed; FIG. 5 is a semiconductor chip of the first embodiment; FIG. 6 is a cross-sectional view showing a configuration of a modification in which a light incident blocking unit such as an aluminum foil is provided on the main surface of the semiconductor chip. FIG. 6 is mounted so that the main surface of the semiconductor chip of the first embodiment faces the mounting substrate. FIG. 7 is a cross-sectional view showing the state, FIG. 7 is a cross-sectional view showing a stacked body according to a second embodiment in which the thin semiconductor devices of the first embodiment are stacked in two stages, and FIG. FIG. 9 is a cross-sectional view for explaining a mounting method, FIG. 9 is a cross-sectional view for explaining a method for mounting the thin semiconductor device of the first embodiment on a substrate in two stages, and FIG. FIG. 11 is a sectional view for explaining another example of mounting on a substrate.
Is a cross-sectional view for explaining another method of mounting the thin semiconductor device of the present invention on a substrate in two steps, FIG. 12 is a perspective view showing an embodiment of a module structure using the thin semiconductor device of the present invention, FIG. 13 is a perspective view showing another embodiment of the module structure using the thin semiconductor device of the present invention.

The thin semiconductor device of the first embodiment (TOC (Tape
As shown in FIGS. 1 and 2, each of a plurality of inner leads (inner portions of the leads 2) 2 </ b> A has a planar shape near the peripheral edge of the semiconductor chip 1. It is arranged. A part of the insulating film tape 3 formed in a stripe shape is attached to the main surface of the semiconductor chip 1 with an adhesive 4. Other portions of the insulating film tape 3 are attached to some of the suspension leads 5 of the plurality of inner leads 2A. In the case where the suspension lead 5 is provided, for example, the other portion of the insulating film tape 3 is attached to at least one suspension lead 5 with the adhesive 4. A plurality of electrode pads 1A are arranged on the main surface of the semiconductor chip 1,
Each of the plurality of electrode pads 1A is electrically connected to each of the corresponding plurality of inner leads 2A via a bonding wire 6. These semiconductor chip 1, inner lead 2A, insulating film tape 3, bonding wire 6, etc. are molded resin (resin-sealed body) 7
It is sealed with. That is, the thin semiconductor device has a TOC package structure.

As shown in FIGS. 3 and 4, the insulating film tape 3 for supporting the semiconductor chip 1 is used to prevent the semiconductor chip 1 from being twisted (tilted) or moved during molding. Preferably at least 4 points,
Alternatively, the suspension lead 5 is supported at at least three points. That is,
If supported in four points, a cross-shaped insulating film tape 3, for example shown by the solid line and dotted lines used in Figure 4, it may be supported lead 5 hanging at its 4 tips section, also supported at three points If you want to, for example, T-shaped insulating film tape 3 shown by the solid line reference in FIG. 4, Li hanging at the three top end portion
The card 5 may be supported. In this case, when at least one suspension lead 5 is provided, the suspension lead 5 may be supported by at least one end of the insulating film tape 3.

As the insulating film tape 3, for example, a polyimide resin is used, and as the adhesive 4,
For example, a polyimide resin or an epoxy resin is used. The thickness of the insulating film tape 3 is equal to or less than the height from the main surface of the semiconductor chip 1 to the top of the bonding wire 6 (hereinafter, referred to as a loop height). For example, as shown in FIG. , Including the thickness of the adhesive 4. The thickness dimension of each part other than the insulating film tape 3 is, for example, the lower surface of the mold resin 7.
The thickness from the (back side) to the semiconductor chip 1 is 0.10 mm, the thickness of the semiconductor chip 1 is 0.28 mm, and the thickness from the main surface of the semiconductor chip 1 to the upper surface of the mold resin 7 is 0.12 mm. The distance between the mold and the lower surface of the mold resin 7 is 0.03 mm.

As the mold resin 7, for example, an epoxy resin to which a phenol-based curing agent, silicone rubber and a filler are added is used in order to reduce stress.

The bonding wire 6 is bonded by a ball bonding method, and the ball side of the bonding wire 6 is provided on the inner lead 2A ( first button).
The non-ball side is provided on the semiconductor chip 1 ( second bond ). In this way, reverse bonding ( this
Ri by the fact that the loading process is referred to as Bath wire bonding) to, model improves reliability, also if there is no problem in terms of reliability, the bonding wires 6 of the mall
Since the amount of the resin 7 can be reduced, the thickness can be further reduced. Therefore, whether to perform the reverse bonding ( Leavage wire bonding ) or the normal bonding as described above may be selected according to the thickness requirement of the thin semiconductor device. In addition, the inner lead 2A
Is a distance line that is half the thickness of the mold resin (resin sealing body) 7
Amount of resin sealing body projecting from above and above and below the semiconductor chip
Are the same. By doing this,
The amount of resin sealing body above and below the semiconductor chip is the same
Influence of stress due to temperature cycling on semiconductor devices
Can be reduced.

Further, as is apparent from FIG. 2, the bonding surface (upper surface) of the inner lead 2A is located below the main surface of the semiconductor chip 1 and the back surface (lower surface) thereof facing the bonding surface of the inner lead 2A. Is located above the back surface opposite to the main surface of the semiconductor chip 1. Thereby, the loop height of the bonding wire 6 can be further reduced, and the wire length of the bonding wire 6 can be further reduced.

The tip (suspension lead 5) of the inner lead 2A to which the insulating film tape 3 is attached is bent out of the plurality of inner leads 2A, as shown in FIG. Since it is arranged at the same height as the above, it is easy to attach the insulating film tape 3.

As shown in FIG. 2, the leads 2 protrude from the mold resin 7, that is, substantially from the center in the thickness direction of the package.

The outer lead 2B has a portion 2B1 protruding substantially parallel to the main surface of the semiconductor chip 1 from a substantially central portion in the thickness direction of the package, and a portion 2B2 bent toward the main surface of the semiconductor chip 1 thereafter. And thereafter, a portion 2B3 substantially flush with the package surface on the main surface side of the semiconductor chip 1, and a portion which is then bent to the side opposite to the main surface of the semiconductor chip 1 and becomes substantially perpendicular to the main surface of the semiconductor chip 2B4, and thereafter, a portion 2B5 facing the package and having substantially the same height as the surface of the package on the side opposite to the main surface of the semiconductor chip 1. Preferably, the lower surface of the portion 2B5 of the outer lead 2B protrudes from the lower surface of the mold resin (package) 7 by about 0.03 mm. Thereby, when soldering the thin semiconductor device to the substrate at the time of mounting on the substrate, the portion 2B5 of the outer lead 2B can be reliably soldered to the substrate even if the substrate is warped or distorted.

In the case where the thin semiconductor device is soldered on the substrate and laminated on the upper side as shown in FIGS. 9 and 11, the portion 2B4 of the outer lead 2B does not need to be substantially perpendicular to the main surface. Alternatively, the semiconductor chip 1 may be inclined from a plane perpendicular to the main surface.

[0045] Incidentally, the outer leads 2B is, FIG. 2 and symmetrical, may be formed from substantially the center of the package thickness direction so bent back surface side of the semiconductor chip 1 (see FIG. 6). Such an outer lead 2B is herein referred to as a reverse bent outer lead 2B, and the one shown in FIG. 2 is referred to as a forward bent outer lead 2B.

As described above, the outer lead 2B is substantially
Since the outer lead 2B is bent in a bend shape, the overall length of the outer lead 2B can be increased and elasticity can be provided. With this configuration, the elasticity of the outer leads 2B absorbs stress due to temperature cycles during soldering during mounting on the board, so cracks are formed in the solder at the connection portions with the wiring pads on the mounting board. This can be prevented from occurring.

Each of the inner lead 2A and the outer lead 2B is formed integrally with the lead frame before the cutting and forming step. This lead frame is, for example, F
It is formed of an e-Ni (e.g., Ni content of 42 or 50 [%]) alloy, Cu, or the like.

Next, the assembly process of the thin semiconductor device of this embodiment will be briefly described.

The steps of assembling the thin semiconductor device of the present embodiment are performed in the following order. (1) The insulating film tape 3 is attached and fixed to some of the suspension leads 5 of the plurality of inner leads 2A supported by the lead frame with the thermoplastic adhesive 4. (2) The semiconductor chip 1 is attached and fixed to the insulating film tape 3 with a thermoplastic adhesive 4 (pelleting). (3) The lower base is evacuated to fix the semiconductor chip 1, and wire bonding is performed. (4) The whole is molded with resin (resin) and sealed. (5) Each outer lead 2B is subjected to a solder plating process, and a solder plated layer having a thickness of, for example, about 10 μm is provided on the entire outer lead 2B. (6) A cutting process for cutting the outer leads 2B from the lead frame is performed. (7) Each outer lead 2B is formed into a substantially J-bend shape as described above. The man-hour for this processing is five steps. (8) Mark and sort.

As can be seen from the above description, according to this embodiment, since the lead frame is used as the lead, the strength of the outer lead 2B can be increased. Further, a part of the insulating film tape 3 is adhered to the main surface of the semiconductor chip 1 with an adhesive 4, and the other part of the insulating film tape 3 is attached to some of the plurality of inner leads 2 </ b> A or the suspension leads 5. The electrode pad 1A provided on the main surface of the semiconductor chip 1 and the tip of the inner lead 2A are electrically connected to each other by a bonding wire 6, and the semiconductor chip 1, the inner The leads 2A, the insulating film tape 3, the bonding wires 6 and the like are sealed with the mold resin 7,
Since the thickness of the insulating film tape 3 is equal to or less than the loop height of the bonding wire 6, a thin semiconductor device of a TOC package having a thickness of about 0.5 mm can be obtained.

The wire bonding is performed by a ball bonding method, and has a reverse bonding wire structure in which the ball side of the bonding wire 6 is provided on the inner lead 2A and the non-ball side is provided on the semiconductor chip 1. . Furthermore, the bonding surface (upper surface) of the inner lead 2A
Since is located below the main surface of the semiconductor chip 1, the amount of the mold resin 7 provided above the bonding wires 6 can be reduced, so that a thinner ultra-thin semiconductor device can be obtained.

The outer lead 2B is connected to the portion 2B
In addition, since the outer lead 2B is curved so as to have a longer overall length and has elasticity, stress due to temperature cycling can be absorbed, thereby preventing cracks from occurring in the solder during mounting. be able to.

Further, in the above-described embodiment, as shown in FIG.
For example, as shown in FIG. 6, a semiconductor chip 1 is mounted so that the main surface of the semiconductor chip 1 faces the mounting substrate 11 to block light from entering the main surface of the semiconductor chip 1. To do it. By providing the light incidence blocking means as described above, it is possible to prevent light from being incident on the main surface of the semiconductor chip 1, and thus to prevent deterioration of characteristics such as data retention due to light even in an ultra-thin semiconductor device. be able to.

Next, a second embodiment of the present invention will be described with reference to the drawings.

As shown in FIG. 7, the laminate of this embodiment is
The structure is such that the thin semiconductor device of the TOC package of the first embodiment is stacked in two stages.

In the laminated body of this embodiment, in both thin semiconductor devices, the ball side of the bonding wire 6 is provided on the inner lead 2A, and the non-ball side is an inverted bonding wire provided on the semiconductor chip 1. However, the bonding wire 6 of the lower thin semiconductor device may have an inverted bonding wire structure, and the bonding wire 6 of the upper thin semiconductor device may have a normal bonding wire structure.

As can be seen from the above description, according to the present embodiment, a thin laminate of about 1 mm can be obtained even when super-thin semiconductor devices are stacked.

Although the present embodiment has been described with respect to a laminated body having a structure in which thin semiconductor devices are stacked in two stages, it can be easily predicted that a laminated body having a structure in which thin semiconductor devices are further stacked in multiple stages can be obtained. I can do it.

As the laminate, thin semiconductor devices provided with the light incident shielding means shown in FIG. 5 may be stacked in multiple stages.

Next, a method of mounting the thin semiconductor device and the laminate of each of the above embodiments on a substrate to form a module structure will be described.

First, a method of mounting the thin semiconductor device of the first embodiment on a substrate will be described with reference to FIG.

(1) First, a solder paste is applied to a portion (region) corresponding to the M portion of the outer lead 2B of the thin semiconductor device in the mounting surface L of the substrate (for example, a printed wiring board) 11.

(2) Next, the thin semiconductor device is mounted on the mounting surface L of the substrate 11 and soldered (for example, solder reflow)
I do. Thus, the thin semiconductor device is mounted on the substrate.

Next, a case where thin semiconductor devices are stacked in two stages will be briefly described with reference to FIG.

(1) First, a solder paste is applied to the N portion of the outer lead 2B of the thin semiconductor device (A) mounted on the substrate 11 as described above.

(2) Next, another thin semiconductor device (B) is mounted on the thin semiconductor device (A) and soldered. By repeating such a process, thin semiconductor devices can be stacked in two or more stages on the mounting surface L of the substrate 11.

After mounting the thin semiconductor device (B) on the thin semiconductor device (A) and soldering the N portion, the integrated thin semiconductor device (laminate) is mounted on the mounting surface L of the substrate 11. It may be mounted on top.

Next, as a thin semiconductor device, as shown in FIG.
A method for mounting a thin semiconductor device provided with solder plating layers 12A and 12B of about μm on a substrate will be described.

In this case, as shown in FIG.
The thin semiconductor device is mounted on the mounting surface L, and then the solder plating layers 12A and 12B are melted at a temperature (for example, 1 ° C.).
(95 ° C or more) to heat the outer lead 2B.
The part melts and soldering is performed. The solder plating layer 12
The thickness of A and 12B is preferably about 20 μm so that the outer lead 2B can be easily formed.

Next, a case where thin semiconductor devices having the solder plating layers 12A and 12B provided on the outer leads 2B are stacked in two stages will be described with reference to FIG.

In this case, as shown in FIG. 11, a two-stage thin semiconductor device in which a thin semiconductor device (B) is stacked on a thin semiconductor device (A) is mounted on a mounting surface L of a substrate 11, Thereafter, by heating at the above-described temperature, the solder plating layers 12B of the N portion and the M portion are melted and soldering is performed. In such a method, the soldering step can be performed once regardless of the number of stages of the thin semiconductor device. When stacking the thin semiconductor devices, after the thin semiconductor devices are mounted on the substrate, preliminary heating is performed at a temperature of about 190 ° C. to slightly melt the solder plating layer, and these thin semiconductor devices and the substrate 11
May be heated at a temperature of about 195 ° C.

As a thin semiconductor device, for example, DRA
When two layers of thin semiconductor devices with M are stacked,
The number of lead pins for chip select is increased (added) by two for each thin semiconductor device. Therefore, when the thin semiconductor devices of the embodiments are stacked in N stages as a memory,
The number of lead pins for chip select is increased by N for each thin semiconductor device.

As described above, FIGS. 2, 3 and FIGS. 5 to 9 except for FIGS. 10 and 11 also show FIGS.
1, each outer lead 2B has about 10 μm.
The plating layer is provided with a thickness of about m, but is not shown.

Further, in each embodiment, the plating layer of each outer lead 2B may be provided only on the portion where the outer lead 2B is soldered, or may be provided only on the outer side of the outer lead 2B.

In each embodiment, the parts where the inner leads 2A are bonded are shown in FIGS.
As shown in FIG. 1, a silver plating layer 12C may be provided.

Next, several embodiments of a module structure in which the thin semiconductor device of the above embodiment is mounted on a substrate at high density will be described.

FIG. 12 shows an embodiment of a module structure in which, for example, thin semiconductor devices stacked in two stages are arranged in two rows, for example.

Thin semiconductor device in one of two rows
Each of (A) and (B) has a positive bending outer lead 2B as shown in FIG. 9 or FIG. 11, and each of the thin semiconductor devices (C) and (D) in the other row is shown in FIG. As shown, it has a reverse bending outer lead 2B. In this case, the thin semiconductor device
Each of the outer leads 2B of (A) and (B) and each of the outer leads 2 of the thin semiconductor devices (C) and (D) opposed thereto.
The pin numbers of B are, for example, the same from 1 Pin to 10 Pin. Therefore, for example, the wiring length when connecting each Pin of the thin semiconductor devices (A) and (B) to each Pin of the thin semiconductor devices (C) and (D) can be shortened, thereby reducing noise. And at the same time, speed up the data. In addition, since high-density mounting of a thin semiconductor device becomes possible, the memory capacity can be increased in the same space as that of the related art.

Next, a method of assembling the module structure will be described.

First, the case where the outer leads of each thin semiconductor device are normal as shown in FIGS. 8 and 9 will be described.

As one method, first, in the same manner as in the method of assembling the laminated body in FIG.
(A) and (B) are soldered together, and then the other row of thin semiconductor devices (C) and (D) are soldered together in the same manner,
While soldering these two rows of laminates to the substrate 11,
Outer leads 2 facing each other of two rows of thin semiconductor devices
The respective portions 2B4 of B are soldered to each other. in this case,
Solder paste is applied to the surface P shown in FIG. 8 by soldering.

As another method, a thin semiconductor device
After soldering (A) and (C) to the substrate, the thin semiconductor device (B) and the thin semiconductor device (C) are placed on the thin semiconductor device (A).
Each of the thin semiconductor devices (D) may be stacked and soldered thereon.

On the other hand, as shown in FIG. 10, the outer leads 2B of each thin semiconductor device have the solder plating layers 12A, 12B
Is provided, as in the embodiment of FIG.
After arranging all the thin semiconductor devices (A) to (D) as shown in FIG. 12, soldering can be performed collectively.

In the embodiment shown in FIG. 12, the stacked body having two layers is arranged in two rows. However, this embodiment may be applied to a case where a single thin semiconductor device is arranged in a plurality of rows in the horizontal direction. In that case, thin semiconductor devices having forward and reverse bent outer leads 2B may be alternately arranged. In addition, the present embodiment can be applied to a case where a plurality of thin layers of three or more thin semiconductor devices are stacked in a plurality of rows. In this case, the stack having the outer leads 2 </ b> B is bent alternately in the lateral direction. Just place them.

FIG. 13 shows an embodiment of a module structure in which thin semiconductor devices stacked in, for example, four stages are vertically arranged in, for example, two rows.

Each of the thin semiconductor devices (A) to 2-row laminates
The outer leads 2B of (D) and (E) to (H) are soldered to the substrates 21 and 31. Preferably, the outer leads 2B of each of the thin semiconductor devices (A) to (D) and (E) to (H) are all bent forward or backward. In this case, 1 Pin to 10 Pin of the outer leads 2B of the thin semiconductor devices (A) to (D)
Is soldered to the same substrate as the outer leads 2B of each of the thin semiconductor devices (E) to (H), for example, the substrate 31. For example, 1 Pin of each of the thin semiconductor devices (A) to (D) and each thin The wiring length when connecting to 1 Pin of the semiconductor devices (E) to (H) can be shortened. Accordingly, noise can be reduced as in the embodiment of FIG. 12, and data can be processed at high speed.
In addition, high-density mounting of a thin semiconductor device becomes possible, so that a memory capacity can be increased in the same space as that of a conventional semiconductor device.

Next, a method of assembling the module structure thus configured will be described.

First, the case where the outer lead 2B of each thin semiconductor device is a normal one as shown in FIGS. 8 and 9 will be described.

As one method, first, the thin semiconductor device in one row is formed in the same manner as in the method of assembling the stacked body in FIG.
(A) to (D) are soldered to each other, and then the thin semiconductor devices (E) to (H) in the other row are soldered to each other by the same method,
These two rows of laminates are soldered to the substrates 21 and 31, respectively. When soldering to the substrates 21 and 31, soldering is performed by applying a solder paste to the surface P of the outer lead 2B shown in FIG.

On the other hand, as shown in FIG. 10, the outer leads 2B of each thin semiconductor device have the solder plating layers 12A, 12B
Is provided, as in the embodiment of FIG.
After all the thin semiconductor devices (A) to (H) are arranged as shown in FIG. 13, soldering can be performed collectively.

As described above, the invention made by the present inventor is:
Although the present invention has been described in detail with reference to the embodiment, the present invention is not limited to the embodiment, and it is needless to say that various changes can be made without departing from the scope of the invention.

[0092]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

[0093] (1) 0.5 mm thickness of about thin type semiconductor device, it is possible to provide a laminated body and the module structure using it using the same.

[0094] (2) lead frame outer lead high strength 0.5mm thickness of about thin semiconductor device using, its
Laminate with Les and module structure using it
Can be provided.

(3) Curve the outer lead to reduce the total length
By extending the length and having elastic force, the semiconductor
Stress caused by temperature cycling when soldering
It can absorb, so it can be
Cracks may occur in the solder connecting the connection part of the
Can be prevented.

(4) The insulating film tape is attached
The upper surface of part of the inner lead (suspension lead) is semiconductor
Since it is located on the same surface as the main surface of the chip, the inner lead
Can be easily pasted with insulating film tape
You.

[0097]

[0098]

[0099]

[0100]

[Brief description of the drawings]

FIG. 1 is a plan view showing a schematic configuration of a thin semiconductor device employing a TOC package structure according to a first embodiment of the present invention in a state where an upper portion of a mold resin is removed.

FIG. 2 is a sectional view taken along the line II-II shown in FIG.

FIG. 3 is a sectional view taken along the line III-III shown in FIG. 1;

FIG. 4 is a view showing a modified example in which the supporting form by the insulating film tape of the first embodiment is changed.

FIG. 5 is a cross-sectional view illustrating a configuration of a modification in which a light incident blocking unit such as an aluminum foil is provided on the main surface of the semiconductor chip of the first embodiment.

FIG. 6 is a sectional view showing a state in which the semiconductor chip of the first embodiment is mounted so that the main surface side faces the mounting substrate.

FIG. 7 is a sectional view showing a stacked body according to a second embodiment in which the thin semiconductor devices according to the first embodiment are stacked in two stages.

FIG. 8 is a sectional view for explaining a method of mounting the thin semiconductor device of the first embodiment on a substrate.

FIG. 9 is a sectional view for explaining a method of mounting the thin semiconductor device of the first embodiment on a substrate in two stages.

FIG. 10 is a cross-sectional view for explaining another example of mounting the thin semiconductor device of the present invention on a substrate.

FIG. 11 is a sectional view for explaining another method for mounting the thin semiconductor device of the present invention on a substrate in two stages.

FIG. 12 is a perspective view showing an embodiment of a module structure using the thin semiconductor device of the present invention.

FIG. 13 is a perspective view showing another embodiment of the module structure using the thin semiconductor device of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 1A ... Electrode pad, 2 ... Lead, 2
A: inner lead, 2B: outer lead, 3: insulating film tape, 4: adhesive, 5: suspension lead, 6: bonding wire, 7: mold resin, 10: aluminum foil, 11: mounting board.

Continued on the front page (56) References JP-A-3-192736 (JP, A) JP-A-4-23460 (JP, A) JP-A-4-56336 (JP, U) (58) Fields surveyed (Int) .Cl. ⁶ , DB name) H01L 23/50 H01L 21/60 H01L 25/10

Claims (10)

(57) [Claims] 1. A semiconductor chip, and a plurality of inner leads having a front end facing a side surface of the semiconductor chip;
A plurality of electrode pads formed on one main surface of the semiconductor chip, a plurality of wires connecting the plurality of inner leads and the plurality of electrode pads, and a semiconductor chip suspension connected to the one main surface of the semiconductor chip A chip supporting means having leads, a resin sealing body for sealing the semiconductor chip, the plurality of inner leads, wires, and the chip supporting means; one main surface of the semiconductor chip and a semiconductor chip suspending lead supporting surface; There is supported on the same plane, the upper surface of the inner lead connecting the wires, than said one main surface of the semiconductor chip located in another major surface of one main surface facing the semiconductor chip, said inner leads Is a semiconductor device characterized in that it protrudes from a distance line that is half the thickness of the resin sealing body to become an outer lead . 2. A semiconductor chip, and a plurality of inner leads each having a tip portion facing a side surface of the semiconductor chip,
A plurality of electrode pads formed on one main surface of the semiconductor chip, a plurality of wires connecting the plurality of inner leads and the plurality of electrode pads, and a semiconductor chip suspension connected to the one main surface of the semiconductor chip A chip supporting means having leads, a resin sealing body for sealing the semiconductor chip, the plurality of inner leads, wires, and the chip supporting means; one main surface of the semiconductor chip and a semiconductor chip suspending lead supporting surface; Are supported on the same plane, and the upper surface of the inner lead connecting the wires is located on the other main surface side opposite to the one main surface of the semiconductor chip with respect to the one main surface of the semiconductor chip. Inner the ball side of the bonding wire
Provided on the lead (first bond) and the non-ball side
A semiconductor device , wherein the inner lead protrudes from a distance line that is half the thickness of the resin sealing body to form an outer lead . 3. A semiconductor chip, and a plurality of inner leads having a front end portion facing a side surface of the semiconductor chip,
A plurality of electrode pads formed on one main surface of the semiconductor chip, a plurality of wires connecting the plurality of inner leads and the plurality of electrode pads, and a semiconductor chip suspension connected to the one main surface of the semiconductor chip a chip support means having a lead, said semiconductor chip, said plurality of inner leads, and resin sealing body which seals the wires and chip support means
Has the one main surface of the semiconductor chip suspension leads supporting surface of the semiconductor chip is supported by the same plane, the upper surface of the inner lead connecting the wires, one of the semiconductor chips of the semiconductor chip than the one main surface of the The inner lead is located on another main surface side opposite to the main surface,
An outer lead protruding from a side surface of the resin sealing body, wherein the outer lead includes a first part protruding from the resin sealing body, a second part bent upward from the first part, and a second part. A third portion extending in the same direction as the extension direction of the first portion from the third portion, a fourth portion bent downward from the third portion, and the resin sealing body from the fourth portion. wherein a and Turkey such and a fifth portion towards extending. 4. A semiconductor chip, and a plurality of inner leads each having a tip portion facing a side surface of the semiconductor chip,
A plurality of electrode pads formed on one main surface of the semiconductor chip, a plurality of wires connecting the plurality of inner leads and the plurality of electrode pads, and a semiconductor chip suspension connected to the one main surface of the semiconductor chip a chip support means having a lead, said semiconductor chip, said plurality of inner leads, and resin sealing body which seals the wires and chip support means
Has the one main surface of the semiconductor chip suspension leads supporting surface of the semiconductor chip is supported by the same plane, the upper surface of the inner lead connecting the wires, one of the semiconductor chips of the semiconductor chip than the one main surface of the The inner lead is located on the other main surface side opposite to the main surface, and the inner lead is a distance line of half the thickness of the resin sealing body.
An outer lead protrudes from above, and the outer lead includes a first portion protruding from the resin sealing body, a second portion bent upward from the first portion, and a second portion bent from the second portion. A third portion extending in the same direction as the extending direction of the first portion, a fourth portion bent downward from the third portion, and a fifth portion extending from the fourth portion toward the resin sealing body. wherein a and Turkey, such from a part of. 5. A semiconductor chip and a side of the semiconductor chip.
A plurality of inner leads having a tip facing the surface;
A plurality of electrode pads formed on one main surface of the semiconductor chip
And the plurality of inner leads and the plurality of electrode pads.
A plurality of wires for connecting the semiconductor chip and one main surface of the semiconductor chip
Support having semiconductor chip suspension leads connected to the chip
Holding means, the semiconductor chip, and the plurality of inner leads
And a resin sealing body for sealing the wire and the chip supporting means.
And one main surface of the semiconductor chip and a semiconductor chip suspension lead support.
The holding surface is supported on the same plane, and the upper surface of the inner lead connecting the wire is
One main surface of the semiconductor chip rather than one main surface of the conductor chip;
The wire is located on the other opposing main surface side, and the ball side of the bonding wire is the inner side.
Provided on the lead (first bond) and the non-ball side
(In the second bond), make sure that the inner lead is on a distance line that is half the thickness of the sealing body.
Projecting from the resin sealing body to form an outer lead.
1 part and a second part bent upward from the first part.
And a direction in which the first portion extends from the second portion.
A third portion extending in the same direction, and a lower portion extending from the third portion;
A fourth portion that bends into the resin portion and the resin portion from the fourth portion.
And a fifth portion extending toward the sealing body.
Semiconductor device. 6. A semiconductor chip and a side of the semiconductor chip.
A plurality of inner leads having a tip facing the surface;
A plurality of electrode pads formed on one main surface of the semiconductor chip
And the plurality of inner leads and the plurality of electrode pads.
A plurality of wires for connecting the semiconductor chip and one main surface of the semiconductor chip
Support having semiconductor chip suspension leads connected to the chip
Holding means, the semiconductor chip, and the plurality of inner leads
And a resin sealing body for sealing the wire and the chip supporting means.
And the upper surface of the inner lead to which the wire is connected is the half
One main surface of the semiconductor chip rather than one main surface of the conductor chip;
The inner lead is located on the other opposing main surface side and protrudes from the side surface of the resin sealing body.
The outer lead is made of the resin
A first portion protruding from the sealing body and an upper portion from the first portion;
A second part bent toward the second part and the second part
A third portion and a front portion extending in the same direction as the extension direction of the first portion;
A fourth portion bent downward from the third portion and the fourth portion;
Fifth portion extending from portion 4 toward the resin sealing body
That a plurality of semiconductor devices having different
Laminate to be featured . 7. A semiconductor chip, and a plurality of inner leads each having a tip portion facing a side surface of the semiconductor chip;
A plurality of electrode pads formed on one main surface of the semiconductor chip, a plurality of wires connecting the plurality of inner leads and the plurality of electrode pads, and a semiconductor chip suspension connected to the one main surface of the semiconductor chip A chip supporting means having leads; and a resin sealing body for sealing the semiconductor chip, the plurality of inner leads, wires, and the chip supporting means. The upper surface of the inner leads to which the wires are connected is the semiconductor chip. Is located on the other main surface side opposite to the one main surface of the semiconductor chip with respect to the one main surface, and the inner lead is a distance line of half the thickness of the resin sealing body.
An outer lead protrudes from above, and the outer lead is formed of a first portion protruding from the resin sealing body, a second portion bent upward from the first portion, and the first portion from the second portion. A third portion extending in the same direction as the extending direction of the portion, a fourth portion bent downward from the third portion, and a fifth portion extending from the fourth portion toward the resin sealing body. A stacked body comprising a plurality of stacked semiconductor devices. 8. The stacked body according to claim 6 , wherein the fifth portion of the outer lead of the upper semiconductor device is connected to the third portion of the outer lead of the lower semiconductor device. A laminate characterized in that: 9. The method of claim 1 or module structure, characterized in that a plurality of serial <br/> mounting of the semiconductor device in any one mounted on the board out of 5. 10. A module structure, wherein the laminate according to claim 6 is mounted on a substrate.