JP2834676B2 - Semiconductor assembly - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor assembly which can be stacked, and more particularly, to a semiconductor assembly which can be applied to a stacked module structure and on which a heat sink or a capacitor plate can be mounted.

[0002]

2. Description of the Related Art
The D-package (Three-Dimensional Package) has been developed with the trend of increasing the capacity, speed, and miniaturization of electronic devices. One.

The above-mentioned 3-D packages can be roughly classified into four types: a semiconductor chip stacked type, a semiconductor package stacked type, a multi-chip module stacked type, and a wafer state KGD die stacked type.

Most companies that manufacture 3-D packages classified as above provide the semiconductor chip stacked type or the semiconductor package stacked type. Among them, the semiconductor chip stacked type can realize miniaturization, large capacity and high speed, but have problems such as low yield, high cost, and long development period.

Although the semiconductor package stacked type has an excellent effect as compared with the semiconductor chip stacked type, the general two-layer type is generally used.
There are the following disadvantages compared to the -D package.

First, there is a problem due to the vertical connection. In order to perform the lamination, many other processes must be added after the existing semiconductor package process.

Second, there is a problem due to heat release during device operation. For example, a heat sink is mounted on one package through another process to facilitate heat release.
A strategy must be adopted that can be equipped with another cooling device for heat release. For this reason, there is a problem in that the package capacity is increased and high-density mounting is impossible, and additional cost must be borne by mounting the heat releasing means.

FIGS. 17 to 19 show an embodiment of the above-described prior art in detail. FIG. 17 shows an example of a conventional stacked semiconductor package.
FIG. 3 is a cross-sectional view of “3-D memory device using exclusive process” manufactured by Staktek.

Referring to FIG. 17, in the stacked semiconductor package, first, a package body 11 is laminated in a four-layer structure, and leads 12 protruding outside the package body 11 are electrically connected by a connector 13. Connecting. At the time of operation of the next element, a metal foil is laminated on the upper and lower surfaces of the package body 11 by a thin plate so that heat is easily released, or the package body 11 laminated as shown in FIG. Package ground heat sink 1
4 are formed.

However, in such a stacked type semiconductor package, metal foils must be stacked on the upper and lower surfaces of the package body 11 for heat dissipation, or the die pad region must be extended and projected to the upper surface for heat release. ,
There is a disadvantage that it is very complicated as compared with the conventional semiconductor package process.

In addition, a new structure must be manufactured, for example, it is necessary to connect a core serving as a carrier to vertically connect the semiconductor package bodies 11, and the existing package manufacturing equipment is applied as it is. I ca n’t,
There are also problems with mass productivity.

FIGS. 18 (a) and 18 (b) are cross-sectional views showing another embodiment of the conventional stacked semiconductor package, which is the technical content disclosed in US Pat. No. 5,105,261. The stacked semiconductor package includes a bidirectional lead 22 projecting from a package body 21 to the outside.
Is formed into a Gull-Wing shape.

Next, as shown in FIG. 18A, the semiconductor package prepared as described above is
And mounted on both sides of two PCBs 23 having
At this time, as shown in FIG.
The gull wing-shaped bidirectional external lead 22 protruding outside 1 is soldered onto a PCB 23 by a braze 24. After this soldering, the assembly of the stacked semiconductor package is completed by inserting the “h” -shaped connecting socket 25 into the end of the PCB 23.

However, the stacked semiconductor package having such a structure has a high mounting height, it is difficult to improve the mounting density, and it is not easy to release heat. In addition, there is a limit to the number of packages that can be stacked due to the limitation of the lead pitch, and there is a problem that the adhesive strength is reduced in a region where the package and the PCB are vertically contacted and the structure is fragile.

FIG. 19 is a perspective view showing another embodiment of the conventional stacked semiconductor package, which relates to an SSIM (single in-line memory module) manufactured by RTB'S. As shown in FIG. 19, for the stacked semiconductor package, first, a semiconductor package is prepared in which a plurality of leads 32 projecting horizontally from a package body 31 are formed with pinholes.

Next, the semiconductor packages prepared as described above are sequentially stacked, and after covering the upper plate 33 and the lower plate 34, the pins 35 are inserted into the pin holes of the leads 32 from the lower part to the upper part.
Are inserted to fix the leads 32, thereby completing the stacking of the package. At this time, a pinhole is formed in the lower plate 34 so as to vertically penetrate on the same line as the pinhole of the lead 32.
The groove is formed so that it can occupy only a predetermined depth of the pin 35. Therefore, the end 36 of the pin 35 protruding downward from the lower plate 34 is mounted on a PCB (not shown).

As described above, in the stacked semiconductor packages, the bar-shaped pins 35 are inserted and employed as vertical connectors of the external leads 32. The finer pitches of the external leads 32 are inserted into the external leads 32. Since the thickness of the pin 35 is thin, it is difficult to mount the pin 35 on the PCB.

Therefore, the other external lead 36 is connected to the PC.
There is a disadvantage that a socket must be used for mounting on the B. Also, since the pins 35 are inserted into the external leads 32, the width of the external leads 32 becomes narrow, and the lamination limit is limited. is there.

[0019]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor assembly for a three-dimensional integrated circuit package capable of minimizing the manufacturing cost and the overall capacity as much as possible. is there.

It is another object of the present invention to provide a semiconductor assembly which is compatible with a high-density three-dimensional integrated circuit package.

It is another object of the present invention to provide a semiconductor assembly capable of realizing a high-density three-dimensional integrated circuit package without using any additional process.

It is another object of the present invention to provide a semiconductor assembly which is compatible with a reliable three-dimensional integrated circuit package.

It is another object of the present invention to provide a semiconductor assembly which can implement a reliable three-dimensional integrated circuit package in various forms.

Another object of the present invention is to provide a reliable three-dimensional integrated circuit package using a high-yield semiconductor assembly.

Another object of the present invention is to provide a high-density three-dimensional integrated circuit package that can reduce manufacturing costs.

It is still another object of the present invention to provide a method of manufacturing a reliable three-dimensional integrated circuit package which can reduce manufacturing costs.

[0027]

According to the present invention, there is provided a semiconductor assembly having a plurality of leads, the plurality of leads being formed on at least one side of the semiconductor assembly and exposing the plurality of leads. It is characterized by having pockets. These pockets can respectively receive a plurality of leads of an overlying semiconductor assembly for electrical connection when a plurality of the semiconductor assemblies constitute an integrated circuit package.

In another aspect of the present invention, a semiconductor assembly having a plurality of leads includes at least one edge recess extending along a side of the semiconductor assembly and exposing the plurality of leads. . The edge recess portion may receive a plurality of leads of an upper semiconductor assembly for electrical connection when a plurality of the semiconductor assemblies constitute a three-dimensional integrated circuit package.

Further, in a semiconductor assembly having another plurality of leads, an edge recess portion extending along at least one side of the semiconductor assembly and exposing an upper surface of the plurality of leads is provided; An upper recess provided on the upper surface of the semiconductor assembly and a lower recess provided on the lower surface of the semiconductor assembly. Here, when a plurality of the semiconductor assemblies constitute a three-dimensional integrated circuit package, an edge recess portion of a certain semiconductor assembly may connect a plurality of leads of the semiconductor assembly located above the semiconductor assembly for electrical connection. Acceptable. Further, when a plurality of the semiconductor assemblies constitute a three-dimensional integrated circuit package, a heat sink or a capacitor may be formed by one upper recess of the semiconductor assembly and a lower recess of the semiconductor assembly located above the semiconductor assembly. A space for receiving the plate can be formed. The capacitor plate includes a connection lead, two conductive foil foil sheets respectively connected to a power supply voltage and a ground voltage through the connection lead, and an insulating plate interposed between the two foil sheets. Preferably, the semiconductor assembly includes a trace for receiving the connection lead of the capacitor plate and communicating with the upper and lower recesses.

Further, in the three-dimensional integrated circuit package according to the present invention, a plurality of integrated circuit built-in assemblies having an edge recess portion extending along at least one side and exposing a plurality of leads; And a capacitor built-in assembly extending along one side to receive a plurality of leads and having at least one capacitor built therein. Here, the capacitor built-in assembly includes:
A first die pad having a ground voltage level; a second die pad electrically connected to a power supply voltage via at least one bonding wire and a lead;
A plurality of capacitor elements connected in parallel between the die pads.

[0031]

The pocket or the edge recess portion is configured so that a lead is exposed, and when the assembly forms a three-dimensional integrated circuit package, receives a lead belonging to an assembly located above and electrically receives the lead. Since the internal connection can be performed, the layers can be stacked with good reliability while minimizing the overall capacity without performing an additional step.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the term “module” means “three-dimensional structure integrated circuit package”.

FIG. 1 is a perspective view showing a first embodiment of a semiconductor assembly according to the present invention, and relates to a dual type package.

As shown in FIG. 1, a plurality of leads 43 of the assembly 41 of the semiconductor assembly are bent into a J shape as an SOJ type, and the upper surface thereof is exposed to form a lead region 42. And pocket 44
Are three vertically surrounding one end of the lead region 42.
The surface is formed in a rectangular shape. Read area 42
The pockets 44 are formed horizontally on the two opposite sides of the assembly body 41 along the same direction.

Although FIG. 1 shows a dual type package, the J-shaped lead 43 can be changed to another shape such as a quad type when applied to a QFP structure. . When applied to a quad type package, the pocket 4
4 can be disposed on four sides of the assembly body 41.
You. As a result, the pockets 44 exposing the lead regions 42 are provided in the same form of the assembly (package) 4.
1 serves as a groove for laminating 1 in a 3-D form.

FIG. 2 shows a state where the four assemblies shown in FIG. 1 are stacked on a PCB 57 to form a module.

In the assembly 41, leads 43 are connected to corresponding pads of the integrated circuit chip 52 via bonding wires 54. The integrated circuit chip 52 is provided on the die pad 51. A certain assembly 4
After the J-shaped lead 43 is received in the pocket 44 of the assembly 41 located below the assembly 41, the lead 43 is adhesively fixed by a known brazing reflow process. During this bonding, alignment jigs are used to ensure a secure electrical connection between the upper and lower assembly bodies 41 to the pockets 44, providing structural stability for support. The vertical height of the bent portion of the lead 43 can be adjusted by a bending tool or the like in relation to the structural state of the assembly body 41 to be stacked. For example, when stacking the package structure of the SOJ type, when the height of the assembly body 41 excluding the standoff is 3 mm, the surplus length of the J-shaped lead 43 of the pocket 44 becomes 0.7 mm. When the semiconductor assemblies (packages) are vertically stacked, the interval between the lower surface of the J-shaped lead 43 and the upper surface of the lead region 42 is 1 m.
m, but the length of the J-shaped lead 43 may be increased by about 1 mm and the molded position may be appropriately adjusted downward.

Further, TSOJ (Thin and Small Out-line)
In the case of the (J-bent) package, since the stand-off of the J-shaped lead to be molded is thicker than the thickness of the assembly (package), the position to be molded can be adjusted upward by reducing the length of the lead. I just need.

FIG. 3 is a perspective view showing a second embodiment of the semiconductor assembly according to the present invention. The assembly 61 shown in FIG. 3 is useful for a TSOJ package so that the leads adjacent to the upper surface of a lead region 62 located above the leads 63 of the assembly (package) 61 are completely exposed. , Edge recess portions 64 are formed on both sides of the lead region 62.

Although the structure shown in FIG. 3 is of a dual in-line package type, when applied to a quad type package, the edge recess portion 64 may be located on the four sides (four sides) of the assembly body 61. it can. Such an arrangement is advantageous for assemblies having a smaller lead-to-lead pitch than the assembly 41 shown in FIG.

FIG. 4 shows a state where the four assembly bodies shown in FIG. 3 are stacked on a PCB (not shown) to form a module. A J-shaped portion of a lead 63 of a certain assembly 61 has a corresponding edge recess 64 of the assembly 61 located below the assembly 61.
And the lower portion of the J-shaped portion is placed in the edge recess 64 by a known brazing reflow process.
The electrical connection between the upper and lower assembly bodies 61 is completed by being adhered to the exposed surface of 3, that is, the lead region 62.

FIG. 5 is a sectional view showing a semiconductor assembly 94 in a lamination form according to a third embodiment of the present invention. As shown in FIG. 5, in this embodiment,
The lead 95 is connected to the integrated circuit chip 92 by a down bonding method, which is applied when the size of the integrated circuit chip 92 mounted on the die pad 91 is large. That is, in the semiconductor assembly 94, the integrated circuit chip 92 is adhered to the lower surface of the die pad 91, and the bonding pads of the semiconductor chip 92 and the internal leads 93 are down-bonded. To form an assembly body (package body) 96. The upper surface of the lead 95 is completely exposed to form an edge recess 97.

FIG. 6 shows the semiconductor assembly 9 shown in FIG.
FIG. 5 is a cross-sectional view of a module (semiconductor device) laminated in a three-layer structure by applying the semiconductor device 94 to the edge recess portion 9 having the same structure as the lamination method described with reference to FIG.
7 shows a state of being vertically mounted and stacked.

FIG. 7 shows a structure in which heat sinks are mounted on upper and lower surfaces of an assembly body 110 of a semiconductor assembly. As shown in FIG. 7, the assembly 110 of this embodiment basically applies the basic structure of the semiconductor assembly shown in FIG. 1 or FIG.
Upper and lower recesses 11 on the upper and lower surfaces of
2 and 113, and an edge recess 114 at a position corresponding to the edge recesses 64 and 97 of the second and third embodiments. The lead 111 in the edge recess portion 114 is buried in the molding compound at a depth equivalent to its own thickness, as indicated by a broken line, and each upper surface is exposed.

The upper and lower recess portions 112 and 113 are shown in FIG.
8 has the same width in the horizontal direction as shown in FIG.
The heat sink 121 or 122 shown in FIG.
Alternatively, as shown in FIG.
2 and 113 are received in a space 124 formed by the two. The shape of the heat sinks 121 and 122 depends on the geometric structure of the space 124 formed during the lamination and the heat sink 12.
It is deformed due to the efficiency of the heat release function of 1,122 itself. The thickness of the heat sinks 121 and 122 depends on the thickness of the assembly. When the thickness of the SOJ type assembly is large, the heat sink 121, 1
In the case of the TSOJ type package, the thickness of the mold for forming the assembly at the time of stacking may be smaller, so that the thickness of the heat sink can be further increased. For example, when stacking a TSOJ type assembly, the upper and lower surfaces of the assembly are provided with a recess with a depth of 0.1 mm, that is, the upper and lower recesses 112 and 113 are formed with a depth of 0.1 mm to form a molding. If so, the thickness of the heat sink is about 0.2 mm.

The step of attaching the heat sink to the upper and lower recessed portions 112 and 113 is performed simultaneously with the lamination of the assembly, and contains silver Ag epoxy, which is an epoxy resin having excellent thermal conductivity, and a metal filler. Can be easily attached using epoxy.

FIG. 11 shows an electrical connection state when nine 16Mb DRAM integrated circuits 150 to 158 are stacked using one of the above-described embodiments of the present invention.

Referring to FIG. 11, each DRAM 150-
In 158, all pins except the data pins DQ0 to DQ35, that is, signal application pins (for example, output enable signal pins OE, address pins A0 to A11,
Write control signal pin W, column address strobe signal pin CAS, and column address strobe signal pin RA
S) is commonly used. Data pins are proportional to the number of semiconductor assemblies stacked in the module.

FIGS. 12 and 13 show an embodiment of a semiconductor assembly having a capacitor for ensuring electrical stability of input / output data.

The capacitor 161 is connected to the die pads 160, 1
70 are adhered in parallel. The die pad 160 is used as a ground voltage plate, and the die pad 170 is connected to the power supply voltage terminal Vcc through two internal leads 162. That is, a bonding wire 163 is provided between the die pad 170 having the Vcc potential and the internal lead 162 for electrical connection between the die pad 170 and the internal lead 162.
The cc terminal is connected. If the capacitance of one capacitor is 0.1 μF, the total capacitance of the four capacitors shown in FIG. 12 or FIG. 13 is 0.4 μF, which is equivalent to the nine-assembly module shown in FIG. Applicable.

As shown in FIG. 14, the assembly 167 including the capacitor shown in FIG. 13 is placed at the bottom of the module, and the assembly 61 including the integrated circuit is stacked above the assembly 167. Assembly and bonding methods are as described above.

The external structure of the assembly including the capacitor shown in FIG. 12 or 13 is the same as the external structure of the assembly 61 shown in FIGS. 3 and 4, but includes an integrated circuit stacked together. It can be formed differently according to the shape of the assembly body.

In the present invention, a capacitor plate 195 as shown in FIGS. 15A and 15B may be employed instead of the assembly 167 including the capacitor 161 shown in FIGS. it can.

Referring to FIGS. 15A and 15B, two metal foil sheets 191 and 192 are bonded to the upper and lower surfaces of the insulating plate 190, respectively.
Metal foil sheet 191 on top of insulating plate 190
Is connected to a power supply voltage Vcc through a lead 193, and the metal foil sheet 192 on the lower surface of the insulating plate 190 is connected to a ground voltage GND through a lead 194. The capacitor plate 195 shown in FIGS. 15 (a) and 15 (b) does not increase the overall height of the module and is suitable for mounting on or between assemblies containing integrated circuits. .

FIG. 16 shows the structure of an assembly 200 including an integrated circuit on which the capacitor plate 195 shown in FIGS. 15A and 15B can be mounted. As shown in FIG. 16, a metal foil trace 203 for receiving the leads 193 and 194 of the capacitor plate 195 on the upper and lower surfaces of the assembly 200.
The structure is the same as that of the assembly 110 shown in FIG. The height of the foil trace 203 is the same as the height of the upper and lower recesses 204 and 205. When the assembly 200 on which the capacitor plate 195 is mounted is stacked, the capacitor plate 1
Since 95 is located in the space formed by the lower recess 205 of the certain assembly 200 and the upper recess 204 of the assembly 200 located below the assembly 200, the volume increase of the entire module due to the capacitor plate 195 is limited. Absent.

The embodiments described above are only some examples of the present invention, and those skilled in the art are not limited to the present embodiments without departing from the technical idea of the present invention, and various modifications and changes may be made. It goes without saying that it is possible.

[0057]

Therefore, in order to manufacture a stacked module using the semiconductor assembly (package) for stacking according to the present invention, the existing package manufacturing process can be directly employed without any special additional process, and the stacking is easy.
In addition, the structure of the laminate is stable, which has the effect of reducing costs.

The present invention also relates to SOJ or TSOJ
The present invention can be applied to a semiconductor package of a type and all other types of packages that can be stacked. In particular, by attaching a heat sink, the present invention can be applied to various semiconductor devices having excellent heat releasing ability.

Further, in the present invention, external tests and inspections can be easily performed, and another socket and a supplementary device for mounting the stacked semiconductor assemblies (packages) are not required.

When stacking the semiconductor assembly (package) of the present invention, an assembly (package) obtained by mounting at least one capacitor on a plurality of die pads and molding with epoxy resin is used.
By stacking with another package stacked on D, electrical characteristics which are problematic in this kind of stacking can be improved, and the characteristics of various elements can be compensated.

Further, according to the present invention, a flat metal foil is formed on the upper and lower surfaces of the recesses formed on the upper and lower surfaces of the assembly body (package body). By disposing the capacitors described above, various types of semiconductor packages can be realized.

According to the present invention, it is possible to realize high-density mounting without reducing the yield of the device by applying the existing package manufacturing process as it is, to simplify the structure and reduce the defect rate. There are advantages that can be done.

As described above, when manufacturing a stacked semiconductor device according to the present invention, various types of semiconductor packages can be vertically stacked by applying the existing process without adding any special equipment. In addition, the electrical characteristics of the semiconductor device which is regarded as a problem in stacking can be compensated in various forms.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a semiconductor assembly according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a state in which a module stacked in a four-layer structure by applying the semiconductor assembly shown in FIG. 1 is mounted on a PCB.

FIG. 3 is a perspective view illustrating a semiconductor assembly according to a second embodiment of the present invention;

FIG. 4 is a cross-sectional view of a module stacked in a four-layer structure by applying the semiconductor assembly shown in FIG. 3;

FIG. 5 is a sectional view showing a semiconductor assembly according to a third embodiment of the present invention.

FIG. 6 is a cross-sectional view of a module stacked in a three-layer structure by applying the semiconductor assembly shown in FIG. 5;

FIG. 7 is a side view showing an outer shape of a semiconductor assembly on which a heat sink according to the present invention is mounted.

8A and 8B are perspective views showing a heat sink that can be mounted on the semiconductor assembly shown in FIG. 7;

9 is a cross-sectional view of a module stacked in a three-layer structure by applying the semiconductor assembly on which the heat sink shown in FIG. 8A is mounted.

10 is a cross-sectional view of a module stacked in a three-layer structure by applying the semiconductor assembly on which the heat sink shown in FIG. 8B is mounted.

FIG. 11 is a functional block diagram showing an electrical connection state of the stacked module according to the present invention.

FIG. 12 is a plan view showing a semiconductor assembly having a capacitor mounted on a die pad according to the present invention.

FIG. 13 is a vertical sectional view specifically showing the semiconductor assembly shown in FIG. 12;

14 is a cross-sectional view showing a module in which the semiconductor assembly shown in FIG. 13 and the semiconductor assembly shown in FIG. 3 are stacked in a four-layer structure.

FIGS. 15A and 15B are a cross-sectional view and a plan view showing a capacitor that can be disposed on the upper and lower surfaces of the semiconductor assembly shown in FIG.

FIG. 16 is a side view showing an outer shape of a semiconductor assembly in which the capacitor shown in FIG. 15 can be provided.

FIG. 17 is a cross-sectional view showing a conventional stacked semiconductor module.

18 (a) and (b) are an overall cross-sectional view and a partial detailed cross-sectional view of another conventional laminated module different from that shown in FIG.

FIG. 19 is a perspective view showing another conventional stacked module different from those shown in FIGS. 17 and 18;

[Explanation of symbols]

41, 61, 96, 110, 167, 200 Assembly 43, 63, 95, 111, 193, 194 Lead 44 Pocket 64, 97, 114 Edge recess 92 Integrated circuit chip 94 Semiconductor assembly 112, 204 Upper recess 113, 205 Lower recess 121, 122 Heat sink 124 Space 160, 170 Die pad 161 Capacitor 191, 192 Metal foil sheet 195 Capacitor plate 203 Foil trace

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-7-235636 (JP, A) JP-A-2-239651 (JP, A) JP-A-6-97355 (JP, A) JP-A-7-235 66364 (JP, A) Hikaru Hei 3-103561 (JP, U) Hiko 5-33016 (JP, Y2) (58) Field surveyed (Int. Cl. ⁶ , DB name) H01L 25/00-25 / 18

Claims (3)

(57) [Claims] 1. A semiconductor assembly having a plurality of leads, an edge recess portion extending along at least one side of the semiconductor assembly and exposing an upper surface of the plurality of leads; When a plurality of semiconductor assemblies including an upper recess provided on an upper surface and a lower recess provided on a lower surface of the semiconductor assembly constitute a three-dimensional integrated circuit package, one upper recess of the semiconductor assembly is provided. A semiconductor assembly, wherein a lower recess of the semiconductor assembly located above the semiconductor assembly forms a space for receiving a heat sink. 2. A semiconductor assembly having a plurality of leads, an edge recess portion extending along at least one side of the semiconductor assembly and exposing upper surfaces of the plurality of leads; When a plurality of semiconductor assemblies including an upper recess provided on an upper surface and a lower recess provided on a lower surface of the semiconductor assembly constitute a three-dimensional integrated circuit package, one upper recess of the semiconductor assembly is provided. A semiconductor assembly, wherein a lower recess portion of the semiconductor assembly located above the semiconductor assembly forms a space for receiving a capacitor plate. 3. The capacitor plate includes a connection lead, two conductive foil sheets respectively connected to a power supply voltage and a ground voltage through the connection lead, and an insulating plate interposed between the two foil sheets. 3. The semiconductor assembly according to claim 2, further comprising: a trace receiving the connection lead of the capacitor plate and communicating with the upper and lower recesses, respectively. 4.