JPH07249736A - Semiconductor assembly - Google Patents

Abstract

PURPOSE: To provide a semiconductor assembly for a three-dimensional integrated circuit package, the whole capacity of which can be suppressed as far as possible, while controlling manufacturing cost. CONSTITUTION: When a plurality of the semiconductor assemblies with a plurality of edge recess sections 114, which are formed on one sides of at least the semiconductor assemblies 110 and from which a plurality of leads 111 are exposed, constitute a three-dimensional integrated circuit package, the edge recess section of a certain semiconductor assembly accepts a plurality of the leads 111 of the semiconductor assemblies placed at the upper sections of the edge recess section of the semiconductor assembly for electrical connection. The semiconductor assemblies 110 have upper and lower recess sections 112, 113 in top faces and undersides, and spaces for accepting the heat sinks 121 or capacitor plates are formed of one upper recess section 112 of the semiconductor assemblies and the lower recess section 113 of the semiconductor assemblies placed at the upper sections of the semiconductor assemblies.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor assembly that can be stacked, and more particularly to a semiconductor assembly that can be applied to a stacked module structure and can be mounted with a heat sink or a capacitor plate.

[0002]

2. Description of the Related Art 3) which is continuously developed up to now
The D-package (Three-Dimensional Package) is being developed in the trend of increasing the capacity, speed and size of electronic devices, and is one of the package types expected to be used effectively and properly in the future. Is one.

The 3-D package can be roughly classified into four types, that is, a semiconductor chip laminated type, a semiconductor package laminated type, a multi-chip module laminated type, and a wafer state KGD die laminated type.

Most of the companies that manufacture 3-D packages classified as above provide the semiconductor chip stacked type or the semiconductor package stacked type. Among them, the semiconductor chip laminated type can realize miniaturization, large capacity and high speed, but there are problems such as low yield, high cost, and long development period.

Further, the semiconductor package laminated type has an excellent effect as compared with the semiconductor chip laminated type, but it is generally used.
-It has the following disadvantages compared to the D package.

First of all, as a problem due to the vertical connection, many other steps must be added after the existing semiconductor packaging step in order to perform stacking.

Secondly, there is a problem due to heat release during device operation. To facilitate heat release, a heat sink may be attached to one package through another process.
A scheme must be adopted that can be equipped with another cooling device for heat release. For this reason, there is a problem in that the package volume increases and high-density mounting is impossible, and the heat dissipation means must be mounted to bear an additional cost.

FIGS. 17 to 19 show details of an embodiment of the above-mentioned prior art. FIG. 17 shows an example of a conventional stacked semiconductor package.
FIG. 3 is a cross-sectional view of “3-D memory device using proprietary process” manufactured by Staktek.

Referring to FIG. 17, in the stacked semiconductor package, first, the package bodies 11 are stacked in a four-layer structure, and then the leads 12 protruding to the outside of the package body 11 are electrically connected by a connector 13. Connecting. In the next operation of the device, metal foils may be laminated on the upper and lower surfaces of the package 11 to facilitate heat dissipation, or the package 11 may be completely laminated as shown in FIG. Ground heat sink 1
4 is formed.

However, in such a stacked semiconductor package, it is necessary to stack metal foils on the upper and lower surfaces of the package body 11 with thin plates or to expand the die pad region so as to project to the upper surface for heat dissipation. ,
It has a disadvantage that it is very complicated as compared with the conventional semiconductor packaging process.

Also, a new structure has to be manufactured, for example, it is necessary to connect a core that plays a role of a carrier for vertically connecting the semiconductor package body 11, and the existing package manufacturing equipment is applied as it is. I can't
There is also a problem with mass productivity.

18 (a) and 18 (b) are sectional views showing another embodiment of a conventional stacked semiconductor package, which is the technical content disclosed in US Pat. No. 5,105,261. In this laminated semiconductor package, a bidirectional lead 22 is first projected from a package body 21 to the outside.
To form a seagull wing (Gull-Wing).

Next, as shown in FIG. 18A, the semiconductor package prepared as described above is provided with a pinhole 26.
It is mounted by inserting it on both sides of the two PCBs 23 each having.
At this time, as shown in FIG.
A seagull wing-shaped bidirectional outer lead 22 projected to the outside of 1 is soldered onto a PCB 23 by a solder 24. After this soldering, the assembly of the stacked semiconductor package is completed by inserting the "h" -shaped connecting socket 25 into the end portion of the PCB 23.

However, in the laminated semiconductor package having such a structure, the mounting height is increased, it is difficult to improve the mounting density, and heat is not easily released. Further, there is a limit to the number of packages that can be stacked due to the limitation of the lead pitch, and there is a problem that the adhesive force is reduced in the region where the packages and the PCB are vertically contacted with each other and the structure is weak.

FIG. 19 is a perspective view showing another embodiment of the conventional laminated semiconductor package, and relates to SSIM (single in-line memory module) manufactured by RTB'S. As shown in FIG. 19, for the laminated semiconductor package, first, a semiconductor package in which pin holes are formed in a large number of leads 32 horizontally projected from the package body 31 to the outside is prepared.

Next, the semiconductor packages prepared in this manner are sequentially laminated, and after covering the upper plate 33 and the lower plate 34, the pins 35 are inserted into the pin holes of the leads 32 from the bottom to the top.
And the leads 32 are fixed to each other to complete the stacking of the packages. At this time, a pinhole is formed in the lower plate 34 so as to penetrate vertically through it on the same line as the pinhole of the lead 32.
The groove is formed so that the pin 35 can occupy only a predetermined depth. Therefore, the end 36 of the pin 35 protruding to the lower part of the lower plate 34 is mounted on a PCB (not shown).

As described above, in the stacked semiconductor packages, the rod-shaped pin 35 is inserted and used as a vertical connector of the external lead 32, but the external lead 32 is inserted into the external lead 32 as the pitch becomes finer. Since the pin 35 is thin, it is difficult to mount the pin type on the PCB.

Therefore, the external lead 36 and the other external lead 36 are connected to the PC.
In order to mount it on B, there is a disadvantage that a socket must be used, and since the pin 35 is inserted into the external lead 32, the width of the external lead 32 becomes narrow and the stacking is limited. is there.

[0019]

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a semiconductor assembly for a three-dimensional integrated circuit package which can suppress the manufacturing cost and the total capacity as much as possible. is there.

Another object of the present invention is to provide a semiconductor assembly adapted for high density three-dimensional integrated circuit packages.

Another object of the present invention is to provide a semiconductor assembly capable of realizing a high-density three-dimensional integrated circuit package without using another additional process.

Another object of the present invention is to provide a semiconductor assembly that is compatible with a reliable three-dimensional integrated circuit package.

Another object of the present invention is to provide a semiconductor assembly capable of implementing a reliable three-dimensional integrated circuit package in various forms.

Another object of the present invention is to provide a reliable three-dimensional integrated circuit package using a high yield semiconductor assembly.

Another object of the present invention is to provide a high density three-dimensional integrated circuit package which can reduce manufacturing cost.

Another object of the present invention is to provide a method of manufacturing a reliable three-dimensional integrated circuit package which can reduce the manufacturing cost.

[0027]

In order to achieve the above object, according to the present invention, in a semiconductor assembly having a plurality of leads, a plurality of leads are formed on at least one side of the semiconductor assembly and the plurality of leads are exposed. It is characterized by having individual pockets. The pockets may each receive a plurality of leads of the semiconductor assembly located above for electrical connection when a plurality of the semiconductor assemblies form an integrated circuit package.

In addition, another semiconductor assembly having a plurality of leads is provided with at least one edge recess portion extending along a side of the semiconductor assembly and exposing the plurality of leads. . The edge recess portion may receive a plurality of leads of the upper semiconductor assembly for electrical connection when the plurality of semiconductor assemblies form a three-dimensional integrated circuit package.

Further, in another semiconductor assembly having a plurality of leads, an edge recess portion extending along at least one side of the semiconductor assembly and exposing upper surfaces of the plurality of leads, and the semiconductor assembly. An upper recess portion provided on the upper surface of the semiconductor assembly and a lower recess portion provided on the lower surface of the semiconductor assembly. Here, when a plurality of the semiconductor assemblies constitute a three-dimensional integrated circuit package, an edge recess portion of a semiconductor assembly may connect a plurality of leads of the semiconductor assembly located above the semiconductor assembly for electrical connection. Acceptable. In addition, when a plurality of the semiconductor assemblies form a three-dimensional integrated circuit package, a heat sink or a capacitor may be formed by one upper recess portion of the semiconductor assembly and a lower recess portion of the semiconductor assembly located above the semiconductor assembly. A space can be formed to receive the plate. The capacitor plate includes connection leads, two conductive foil foil sheets each connected to a power supply voltage and a ground voltage through the connection leads, and an insulating plate interposed between the two foil sheets. The semiconductor assembly preferably includes a trace for receiving the connection lead of the capacitor plate and communicating with the upper and lower recess portions, respectively.

Further, in the three-dimensional integrated circuit package according to the present invention, a plurality of integrated circuit built-in assemblies each having an edge recess portion extending along at least one side and exposing a plurality of leads are provided. A capacitor-embedded assembly having an edge recess portion extending along one side for receiving a plurality of leads and containing at least one capacitor. Here, the capacitor built-in assembly is
A first die pad having a ground voltage level, a second die pad electrically connected to a power supply voltage via at least one bonding wire and a lead, and the first and second die pads.
A plurality of capacitor elements connected in parallel between the die pads.

[0031]

The pockets or the edge recesses are configured to expose the leads, and each of the pockets or the edge recesses receives the leads belonging to an assembly located above when the assembly forms a three-dimensional integrated circuit package, and electrically. Since the internal connection can be performed, it is possible to stack with good reliability while suppressing the entire capacity as much as possible without performing an additional step.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of a laminated semiconductor package according to the present invention will now be described in detail with reference to the accompanying drawings. The term "module" means "three-dimensional structure integrated circuit package".

FIG. 1 is a perspective view showing a first embodiment of a semiconductor assembly according to the present invention and relates to a dual type package.

As shown in FIG. 1, a plurality of leads 43 of the assembly body 41 of the semiconductor assembly are bent into a J shape as an SOJ type, and the upper surface thereof is exposed to form a lead region 42. That is, in the assembly 41, the lead region 4 at one end of the lead 43
A surface is formed vertically upward from three directions 2 and 2, and thus a rectangular parallelepiped pocket 44 is formed. The lead region 42 and the pocket 44 are formed side by side in the horizontal direction along the same direction on the two sides of the assembly 41 that face each other.

Although FIG. 1 shows a dual type package, the J-shaped lead 43 can be changed to another shape such as a quad type when applied to a QFP structure. . When applied to a quad type package, the pocket 44
Can also be arranged on four sides of the assembly 41. As a result, the pockets 44 exposing the lead regions 42 have the same shape as the assembly 4 (package).
1 serves as a groove for stacking 1 in a 3-D configuration.

FIG. 2 shows a state in which the four assemblies shown in FIG. 1 are stacked on the PCB 57 to form a module.

In the assembly 41, the leads 43 are connected to the corresponding pads of the integrated circuit chip 52 via the bonding wires 54. The integrated circuit chip 52 is installed on the die pad 51. Certain assembly 4
The J-shaped lead 43 of No. 1 is received in the pocket 44 of the assembly body 41 located below the assembly body 41, and then adhesively fixed by a known brazing reflow process. During this bonding, matching jigs are used for the pockets 44 to ensure a reliable electrical connection between each one of the upper and lower assembly bodies 41 and provide structural stability for support. The vertical height of the bent portion of the lead 43 can be adjusted by a bending tool or the like in relation to the structural state of the stacked assembly 41. For example, when stacking SOJ type package structures, when the height of the assembly 41 excluding the standoff is 3 mm, the surplus length of the J-shaped lead 43 of the pocket 44 is 0.7 mm. When the semiconductor assemblies (packages) are vertically stacked, the distance between the lower surface of the J-shaped lead 43 and the upper surface of the lead region 42 is 1 m.
Although it is possible to obtain about m, the length of the J-shaped lead 43 may be lengthened by about 1 mm and the position to be molded may be appropriately adjusted downward.

In addition, TSOJ (Thin and Small Out-line
In the case of a J-bent package, the standoff of the J-shaped lead to be molded is thicker than the thickness of the assembly (package), so reduce the length of the lead and adjust the molding position upward. Good.

FIG. 3 is a perspective view showing a second embodiment of the semiconductor assembly according to the present invention. The assembly 61 shown in FIG. 3 is useful for a TSOJ package so that the lead adjacent to the upper surface of the lead region 62 above the lead 63 of the assembly (package) 61 is completely exposed. Edge recesses 64 are formed on both sides of the lead region 62.

Although the structure shown in FIG. 3 is a dual in-line package type, when applied to a quad type package, the edge recess portion 64 may be located on four sides (four sides) of the assembly body 61. it can. Such a structure is advantageous for assemblies having a smaller lead-to-lead pitch than the assembly 41 shown in FIG.

FIG. 4 shows a state in which the four assemblies shown in FIG. 3 are stacked on a PCB (not shown) to form a module. The J-shaped portion of the lead 63 of a certain assembly 61 has a corresponding edge recess portion 64 of the assembly 61 located below the assembly 61.
A lead 6 received in the lower portion of the J-shaped portion and placed in the edge recess portion 64 by a known brazing reflow process.
The electrical connection between the upper and lower assembly bodies 61 is completed by being adhered to the exposed surface of the third electrode 3, that is, the lead region 62.

FIG. 5 is a sectional view showing a semiconductor assembly 94 in the form for lamination according to the third embodiment of the present invention. As shown in FIG. 5, in this embodiment,
As applied when the size of the integrated circuit chip 92 mounted on the die pad 91 is large, the leads 95 are connected to the integrated circuit chip 92 by the down bonding method. That is, in the semiconductor assembly 94, the integrated circuit chip 92 is bonded to the lower surface of the die pad 91, the bonding pad of the semiconductor chip 92 and the internal lead 93 are down-bonded, and the electrical connection is completed. To form an assembly body (package body) 96. The upper surface of the lead 95 is completely exposed to form an edge recess 97.

FIG. 6 shows the semiconductor assembly 9 shown in FIG.
5 is a cross-sectional view of a module (semiconductor device) in which No. 4 is applied and is laminated in a three-layer structure.
7 shows a state in which the components are vertically mounted and laminated on No. 7.

FIG. 7 shows a structure in which heat sinks are mounted on the upper and lower surfaces of the assembly 110 of the semiconductor assembly. As shown in FIG. 7, the assembly body 110 in this embodiment basically applies the basic structure of the semiconductor assembly shown in FIG. 1 or FIG.
0 upper and lower recesses 11 on the upper and lower surfaces, respectively.
2 and 113 are provided, and an edge recess portion 114 is provided at a portion corresponding to the edge recess portions 64 and 97 of the second and third embodiments. The lead 111 in the edge recess 114 is buried in the molding compound to a depth equivalent to the thickness of the lead 111, as shown by the broken line, and the upper surface of each is exposed.

The upper and lower recesses 112 and 113 are shown in FIG.
8 has the same width in the lateral direction as shown in FIG.
The heat sink 121 or 122 shown in FIG.
Or, as shown in FIG. 10, the upper and lower recesses 11
It is received in the space 124 formed by 2,113. The shapes of the heat sinks 121 and 122 are the geometrical structure of the space 124 formed at the time of stacking and the heat sink 12
It is deformed by the efficiency of the heat release function of 1,122 itself. The thickness of the heat sinks 121 and 122 depends on the thickness of the assembly. When the thickness of the SOJ type assembly is large, the heat sinks 121, 1
Since the thickness of 22 becomes thicker and the thickness of the mold forming the assembly body at the time of stacking may be thinner even in the case of the TSOJ type package, the thickness of the heat sink can be further thickened. For example, when stacking a TSOJ type assembly, recesses are provided on the upper and lower surfaces of the assembly at a depth of 0.1 mm, that is, the depth of the upper and lower recesses 112 and 113 is set to 0.1 mm. If so, the thickness of the heat sink is about 0.2 mm.

The process of attaching the heat sink to the upper and lower recesses 112 and 113 is performed at the same time as the assembly is laminated, and contains silver Ag epoxy which is an epoxy resin having excellent thermal conductivity and a metal filler. It can be easily attached using epoxy.

FIG. 11 shows an electrical connection state when nine 16 Mb DRAM integrated circuits 150 to 158 are stacked by utilizing one of the embodiments according to the present invention described above.

Referring to FIG. 11, each DRAM 150-
In 158, all pins except the data pins DQ0 to DQ35, that is, signal application pins (for example, output enable signal pin OE, address pins A0 to A11,
Write control signal pin W, column address strobe signal pin CAS, and column address strobe signal pin RA
S) is commonly used. The data pins are proportional to the number of semiconductor assemblies stacked in the module.

12 and 13 show an embodiment of a semiconductor assembly having a capacitor for ensuring the electrical stability of input / output data.

The capacitor 161 is the die pad 160, 1
70 are bonded in parallel. The die pad 160 is used as a ground voltage plate, and the die pad 170 is connected to the power supply voltage terminal Vcc through two internal leads 162. That is, a bonding wire 163 is provided between the die pad 170 having a Vcc potential and the internal lead 162 to electrically connect the die pad 170 and the internal lead 162.
The cc terminal is connected. If the capacitance of one capacitor is 0.1 μF, the total capacitance of the four capacitors shown in FIG. 12 or 13 is 0.4 μF, which is equivalent to the module of nine assemblies shown in FIG. Applicable.

As shown in FIG. 14, the assembly body 167 including the capacitors shown in FIG. 13 is placed at the bottom of the module, and the assembly body 61 including the integrated circuit is stacked above the assembly body 167. The assembling and bonding method is performed as described above.

The external structure of the assembly containing the capacitors shown in FIG. 12 or 13 is the same as the external structure of the assembly 61 shown in FIGS. 3 and 4, but with the integrated circuits stacked together. It may be formed differently according to the shape of the assembly.

In the present invention, instead of the assembly 167 including the capacitor 161 shown in FIGS. 12 and 13, a capacitor plate 195 as shown in FIGS. 15A and 15B may be adopted. it can.

Referring to FIGS. 15A and 15B, two metal foil sheets 191 and 192 are adhered to the upper surface and the lower surface of the insulating plate 190, respectively.
Metal foil sheet 191 on top of insulating plate 190
Is connected to the power supply voltage Vcc through the lead 193, and the metal foil sheet 192 on the lower surface of the insulating plate 190 is connected to the ground voltage GND through the lead 194. The capacitor plate 195 shown in FIGS. 15 (a) and 15 (b) does not increase the overall height of the module and is suitable for mounting on or between assemblies containing integrated circuits. .

FIG. 16 shows the structure of an assembly 200 including an integrated circuit on which the capacitor plate 195 shown in FIGS. 15A and 15B can be mounted. As shown in FIG. 16, a metal foil trace 203 for receiving the leads 193 and 194 of the capacitor plate 195 on the upper and lower surfaces of the assembly 200.
7 is the same as the structure of the assembly 110 shown in FIG. The height of the foil trace 203 is the same as the height of the upper and lower recess portions 204 and 205. When the assembly bodies 200 on which the capacitor plates 195 are mounted are stacked, the capacitor plates 1
Since 95 is located in the space formed by the lower recess portion 205 of a certain assembly body 200 and the upper recess portion 204 of the assembly body 200 located below the assembly body 200, the volume increase of the entire module due to the capacitor plate 195 does not occur. Absent.

The embodiments described above are merely some examples of the present invention, and those skilled in the art will not be limited to the embodiments without departing from the technical idea of the present invention, and various transformations and modifications can be made. It goes without saying that it is possible.

[0057]

Therefore, in order to manufacture a stacked module by the semiconductor assembly (package) for stacking according to the present invention, the existing package manufacturing process can be directly adopted without any special additional process, and the stacking is easy.
In addition, the laminated structure is stable, which has the effect of cost savings.

The present invention also provides a SOJ or TSOJ
The present invention can be applied to a semiconductor package of a type and all other types of packages that can be stacked, and in particular, by attaching a heat sink, it can be applied to a variety of semiconductor devices having excellent heat dissipation capability.

Further, according to the present invention, it is possible to easily perform the test and the inspection on the outside, and it is not necessary to provide another socket or a supplementary device for mounting the stacked semiconductor assemblies (packages).

In stacking the semiconductor assembly (package) of the present invention, at least one or more capacitors are mounted on a plurality of die pads, and then the assembly (package) molded with epoxy resin is used.
By stacking with another package stacked on D, the electrical characteristics which are a problem in this kind of stacking can be improved, and the characteristics of various elements can be compensated.

Further, according to the present invention, with respect to the recess portions formed on the upper surface and the lower surface of the assembly body (package body), the metal foil formed in a plane shape is formed on the upper and lower surfaces to form a plane shape. Various types of semiconductor packages can be realized by arranging the capacitors.

Further, in the present invention, by applying the existing package manufacturing process as it is, it is possible to realize high-density mounting without lowering the yield of the device, the structure is simple, and the defect rate can be reduced. There are advantages.

As described above, when manufacturing a stacked semiconductor device according to the present invention, it is possible to vertically stack semiconductor packages of various forms by applying existing processes as they are without adding special equipment. The electrical characteristics of the semiconductor device, which are regarded as problems in stacking, can be compensated in various forms.

[Brief description of drawings]

FIG. 1 is a perspective view showing a semiconductor assembly according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a state in which a module in which the semiconductor assembly shown in FIG. 1 is applied and which has a four-layer structure is mounted on a PCB.

FIG. 3 is a perspective view showing a semiconductor assembly according to a second exemplary embodiment of the present invention.

FIG. 4 is a cross-sectional view of a module in which the semiconductor assembly shown in FIG. 3 is applied and stacked in a four-layer structure.

FIG. 5 is a sectional view showing a semiconductor assembly according to a third embodiment of the present invention.

FIG. 6 is a cross-sectional view of a module in which the semiconductor assembly shown in FIG. 5 is applied to be stacked in a three-layer structure.

FIG. 7 is a side view showing an outer shape of a semiconductor assembly on which a heat sink according to the present invention is mounted.

8A and 8B are perspective views showing a heat sink that can be mounted on the semiconductor assembly shown in FIG. 7.

FIG. 9 is a cross-sectional view of a module in which the semiconductor assembly having the heat sink shown in FIG. 8A is applied and stacked in a three-layer structure.

FIG. 10 is a cross-sectional view of a module in which the semiconductor assembly having the heat sink shown in FIG. 8B is applied and stacked in a three-layer structure.

FIG. 11 is a functional block diagram showing an electrical connection state of the laminated module according to the present invention.

FIG. 12 is a plan view showing a semiconductor assembly having a capacitor mounted on a die pad according to the present invention.

13 is a vertical cross-sectional view showing the semiconductor assembly shown in FIG. 12 in detail.

14 is a cross-sectional view showing a module in which the semiconductor assembly shown in FIG. 13 and the semiconductor assembly shown in FIG. 3 are stacked in a four-layer structure.

15A and 15B are a cross-sectional view and a plan view showing a capacitor that can be disposed on the upper and lower surfaces of the semiconductor assembly shown in FIG.

16 is a side view showing the outer shape of a semiconductor assembly in which the capacitor shown in FIG. 15 can be arranged.

FIG. 17 is a cross-sectional view showing a conventional stacked semiconductor module.

18 (a) and 18 (b) are an overall sectional view and a partial detailed sectional view of a conventional laminated module different from that shown in FIG.

FIG. 19 is a perspective view showing another conventional laminated module different from those shown in FIGS. 17 and 18;

[Explanation of symbols]

41, 61, 96, 110, 167, 200 Assembly body 43, 63, 95, 111, 193, 194 Lead 44 pocket 64, 97, 114 Edge recess portion 92 Integrated circuit chip 94 Semiconductor assembly 112, 204 Upper recess portion 113, 205 Lower recess 121,122 Heat sink 124 Space 160,170 Die pad 161 Capacitor 191,192 Metal foil sheet 195 Capacitor plate 203 Foil trace

Claims (11)

[Claims] 1. A semiconductor assembly having a plurality of leads, comprising: a plurality of pockets formed on at least one side of the semiconductor assembly to expose the plurality of leads. 2. The plurality of pockets each receive a plurality of leads of an upper semiconductor assembly for electrical connection when the plurality of semiconductor assemblies form an integrated circuit package. The semiconductor assembly of claim 1, wherein the semiconductor assembly is characterized by: 3. A semiconductor assembly having a plurality of leads, the semiconductor assembly comprising at least one edge recess extending along a side of the semiconductor assembly and exposing the plurality of leads. . 4. The edge recess portion receives a plurality of leads of an upper semiconductor assembly for electrical connection when a plurality of the semiconductor assemblies form a three-dimensional integrated circuit package. The semiconductor assembly according to claim 3, wherein: 5. A semiconductor assembly having a plurality of leads, an edge recess portion extending along at least one side of the semiconductor assembly, wherein an upper surface of the plurality of leads is exposed, and an edge recess portion of the semiconductor assembly. A semiconductor assembly comprising: an upper recess portion provided on an upper surface and a lower recess portion provided on a lower surface of the semiconductor assembly. 6. When a plurality of semiconductor assemblies form a three-dimensional integrated circuit package, an edge recess portion of a semiconductor assembly electrically connects a plurality of leads of the semiconductor assembly located above the semiconductor assembly. 6. The semiconductor assembly according to claim 5, wherein the semiconductor assembly is for receiving. 7. When a plurality of the semiconductor assemblies form a three-dimensional integrated circuit package, one upper recess portion of the semiconductor assembly and a lower recess portion of the semiconductor assembly located above the semiconductor assembly are formed. The semiconductor assembly of claim 5, wherein a space is formed to receive the heat sink. 8. When a plurality of the semiconductor assemblies constitute a three-dimensional integrated circuit package, one upper recess portion of the semiconductor assembly and a lower recess portion of the semiconductor assembly located above the semiconductor assembly include: The semiconductor assembly of claim 5, wherein a space is formed for receiving the capacitor plate. 9. The capacitor plate includes a connection lead, two conductive foil foil sheets respectively connected to a power supply voltage and a ground voltage through the connection lead, and an insulation interposed between the two foil sheets. Plate and
9. The semiconductor assembly according to claim 8, further comprising a trace that receives the connection lead of the capacitor plate and that communicates with the upper and lower recess portions, respectively. 10. A three-dimensional integrated circuit package, comprising: a plurality of integrated circuit built-in assemblies having edge recesses extending along at least one side and exposing a plurality of leads; and at least one side thereof. A three-dimensional integrated circuit package, comprising: a capacitor-embedded assembly having an edge recess portion extending along the edge recess for receiving a plurality of leads and containing at least one capacitor. 11. The capacitor built-in assembly includes a first die pad having a ground voltage level, a second die pad electrically connected to a power supply voltage through at least one bonding wire and a lead, and a first die pad and a first die pad. The three-dimensional integrated circuit package according to claim 10, further comprising a plurality of capacitor elements connected in parallel between two die pads.