JP3167720B2 - ＢｉＣＭＯＳデジタルドライバ回路 - Google Patents

ＢｉＣＭＯＳデジタルドライバ回路

Info

Publication number
JP3167720B2
JP3167720B2 JP50997991A JP50997991A JP3167720B2 JP 3167720 B2 JP3167720 B2 JP 3167720B2 JP 50997991 A JP50997991 A JP 50997991A JP 50997991 A JP50997991 A JP 50997991A JP 3167720 B2 JP3167720 B2 JP 3167720B2
Authority
JP
Japan
Prior art keywords
transistor
bipolar transistor
input signal
terminal
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP50997991A
Other languages
English (en)
Japanese (ja)
Other versions
JPH05508753A (ja
Inventor
エルガマル、アバス
Original Assignee
シノシス・インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シノシス・インコーポレイテッド filed Critical シノシス・インコーポレイテッド
Publication of JPH05508753A publication Critical patent/JPH05508753A/ja
Application granted granted Critical
Publication of JP3167720B2 publication Critical patent/JP3167720B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
JP50997991A 1990-05-15 1991-05-08 ＢｉＣＭＯＳデジタルドライバ回路 Expired - Lifetime JP3167720B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US524,207 1990-05-15
US07/524,207 US5068548A (en) 1990-05-15 1990-05-15 Bicmos logic circuit for basic applications

Publications (2)

Publication Number Publication Date
JPH05508753A JPH05508753A (ja) 1993-12-02
JP3167720B2 true JP3167720B2 (ja) 2001-05-21

Family

ID=24088237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50997991A Expired - Lifetime JP3167720B2 (ja) 1990-05-15 1991-05-08 ＢｉＣＭＯＳデジタルドライバ回路

Country Status (4)

Country Link
US (1) US5068548A (enExample)
JP (1) JP3167720B2 (enExample)
AU (1) AU7987891A (enExample)
WO (1) WO1991018448A1 (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173623A (en) * 1989-05-15 1992-12-22 Texas Instruments Incorporated High performance BiCMOS logic circuits with full output voltage swing up to four predetermined voltage values
US5055716A (en) * 1990-05-15 1991-10-08 Siarc Basic cell for bicmos gate array
US5289021A (en) * 1990-05-15 1994-02-22 Siarc Basic cell architecture for mask programmable gate array with 3 or more size transistors
JP3095229B2 (ja) * 1990-08-31 2000-10-03 株式会社日立製作所 マイクロプロセッサ及び複合論理回路
JP2734254B2 (ja) * 1991-10-15 1998-03-30 日本電気株式会社 レベル変換回路
US5300829A (en) * 1992-09-09 1994-04-05 Intel Corporation BiCMOS circuit with negative VBE protection
US5430408A (en) * 1993-03-08 1995-07-04 Texas Instruments Incorporated Transmission gate circuit
JP3019668B2 (ja) * 1993-05-21 2000-03-13 日本電気株式会社 半導体論理回路
US5398000A (en) * 1994-03-30 1995-03-14 Intel Corporation Simple and high speed BICMOS tristate buffer circuit
US5591995A (en) * 1994-05-10 1997-01-07 Texas Instruments, Incorporated Base cell for BiCMOS and CMOS gate arrays
US5563543A (en) * 1994-12-14 1996-10-08 Philips Electronics North America Corporation Low-voltage BiCMOS digital delay chain suitable for operation over a wide power supply range
US5554942A (en) * 1995-03-13 1996-09-10 Motorola Inc. Integrated circuit memory having a power supply independent input buffer
JP2720816B2 (ja) * 1995-03-31 1998-03-04 日本電気株式会社 ＢｉＭＯＳ集積回路
US5682108A (en) * 1995-05-17 1997-10-28 Integrated Device Technology, Inc. High speed level translator
US5990502A (en) * 1995-12-29 1999-11-23 Lsi Logic Corporation High density gate array cell architecture with metallization routing tracks having a variable pitch
JP3152635B2 (ja) * 1996-09-09 2001-04-03 三洋電機株式会社 マスタスライス方式の基本セル、半導体集積回路装置、フリップフロップ回路、排他的論理和回路、マルチプレクサ及び加算器
US5977574A (en) * 1997-03-28 1999-11-02 Lsi Logic Corporation High density gate array cell architecture with sharing of well taps between cells
US6480032B1 (en) 1999-03-04 2002-11-12 Intel Corporation Gate array architecture
US6974978B1 (en) 1999-03-04 2005-12-13 Intel Corporation Gate array architecture
US6294959B1 (en) 1999-11-12 2001-09-25 Macmillan Bruce E. Circuit that operates in a manner substantially complementary to an amplifying device included therein and apparatus incorporating same
US8196086B2 (en) * 2010-07-21 2012-06-05 Lsi Corporation Granular channel width for power optimization
US10672439B2 (en) * 2018-07-10 2020-06-02 Globalfoundries Inc. Data dependent keeper on global data lines

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6242614A (ja) * 1985-08-20 1987-02-24 Fujitsu Ltd 複合トランジスタ形インバ−タ
US4649294A (en) * 1986-01-13 1987-03-10 Motorola, Inc. BIMOS logic gate
US4701642A (en) * 1986-04-28 1987-10-20 International Business Machines Corporation BICMOS binary logic circuits
JPH07120727B2 (ja) * 1987-03-27 1995-12-20 株式会社東芝 ＢｉＭＯＳ論理回路

Also Published As

Publication number Publication date
US5068548A (en) 1991-11-26
JPH05508753A (ja) 1993-12-02
WO1991018448A1 (en) 1991-11-28
US5068548B1 (enExample) 1993-03-30
AU7987891A (en) 1991-12-10

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