Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
  • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
  • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
  • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
  • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]

Definitions

• This invention relates to integrated circuits and in particular to BiCMOS driver circuits for use in macrocells for Application Specific Integrated Circuits.
• CMOS transistors are frequently used to keep power consumption of the integrated circuit to a minimum. These CMOS transistors may be used as building blocks to create a wide variety of logic circuits. Since many CMOS transistors are formed on a single die, it is desirable to make the CMOS transistors very small, resulting in these CMOS transistors having only low current handling capability. To increase the low current output signal of CMOS transistors in order to overcome the parasitic capacitance, inductance, and resistance of conductors and components connecting the output of the CMOS transistors to a subsequent stage, drivers are typically incorporated throughout the integrated circuit to receive the low current output of the CMOS transistors and output a much higher current to drive one or more subsequent stages.
• CMOS transistors are in programmable gate arrays, including sea of gates, where the various input and output terminals of a plurality of low current CMOS transistors grouped within cells are programmably interconnected, using mask, electrical, or laser programming techniques, to form any number of logic circuits (macrocells) .
• CMOS transistors due to the low current output of the individual CMOS transistors, in order to drive a relatively high capacitance load, such as in the case of a fan out, a plurality of CMOS transistors must be connected in parallel to increase the current output and, thus, ensure high speed and reliable operation of the integrated circuit.
• BiCMOS circuits A faster and more area efficient means for driving high capacitance loads is to drive the loads with bipolar transistors.
• Such circuits which have become increasingly popular, are generally known as BiCMOS circuits.
• bipolar devices are used as the BiCMOS driver in a totem- pole configuration, as shown in the macrocell of Fig. 1. Representative channel widths and channel lengths of the MOSFETs are shown. Pull-up and pull-down bipolar transistors are used frequently as driver transistors instead of large MOSFETs due to their fast switching speeds and low parasitic capacitance.
• the representative prior art circuit of Fig. 1 shows a CMOS device comprising low current handling transistors Ql and Q2 having gates coupled to input terminal 8.
• N-channel low current handling transistors Q3 and Q4 are coupled in series, with the gate of transistor Q3 coupled to input terminal 8 and the gate of transistor Q4 coupled to the output of the CMOS device.
• the base of high current NPN bipolar transistor Q5 is coupled to the output of the CMOS device.
• the common node of transistors Q3 and Q4 is coupled to the base of high current NPN bipolar transistor Q6, acting as a pull-down device.
• N-channel transistors Q3 and Q4 are used to prevent a full high level input voltage (e.g., 5 volts) from being directly applied to the base of bipolar pull-down transistor Q6.
• Bipolar transistors Q5 and Q6 are connected in series between supply voltage terminal 10 and ground terminal 12. The output of the driver circuit comprising bipolar transistors Q5 and Q6 is at the common node of transistors Q5 and Q6.
• the driver circuits may be located in each cell or remote from the CMOS transistors.
• the driver circuits may or may not be - used for a specific configuration of the CMOS gates, depending on whether the CMOS gates themselves provide a sufficiently high output current to adequately drive a subsequent stage.
• many of these driver circuits may not even be required for a specific application, leaving a large portion of the die area unused.
• driver circuits in integrated circuits which require a minimum of die area but still possess fast switching speeds and high current capability.
• a novel, high switching speed, driver circuit for use with a CMOS or other low power device is disclosed herein, wherein the driver circuit comprises a single pull-up bipolar transistor and a single N-channel pull ⁇ down MOSFET.
• a low power CMOS device inverts an input signal and provides this inverted input signal into the base of an NPN bipolar transistor whose collector is coupled to a positive power supply voltage.
• the input signal coupled to the input of the CMOS device is also coupled to the gate of a large N-channel MOSFET having its drain coupled to the emitter of the bipolar transistor and its source coupled to ground.
• the common node of the bipolar transistor and the N-channel MOSFET provides the output signal of the driver.
• an input signal into the CMOS device is directly coupled to the gate of the N-channel pull-down MOSFET, while an inverted input signal is coupled to the base of the bipolar transistor, so that the bipolar transistor and the N-channel MOSFET always assume opposite states to provide a high or low output signal with very low leakage current passing from the power supply terminal to ground through the bipolar transistor and the N-channel MOSFET.
• This driver is inherently smaller than prior art BiCMOS drivers since the driver requires fewer transistors to operate, and its performance is comparable to standard BiCMOS drivers. Additional advantages of this novel driver circuit are discussed below.
• Fig. 1 shows a prior art BiCMOS circuit using bipolar pull-down and pull-up transistors.
• Fig. 2a shows one embodiment of a circuit using the inventive BiNMOS driver circuit.
• Fig. 2b shows an equivalent circuit of Fig. 2a.
• Fig. 2c is a graph showing delay vs. capacitance for different types of driver circuits.
• Fig. 3 shows an alternative embodiment of a circuit using the BiNMOS driver circuit.
• Fig. 4 shows an alternative embodiment of a circuit using the BiNMOS driver circuit.
• Figs. 5a-5c show embodiments of the inventive BiNMOS driver circuit incorporated into a NAND gate.
• Fig. 6 illustrates one type of logic circuit which uses the BiNMOS driver, which may be included in a macrocell library.
• Fig. 7 illustrates a three state logic circuit which uses the BiNMOS driver.
• Fig. 2a The preferred embodiment of the invention is shown in Fig. 2a and also described in the paper entitled "BiNMOS: A Basic Cell For BiCMOS-Sea-Of-Gates," by A. El Gamal et al., dated May 15, 1989. This article is incorporated herein by reference.
• the circuit of Fig. 2a comprises a logic portion, comprising CMOS transistors Ql and Q2, and a drive portion, comprising bipolar transistor Q3 and N-channel transistor Q4.
• an input signal is applied to the gates of P-channel transistor Ql and N-channel transistor Q2, connected as a CMOS device between power supply terminal 20 and ground terminal 22.
• the common node of transistors Ql and Q2 at terminal 24 provides an input signal into the base of NPN bipolar pull-up transistor Q3.
• the input signal applied to the gates of transistors Ql and Q2 is also directly applied to the gate of N-channel transistor Q4 so that the signal applied to the base of transistor Q3 is inverted from the signal applied to the gate of transistor Q4.
• a high logic level input signal coupled to the gates of transistors Ql and Q2 turns N-channel transistor Q2 on and P-channel transistor Ql off. This causes a low voltage to be applied to the base of transistor Q3, turning transistor Q3 off.
• the high logic level input signal applied to the gate of N-channel transistor Q4 turns transistor Q4 on. Thus, the output at terminal 28 will be shorted to ground.
• N-channel transistor Q4 will approach that of a bipolar transistor if the parasitic capacitance seen at terminal 28 is sufficiently low.
• transistor Q4 exhibits a pull-down delay time approximately equal to that of a bipolar pull-down transistor in a BiCMOS driver for an output capacitance of less than approximately 0.4pF (see Fig. 2c) .
• a parallel N-channel transistor Q5 may be connected in a manner identical to the connection of transistor Q4.
• the pull-down delay of the driver is approximately that of a bipolar pull-down transistor in a BiCMOS driver for an output capacitance of less than approximately 2.0 pF.
• Transistor Q5 is shown in dashed outline to indicate that it is optional.
• N-channel transistor Q4 can be made larger to increase its speed in pulling down output terminal 28.
• transistor Q4 The size of transistor Q4 is dictated by its desired switching speed, given a certain anticipated capacitance at output terminal 28, whereby transistor Q4 must be designed to short to ground a sufficient percentage of the charge stored in the parasitic capacitor as seen at terminal 28 within a certain predetermined period of time.
• Fig. 2b shows an equivalent circuit of the circuit of Fig. 2a, where transistors Ql and Q2 in Fig. 2a are represented by inverter 32, while transistors Q3 and Q4 are connected as described with respect to Fig. 2a.
• An input signal is applied to terminal 34 in Fig. 2b, while an output signal is taken from terminal 36.
• Fig. 2c is a graph of switching delay vs. load capacitance for: 1) a CMOS device (channel width 12.5 ⁇ ) , channel length 0.8 ⁇ ); 2) the BiCMOS device of Fig. 1;
• programmable gate arrays incorporating the driver circuit of Fig. 2a may devote less area to driver circuits and more area to logic circuits.
• the pull-down time for the BiNMOSl inverter is shorter than or comparable to the pull-down time for the BiCMOS inverter, given a capacitive loading of less than approximately 0.4 pF
• the pull-down time for the BiNMOS2 inverter is shorter than or comparable to the pull-down time for the BiCMOS inverter, given a capacitive loading of less than approximately 2 pf.
• the pull-up time of the P-channel transistor of the CMOS device is significantly longer than the pull-up time of the BiCMOS inverter even for low capacitive loading, due to the slower mobility of holes through the P-channel transistor.
• BiNMOS driver also has the advantage of pulling an output terminal to ground with no threshold voltage drop.
• an inverter 37 may be placed between input terminal 38 and the gate of N-channel transistor Q4, while the base of transistor Q3 is coupled directly to input terminal 38.
• the output signal at terminal 40 would be a noninverted representation of the input signal applied to input terminal 38.
• Fig. 4 shows another embodiment of the invention where small P-channel MOS transistor Q6 is connected in parallel with the base and emitter of transistor Q3, where the gate of transistor Q6 is either coupled to input terminal 42 or to a ground terminal.
• Inverter 44 which may be a CMOS device, is coupled between terminal 42 and the base of transistor Q3.
• transistor Q6 when transistor Q6 is on, due to the output of inverter 44 being high, the full output voltage of inverter 44 is coupled to output terminal 46 via transistor Q6 instead of a voltage lowered by the V of transistor Q3.
• Figs. 5a, 5b, and 5c show three separate NAND gate circuits using a BiNMOS driver having inputs A and B and an output at terminal 50.
• Figs. 5a-5c are intended to illustrate the flexibility of the BiNMOS driver to accommodate a range of capacitances as seen at output terminal 50.
• the NAND circuit of Fig. 5a is advantageous for outputs having a relatively high parasitic capacitance.
• bipolar transistor Q3 and N-channel transistor Q4 together act as a non-inverting BiNMOS driver for the output of NAND gate 52, where the output of NAND gate 52 is coupled to the gate of transistor Q4 via inverter 54.
• Inverter 54 applies a relatively high power signal to the gate of transistor Q4 to cause transistor Q4 to quickly turn on.
• Small P-channel transistor 56 is coupled across the base and emitter of bipolar transistor Q3 and has its gate connected to either the output of inverter 54 or ground potential. Transistor 56 is thus turned on when a high voltage is applied to the base of transistor Q3 and serves to eliminate any V_, chorus drop at output terminal 50 when the output is a logical high.
• circuit of Fig. 5b is beneficial for driving medium capacitive outputs, where inputs A and B into NAND gate 52 are also applied directly to the gates of
• a separate inverter, such as inverter 54 in Fig. 5a, is not required, since input signals A and B are sufficient to adequately switch transistors Q4 and Q5.
• Small P-channel transistor 56 may be connected between the base and emitter of bipolar transistor Q3, with its gate connected to ground, to eliminate any V o.,.h-i, drop across transistor Q3 when the output at terminal 50 is a logical high.
• the NAND gate circuit of Fig. 5c uses the least number of transistors and is most advantageous with low capacitive loading on output terminal 50.
• Pull-up P-channel transistors Q6 and Q7 have their gates coupled to receive input signals A and B, respectively, and have their sources coupled to the base of transistor Q3.
• N-channel transistor Q8 has its gate coupled to receive input signal A, its drain coupled to the base of transistor Q3, and its source coupled to the source of N-channel transistor Q4.
• the drain of transistor Q4 is coupled to the emitter of transistor Q3, and the source of transistor Q4 is coupled to ground through N-channel transistor Q5.
• the gate of transistor Q5 is coupled to receive input signal B.
• Small P-channel transistor 56 of Fig. 5b may similarly be used in the circuit of Fig.
• the NAND circuit of Fig. 5c since it uses very few transistors, requires very little die area.
• the circuit of Fig. 5b uses more transistors but drives a larger load, and the circuit of Fig. 5a, having a driver circuit similar to that of Fig. 3, contains the most transistors but drives a still larger capacitance load.
• BiNMOS driver being smaller than a full BiCMOS driver
• other advantages include the BiNMOS being faster for small to medium loads and faster than a BiCMOS driver for reduced output voltage swings. These advantages are additionally discussed in the article, "Future BiCMOS Technology For Scaled Supply Voltage," by Watanabe et al., published December 30, 1989 in IEDM '89, which briefly discusses Applicant's BiNMOS circuit.
• the BiNMOS circuit is ideally suited to a sea of gates type programmable gate array integrated circuit, where a BiNMOS driver may be incorporated into each cell. Since a BiNMOS driver uses significantly less area than a two-bipolar transistor driver, the inclusion of a BiNMOS driver in each cell enables each cell to be made smaller than cells incorporating a two-bipolar transistor driver. If additional pull-down capability is desired, other
• N-channel MOSFETs within the cell may be connected in parallel with the N-channel pull-down driver transistor. Further, since a BiNMOS driver is to be included in each cell, the other CMOS components in the cell may be made smaller than prior art CMOS components. The BiNMOS driver would then be typically used as an output buffer for each cell, thus fully utilizing the BiNMOS drivers and minimizing the size of other components within the cell.
• ASIC Application Specific Integrated Circuits
• ASIC Application Specific Integrated Circuits
• programmable gate arrays e.g., sea-of-gates type circuits
• standard cell type circuits publish macrocell libraries identifying standard logic circuits (macrocells) which may be created or are included in the ASIC.
• This macrocell library identifies for each macrocell the connections between transistors or other components within one or more cells necessary to create the macrocell.
• the BiNMOS driver would be used to drive the output of most macrocells.
• a typical latch circuit in a macrocell library may resemble the circuit shown in Fig. 6, where transistors Q3 and Q4 operate as the BiNMOS driver.
• input signal IN is applied to the input of inverter 58 upon an occurrence of a high CLK signal.
• the inverted signal at the output of inverter 58 is applied to the gate of N- channel transistor Q4, turning transistor Q4 off.
• the inverted output of inverter 58 is inverted by inverter 60 so as to apply a high signal to the base of bipolar transistor Q3, turning transistor Q3 on and providing a high output signal at output terminal 61.
• P-channel transistor 56 eliminates the V BE drop across transistor Q3 when the output at terminal 61 is a logical high.
• P-channel transistor 62 causes the full power supply voltage to be applied to the input of inverter 58 when the output of inverter 58 is low.
• the BiNMOS driver may also be used in a tristate output configuration wherein, in addition to the output being driven high or low, a high impedance state may be generated by applying a low signal to the base of the bipolar pull-up transistor and the gate of the N-channel pull-down transistor.
• Fig. 7 One such tristate device is shown in Fig. 7.
• enable signal E if enable signal E is low, the outputs of AND gates 64 and 66 will be low, causing transistors Q3 and Q4 to both be off and causing a high impedance to appear at output 68.
• enable signal E If enable signal E is high, the output signal at output 68 will correspond to the state of control signal X.
• P-channel transistor Q5 causes the signal at output 64 to be at a fully high voltage, and not lowered by V BE , when both signals E and X are high.
• Inverter 70 causes the gate of transistor Q5 to be low only when enable signal E is high.
• the driver circuits in Figs. 2-7 are preferably formed with the NPN bipolar transistor and the P-channel transistors in the same N-well to minimize die area. Additionally, multiple parallel emitters are preferably used to conduct a greater current.
• the circuits of Figs. 2-7 may be fabricated using any technology, such as Signetics' Sabre and HS4 technologies.

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• 1990
  • 1990-05-15 US US07/524,207 patent/US5068548A/en not_active Expired - Fee Related
• 1991
  • 1991-05-08 WO PCT/US1991/003192 patent/WO1991018448A1/en not_active Ceased
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