JP3152344B2 - Ceramic circuit board - Google Patents
Ceramic circuit boardInfo
- Publication number
- JP3152344B2 JP3152344B2 JP22147896A JP22147896A JP3152344B2 JP 3152344 B2 JP3152344 B2 JP 3152344B2 JP 22147896 A JP22147896 A JP 22147896A JP 22147896 A JP22147896 A JP 22147896A JP 3152344 B2 JP3152344 B2 JP 3152344B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- ceramic substrate
- weight
- ceramic
- aluminum plates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Laminated Bodies (AREA)
- Ceramic Products (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明はパワーモジュール用
基板等の半導体装置のセラミック回路基板に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic circuit board of a semiconductor device such as a power module board.
【０００２】[0002]
【従来の技術】従来、窒化物系のセラミック基板と金属
部材とが、１５〜３５重量％のＣｕと、１〜１０重量％
のＴｉ，Ｚｒ及びＮｂから選ばれた少なくとも１種と、
２０〜４０重量％のＷ，Ｍｏ，窒化アルミニウム，窒化
ケイ素及び窒化ホウ素から選ばれた少なくとも１種と、
残部にＡｇとを含む接合用組成物により接合されたセラ
ミックス−金属接合体が開示されている（特開平５−２
４６７６９）。この接合体では、窒化物系のセラミック
基板が窒化アルミニウム，窒化ケイ素，窒化ホウ素，サ
イアロン等により形成され、電子部品の回路となる金属
部材がＣｕ，Ｃｕ合金，Ｎｉ，Ｎｉ合金，Ｗ，Ｍｏ等に
より形成される。また上記接合用組成物はＡｇ−Ｃｕの
共晶組成（７２重量％Ａｇ−２８重量％Ｃｕ）若しくは
その近傍の組成のろう材成分を主とし、これにＴｉ，Ｚ
ｒ及びＮｂから選ばれた少なくとも１種の活性金属と、
Ｗ，Ｍｏ，窒化アルミニウム，窒化ケイ素及び窒化ホウ
素から選ばれた少なくとも１種とを配合して構成され
る。2. Description of the Related Art Conventionally, a nitride ceramic substrate and a metal member are composed of 15 to 35% by weight of Cu and 1 to 10% by weight.
At least one selected from Ti, Zr and Nb,
20 to 40% by weight of at least one selected from W, Mo, aluminum nitride, silicon nitride and boron nitride;
A ceramic-metal joined body joined by a joining composition containing Ag in the remainder is disclosed (Japanese Patent Laid-Open No. 5-2 / 1993).
46769). In this bonded body, a nitride ceramic substrate is formed of aluminum nitride, silicon nitride, boron nitride, sialon, or the like, and a metal member serving as a circuit of an electronic component is formed of Cu, Cu alloy, Ni, Ni alloy, W, Mo, or the like. Formed by Further, the bonding composition mainly includes a brazing filler metal component having a eutectic composition of Ag-Cu (72% by weight of Ag-28% by weight of Cu) or a composition in the vicinity thereof.
at least one active metal selected from r and Nb;
W, Mo, aluminum nitride, silicon nitride, and at least one selected from boron nitride are blended.
【０００３】このように構成されたセラミック−金属接
合体では、窒化物系のセラミック基板に熱膨張係数が近
似した熱応力緩和成分を配合した接合用組成物を、上記
セラミック基板及び金属部材間に介在させた状態で加熱
接合するので、中間接合層となる上記接合用組成物の熱
膨張係数がセラミック基板と金属部材との中間的な値を
示す。この結果、上記中間接合層が窒化物系セラミック
部材と金属部材との熱膨張係数の差に起因する熱応力の
緩和層として機能するため、セラミック基板側に過度の
応力が働くことを防止できる。従って、熱サイクルが付
加されても、セラミック基板側のクラック等の発生を抑
制できるようになっている。[0003] In the ceramic-metal bonded body configured as described above, a bonding composition in which a nitride-based ceramic substrate is blended with a thermal stress relaxation component having a similar thermal expansion coefficient is mixed between the ceramic substrate and the metal member. Since the heat bonding is performed in the state of being interposed, the thermal expansion coefficient of the bonding composition to be an intermediate bonding layer has an intermediate value between the ceramic substrate and the metal member. As a result, the intermediate bonding layer functions as a layer for relieving thermal stress caused by a difference in thermal expansion coefficient between the nitride-based ceramic member and the metal member, thereby preventing an excessive stress from acting on the ceramic substrate side. Therefore, even if a heat cycle is added, generation of cracks and the like on the ceramic substrate side can be suppressed.
【０００４】[0004]
【発明が解決しようとする課題】しかし、上記従来のセ
ラミックス−金属接合体では、ＣｕやＣｕ合金等により
形成された金属部材の変形抵抗が比較的大きいため、熱
サイクルを付加すると、接合用組成物で窒化物系のセラ
ミック基板に作用する熱応力が多少緩和されるけれど
も、このセラミック基板に作用する熱応力は未だ大き
い。この結果、熱サイクルが繰返し付加されると、セラ
ミック基板にクラックが発生する場合があった。本発明
の目的は、熱サイクルを繰返し付加してもセラミック基
板にクラックが発生しないセラミック回路基板を提供す
ることにある。However, in the above-mentioned conventional ceramic-metal joined body, the deformation resistance of the metal member formed of Cu or Cu alloy is relatively large. Although the thermal stress acting on the nitride-based ceramic substrate is somewhat reduced, the thermal stress acting on this ceramic substrate is still large. As a result, when a thermal cycle is repeatedly applied, cracks may occur in the ceramic substrate. An object of the present invention is to provide a ceramic circuit board in which cracks do not occur in a ceramic substrate even when a thermal cycle is repeatedly applied.
【０００５】[0005]
【課題を解決するための手段】請求項１に係る発明は、
図１に示すように、Ｓｉ3Ｎ4により形成されたセラミッ
ク基板１３と、セラミック基板１３の両面にＡｌ−Ｓｉ
系ろう材を介してそれぞれ積層接着された第１及び第２
アルミニウム板１１，１２とを備えたセラミック回路基
板であって、Ａｌ−Ｓｉ系ろう材が９３．５〜９１．５
重量％のＡｌと６．５〜８．５重量％のＳｉとを含む合
金により形成されたことを特徴とする。この請求項１に
係るセラミック回路基板では、第１及び第２アルミニウ
ム板１１，１２が従来のＣｕやＣｕ合金等にて形成され
た金属部材と比べて変形抵抗が小さいので、回路基板１
０に熱サイクルを付加したときのセラミック基板１３に
作用する熱応力は小さい。この結果、セラミック基板１
３にクラックが発生しない。The invention according to claim 1 is
As shown in FIG. 1, a ceramic substrate 13 made of Si 3 N 4 and Al-Si
First and second laminated and bonded via a brazing filler metal
What ceramic circuit board der having an aluminum plate 11, is Al-Si based brazing material from 93.5 to 91.5
% Al and 6.5-8.5% Si by weight.
It is characterized by being formed of gold . In the ceramic circuit board according to the first aspect, since the first and second aluminum plates 11 and 12 have a lower deformation resistance than a conventional metal member formed of Cu, a Cu alloy, or the like, the circuit board 1
The thermal stress acting on the ceramic substrate 13 when a thermal cycle is applied to 0 is small. As a result, the ceramic substrate 1
No crack occurs in No. 3.
【０００６】請求項２に係る発明は、請求項１に係る発
明であって、更に図１に示すように、第１及び第２アル
ミニウム板１１，１２のＡｌの純度が９９．９８重量％
以上であることを特徴とする。この請求項２に係るセラ
ミック回路基板では、第１及び第２アルミニウム板１
１，１２のＡｌの純度を９９．９８重量％以上とする
と、第１及び第２アルミニウム板１１，１２の０．２％
耐力が２９ＭＰａと小さくなる。この結果、第１及び第
２アルミニウム板１１，１２の変形抵抗が小さくなるの
で、回路基板１０に熱サイクルを付加しても、セラミッ
ク基板１３に作用する熱応力はこのセラミック基板１３
にクラックが発生しない範囲となる。The invention according to claim 2 is the invention according to claim 1, wherein the purity of Al in the first and second aluminum plates 11 and 12 is 99.98% by weight as shown in FIG.
It is characterized by the above. In the ceramic circuit board according to claim 2, the first and second aluminum plates 1
Assuming that the purity of Al of the first and second aluminum plates 11 and 12 is 99.98% by weight or more, 0.2%
The yield strength is reduced to 29 MPa. As a result, the deformation resistance of the first and second aluminum plates 11 and 12 is reduced, so that even if a thermal cycle is applied to the circuit board 10, the thermal stress acting on the ceramic substrate 13 is reduced.
In the range where no cracks occur.
【０００７】[0007]
【発明の実施の形態】次に本発明の実施の形態を図面に
基づいて詳しく説明する。図１に示すように、セラミッ
ク回路基板１０はＳｉ3Ｎ4により形成されたセラミック
基板１３と、このセラミック基板１３の両面にＡｌ−Ｓ
ｉ系ろう材（図示せず）を介してそれぞれ積層接着され
た第１及び第２アルミニウム板１１，１２とを備える。
第１及び第２アルミニウム板１１，１２はＡｌの純度が
９９．９８重量％以上の高純度のＡｌ合金により形成さ
れ、Ａｌ−Ｓｉ系ろう材は９３．５〜９１．５重量％の
Ａｌと６．５〜８．５重量％のＳｉとの合金により形成
される。Embodiments of the present invention will now be described in detail with reference to the drawings. As shown in FIG. 1, a ceramic circuit board 10 has a ceramic substrate 13 formed of Si 3 N 4 and Al-S
The first and second aluminum plates 11 and 12 are laminated and bonded via an i-type brazing material (not shown).
The first and second aluminum plates 11 and 12 are formed of a high-purity Al alloy having an Al purity of 99.98% by weight or more, and the Al-Si-based brazing material is made of 93.5 to 91.5% by weight of Al. It is formed by an alloy with 6.5 to 8.5% by weight of Si.
【０００８】セラミック基板１３の両面に第１及び第２
アルミニウム板１１，１２を積層接着するには、第１ア
ルミニウム板１１の上にＡｌ−Ｓｉ系ろう材、セラミッ
ク基板１３、Ａｌ−Ｓｉ系ろう材及び第２アルミニウム
板１２を重ねた状態で、これらに荷重０．５〜５ｋｇｆ
／ｃｍ2を加え、真空中で６００〜６３０℃に加熱する
ことにより行われる。積層接着後、第２アルミニウム板
１２はエッチング法により所定のパターンの回路とな
る。なお、第１アルミニウム板をエッチング法により所
定のパターンの回路としてもよく、また第１及び第２ア
ルミニウム板の両者をエッチング法により所定のパター
ンの回路としてもよい。[0008] First and second surfaces are provided on both sides of the ceramic substrate 13.
To laminate and bond the aluminum plates 11 and 12, the Al—Si-based brazing material, the ceramic substrate 13, the Al—Si-based brazing material, and the second aluminum plate 12 are stacked on the first aluminum plate 11. Load 0.5 ~ 5kgf
/ Cm 2 and heating in vacuum to 600-630 ° C. After lamination and bonding, the second aluminum plate 12 becomes a circuit having a predetermined pattern by an etching method. The first aluminum plate may be a circuit having a predetermined pattern by an etching method, or both the first and second aluminum plates may be circuits having a predetermined pattern by an etching method.
【０００９】[0009]
【実施例】次に本発明の実施例を比較例とともに図面に
基づいて詳しく説明する。 ＜実施例１＞図１に示すように、縦、横及び厚さがそれ
ぞれ５０．８ｍｍ、５０．８ｍｍ及び０．６３５ｍｍの
Ｓｉ3Ｎ4により形成されたセラミック基板１３と、縦、
横及び厚さがそれぞれ５０．８ｍｍ、５０．８ｍｍ及び
０．４ｍｍのＡｌ合金により形成された第１及び第２ア
ルミニウム板１１，１２と、縦、横及び厚さがそれぞれ
５０．８ｍｍ、５０．８ｍｍ及び０．０３ｍｍの図示し
ないＡｌ−Ｓｉ系ろう材とを用意した。第１及び第２ア
ルミニウム板１１，１２のＡｌの純度はともに９９．９
９９重量％であり、Ａｌ−Ｓｉ系ろう材はＡｌ−７．５
重量％Ｓｉ合金であった。また第１及び第２アルミニウ
ム板はＡｌの他に０．０００３重量％のＳｉと、０．０
００２重量％のＦｅと、０．０００１重量％のＣｕとを
含んでいた。第１アルミニウム板１１の上にＡｌ−Ｓｉ
系ろう材、セラミック基板１３、Ａｌ−Ｓｉ系ろう材及
び第２アルミニウム板１２を重ねた状態で、これらに荷
重５ｋｇｆ／ｃｍ2を加え、真空中で６３０℃に加熱す
ることにより、セラミック基板１３の両面に第１及び第
２アルミニウム板１１，１２を積層接着した。積層接着
後、第２アルミニウム板１２をエッチング法により所定
のパターンの回路として、セラミック回路基板１０を得
た。Next, embodiments of the present invention will be described in detail with reference to the drawings together with comparative examples. Example 1 As shown in FIG. 1, a ceramic substrate 13 formed of Si 3 N 4 having a length, width and thickness of 50.8 mm, 50.8 mm and 0.635 mm, respectively,
First and second aluminum plates 11 and 12 made of an Al alloy having a width and a thickness of 50.8 mm, 50.8 mm and 0.4 mm, respectively, and a length, a width and a thickness of 50.8 mm, 50. 8 mm and 0.03 mm Al-Si-based brazing materials (not shown) were prepared. The purity of Al in both the first and second aluminum plates 11 and 12 is 99.9.
99% by weight, and the Al-Si brazing material is Al-7.5.
It was a weight% Si alloy. The first and second aluminum plates were made of 0.0003% by weight of Si in addition to Al,
It contained 002% by weight of Fe and 0.0001% by weight of Cu. Al-Si on the first aluminum plate 11
In a state where the brazing material, the ceramic substrate 13, the Al-Si-based brazing material and the second aluminum plate 12 are stacked, a load of 5 kgf / cm 2 is applied thereto, and the ceramic substrate 13 is heated to 630 ° C. in a vacuum. The first and second aluminum plates 11 and 12 were laminated and adhered to both surfaces. After lamination and bonding, the ceramic circuit board 10 was obtained by using the second aluminum plate 12 as a circuit having a predetermined pattern by an etching method.
【００１０】＜実施例２＞第１及び第２アルミニウム板
が９９．９９重量％のＡｌと、０．００３重量％のＳｉ
と、０．００３重量％のＦｅと、０．００３重量％のＣ
ｕとを含むことを除いて、実施例１のセラミック回路基
板と同一に構成されたセラミック回路基板を実施例２と
した。 ＜実施例３＞第１及び第２アルミニウム板が９９．９８
重量％のＡｌと、０．００３重量％のＳｉと、０．００
３重量％のＦｅと、０．００３重量％のＣｕと、０．０
１重量％のＭｎとを含むことを除いて、実施例１のセラ
ミック回路基板と同一に構成されたセラミック回路基板
を実施例３とした。<Embodiment 2> The first and second aluminum plates are composed of 99.99% by weight of Al and 0.003% by weight of Si.
And 0.003% by weight of Fe and 0.003% by weight of C
A ceramic circuit board having the same configuration as that of the ceramic circuit board of the first embodiment except that u was included was used as a second embodiment. <Embodiment 3> First and second aluminum plates are 99.98.
% Al, 0.003% Si, 0.00%
3 wt% Fe, 0.003 wt% Cu, 0.0
A ceramic circuit board having the same configuration as the ceramic circuit board of Example 1 except that it contained 1% by weight of Mn was used as Example 3.
【００１１】＜比較例１＞第１及び第２アルミニウム板
が９９．９７重量％のＡｌと、０．００３重量％のＳｉ
と、０．００３重量％のＦｅと、０．００３重量％のＣ
ｕと、０．０２重量％のＭｎとを含むことを除いて、実
施例１のセラミック回路基板と同一に構成されたセラミ
ック回路基板を比較例１とした。 ＜比較例２＞第１及び第２アルミニウム板が９９．８５
重量％のＡｌと、０．０４重量％のＳｉと、０．０５重
量％のＦｅと、０．０３重量％のＣｕと、０．０３重量
％のＭｎとを含むことを除いて、実施例１のセラミック
回路基板と同一に構成されたセラミック回路基板を比較
例２とした。 ＜比較例３＞第１及び第２アルミニウム板が９９．５０
重量％のＡｌと、０．２０重量％のＳｉと、０．２５重
量％のＦｅと、０．０３重量％のＣｕと、０．０３重量
％のＭｎとを含むことを除いて、実施例１のセラミック
回路基板と同一に構成されたセラミック回路基板を比較
例３とした。Comparative Example 1 First and second aluminum plates were 99.97% by weight of Al and 0.003% by weight of Si
And 0.003% by weight of Fe and 0.003% by weight of C
Comparative Example 1 was a ceramic circuit board configured identically to the ceramic circuit board of Example 1 except that u and 0.02% by weight of Mn were included. <Comparative Example 2> First and second aluminum plates were 99.85.
Example, except that it contains Al wt%, 0.04 wt% Si, 0.05 wt% Fe, 0.03 wt% Cu, and 0.03 wt% Mn. Comparative Example 2 was made of a ceramic circuit board having the same configuration as that of the first ceramic circuit board. <Comparative Example 3> First and second aluminum plates were 99.50.
Examples except that the composition contains Al wt%, 0.20 wt% Si, 0.25 wt% Fe, 0.03 wt% Cu, and 0.03 wt% Mn. Comparative Example 3 was made of a ceramic circuit board having the same configuration as that of the first ceramic circuit board.
【００１２】＜比較例４＞図示しないが、実施例１と同
形同大のＳｉ3Ｎ4により形成されたセラミック基板と、
実施例１の第１及び第２アルミニウム板と同形同大のＣ
ｕ（無酸素銅或いはリン脱酸銅）により形成された第１
及び第２銅板とを用意した。また接合用組成物として重
量比でＡｇ：Ｃｕ：Ｔｉ：Ｗ＝４９．９：１９．０：
２．０：３０．０の混合粉末を用意し、この混合粉末１
００重量部に、カルボキシル基重合したアクリル樹脂を
１０重量部、テレピネオールを２０重量部、オレイン酸
を０．１ｃｃ加え、十分に混合して接合用ペーストを作
製した。第１及び第２銅板の各々一方の表面に上記接合
用ペーストをスクリーン印刷して乾燥し、上記セラミッ
ク基板の両面に接合用ペーストの塗布層を有する第１及
び第２銅板を積層した。この積層物を所定の雰囲気中で
所定の温度で熱処理することにより、セラミック基板の
両面に第１及び第２銅板を積層接着し、第２銅板をエッ
チング法により所定のパターンの回路とした。このセラ
ミック回路基板を比較例４とした。<Comparative Example 4> Although not shown, a ceramic substrate formed of Si 3 N 4 of the same shape and size as in Example 1;
C of the same shape and size as the first and second aluminum plates of Example 1
u (oxygen-free copper or phosphorus deoxidized copper)
And a second copper plate. Ag: Cu: Ti: W = 49.9: 19.0:
A mixed powder of 2.0: 30.0 was prepared.
To 100 parts by weight, 10 parts by weight of a carboxyl group-polymerized acrylic resin, 20 parts by weight of terpineol, and 0.1 cc of oleic acid were added and thoroughly mixed to prepare a bonding paste. The bonding paste was screen-printed and dried on one surface of each of the first and second copper plates, and the first and second copper plates having a coating layer of the bonding paste on both surfaces of the ceramic substrate were laminated. This laminate was heat-treated at a predetermined temperature in a predetermined atmosphere to laminate and bond the first and second copper plates on both surfaces of the ceramic substrate, and the second copper plate was formed into a circuit having a predetermined pattern by an etching method. This ceramic circuit board was used as Comparative Example 4.
【００１３】＜比較試験及び評価＞実施例１〜３及び比
較例１〜４のセラミック回路基板を、先ず−５５℃に３
０分間さらし、次いで室温に１０分間さらし、次に１５
０℃に３０分間さらし、更に室温に１０分間さらした。
これを１サイクルとして温度サイクル試験をそれぞれ１
０００回行った。それぞれの試験で温度サイクルが１０
回、１００回、２００回、４００回、７００回及び１０
００回になった時点で、倍率１０倍の顕微鏡により上記
回路基板のセラミック基板にクラックが発生しているか
否かをそれぞれ観察した。その結果を表１に示す。表１
において、「１」はセラミック基板にクラックが全く発
生していなかったことを示し、「２」はセラミック基板
に僅かにクラックが発生していたことを示し、「３」は
セラミック基板に多くのクラックが発生していたことを
示す。<Comparative Test and Evaluation> The ceramic circuit boards of Examples 1 to 3 and Comparative Examples 1 to 4 were first heated to -55 ° C.
0 minutes, then 10 minutes at room temperature, then 15 minutes
Exposure to 0 ° C. for 30 minutes and further to room temperature for 10 minutes.
This is regarded as one cycle, and each temperature cycle test is
000 times. 10 temperature cycles in each test
Times, 100 times, 200 times, 400 times, 700 times and 10 times
At the time when the number of times was 00, the ceramic substrate of the circuit board was observed for any cracks with a microscope with a magnification of 10 times. Table 1 shows the results. Table 1
In Table 1, "1" indicates that no cracks occurred on the ceramic substrate, "2" indicates that slight cracks occurred on the ceramic substrate, and "3" indicates many cracks on the ceramic substrate. Indicates that the error occurred.
【００１４】[0014]
【表１】 [Table 1]
【００１５】表１から明らかなように、実施例１〜３で
はセラミック基板に全くクラックが発生しなかったのに
対し、比較例１〜６では温度サイクル７００回後、４０
０回後及び２００回後にセラミック基板にそれぞれクラ
ックが発生していた。この結果、第１及び第２アルミニ
ウム板のＡｌの純度が９９．９８重量％以上であれば、
セラミック基板にクラックが発生しないことが判った。
またセラミック基板の両面に第１及び第２銅板を積層接
着した比較例４の回路基板では、温度サイクル１００回
後にセラミック基板にクラックが既に発生していた。As is clear from Table 1, cracks did not occur at all in the ceramic substrates in Examples 1 to 3, whereas in Comparative Examples 1 to 6, 40 cycles after 700 temperature cycles.
Cracks occurred in the ceramic substrate after 0 times and 200 times, respectively. As a result, if the purity of Al of the first and second aluminum plates is 99.98% by weight or more,
It was found that no cracks occurred on the ceramic substrate.
Further, in the circuit board of Comparative Example 4 in which the first and second copper plates were laminated and bonded to both sides of the ceramic substrate, cracks had already occurred in the ceramic substrate after 100 temperature cycles.
【００１６】[0016]
【発明の効果】以上述べたように、本発明によれば、セ
ラミック基板をＳｉ3Ｎ4により形成し、このセラミック
基板の両面にＡｌ−Ｓｉ系ろう材を介して第１及び第２
アルミニウム板をそれぞれ積層接着し、更にＡｌ−Ｓｉ
系ろう材を９３．５〜９１．５重量％のＡｌと６．５〜
８．５重量％のＳｉとを含む合金により形成したので、
この回路基板に熱サイクルを付加しても、セラミック基
板と第１及び第２アルミニウム板との熱膨張係数の差に
よる歪みが従来のＣｕやＣｕ合金等にて形成された金属
部材と比べて変形抵抗の小さい第１及び第２アルミニウ
ム板の弾性変形により吸収される。またこのときのセラ
ミック基板に作用する熱応力は小さいので、セラミック
基板にクラックが発生することはない。また第１及び第
２アルミニウム板のＡｌの純度が９９．９８重量％以上
であれば、第１及び第２アルミニウム板の０．２％耐力
が２９ＭＰａと小さくなる。この結果、第１及び第２ア
ルミニウム板の変形抵抗が小さくなるので、回路基板に
熱サイクルを付加しても、セラミック基板に作用する熱
応力はこのセラミック基板にクラックが発生しない範囲
となる。As described above, according to the present invention, according to the present invention, the ceramic substrate is formed by Si 3 N 4, the first and second via Al-Si based brazing material on both surfaces of the ceramic substrate
Aluminum plates are laminated and bonded, and Al-Si
93.5 to 91.5% by weight of Al and 6.5 to
Since it was formed by an alloy containing 8.5% by weight of Si ,
Even if a thermal cycle is applied to this circuit board, the distortion due to the difference in the coefficient of thermal expansion between the ceramic substrate and the first and second aluminum plates is deformed as compared with a conventional metal member made of Cu or Cu alloy. It is absorbed by the elastic deformation of the first and second aluminum plates having a small resistance. Further, since the thermal stress acting on the ceramic substrate at this time is small, no crack is generated on the ceramic substrate. If the purity of Al in the first and second aluminum plates is 99.98% by weight or more, the 0.2% proof stress of the first and second aluminum plates is as small as 29 MPa. As a result, the deformation resistance of the first and second aluminum plates is reduced, so that even if a thermal cycle is applied to the circuit board, the thermal stress acting on the ceramic substrate falls within a range in which cracks do not occur in the ceramic substrate.
【図１】本発明一実施形態のセラミック回路基板を示す
縦断面図。FIG. 1 is a longitudinal sectional view showing a ceramic circuit board according to an embodiment of the present invention.
１０ セラミック回路基板 １１ 第１アルミニウム板 １２ 第２アルミニウム板 １３ セラミック基板 Reference Signs List 10 ceramic circuit board 11 first aluminum plate 12 second aluminum plate 13 ceramic substrate
フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｈ０５Ｋ 3/38 Ｈ０１Ｌ 23/14 Ｃ (72)発明者 初鹿 昌文 埼玉県大宮市北袋町１丁目297番地 三 菱マテリアル株式会社総合研究所内 (56)参考文献 特開 平５−191018（ＪＰ，Ａ) 特開 平７−227680（ＪＰ，Ａ) 特開 平８−319187（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H05K 1/09 B32B 18/00 C04B 37/02 H01L 23/15 H05K 1/03 610 H05K 3/38 Continued on the front page (51) Int.Cl. 7 Identification code FI H05K 3/38 H01L 23/14 C (72) Inventor Masafumi Hatsuka 1-297 Kitabukurocho, Omiya City, Saitama Prefecture 56) References JP-A-5-191018 (JP, A) JP-A-7-227680 (JP, A) JP-A-8-319187 (JP, A) (58) Fields investigated (Int. Cl. 7 , (DB name) H05K 1/09 B32B 18/00 C04B 37/02 H01L 23/15 H05K 1/03 610 H05K 3/38
Claims (2)
板(13)と、 前記セラミック基板(13)の両面にＡｌ−Ｓｉ系ろう材を
介してそれぞれ積層接着された第１及び第２アルミニウ
ム板(11,12)とを備えたセラミック回路基板であって、 前記Ａｌ−Ｓｉ系ろう材が９３．５〜９１．５重量％の
Ａｌと６．５〜８．５重量％のＳｉとを含む合金により
形成されたことを特徴とするセラミック回路基板 。1. A ceramic substrate (13) formed of Si 3 N 4, and first and second aluminum plates laminated and bonded to both surfaces of the ceramic substrate (13) via an Al—Si brazing material, respectively. (11, 12) , wherein the Al-Si brazing material is 93.5 to 91.5% by weight.
By alloy containing Al and 6.5 to 8.5% by weight of Si
A ceramic circuit board, wherein the ceramic circuit board is formed .
Ａｌの純度が９９．９８重量％以上である請求項１記載
のセラミック回路基板。2. The ceramic circuit board according to claim 1, wherein the first and second aluminum plates have an Al purity of at least 99.98% by weight.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22147896A JP3152344B2 (en) | 1996-08-22 | 1996-08-22 | Ceramic circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22147896A JP3152344B2 (en) | 1996-08-22 | 1996-08-22 | Ceramic circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1065296A JPH1065296A (en) | 1998-03-06 |
| JP3152344B2 true JP3152344B2 (en) | 2001-04-03 |
Family
ID=16767347
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22147896A Expired - Lifetime JP3152344B2 (en) | 1996-08-22 | 1996-08-22 | Ceramic circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3152344B2 (en) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4649027B2 (en) * | 1999-09-28 | 2011-03-09 | 株式会社東芝 | Ceramic circuit board |
| DE10165080B4 (en) | 2000-09-20 | 2015-05-13 | Hitachi Metals, Ltd. | Silicon nitride powder and sintered body and method of making the same and printed circuit board therewith |
| JP4434545B2 (en) | 2001-03-01 | 2010-03-17 | Ｄｏｗａホールディングス株式会社 | Insulating substrate for semiconductor mounting and power module |
| JP4779178B2 (en) * | 2001-03-01 | 2011-09-28 | Ｄｏｗａメタルテック株式会社 | Insulating substrate for semiconductor mounting and power module |
| JP4554105B2 (en) * | 2001-04-05 | 2010-09-29 | 電気化学工業株式会社 | Circuit board and module |
| JP3915722B2 (en) * | 2003-03-20 | 2007-05-16 | 三菱マテリアル株式会社 | Circuit board manufacturing method and manufacturing apparatus |
| US7482685B2 (en) | 2003-09-25 | 2009-01-27 | Kabushiki Kaisha Toshiba | Ceramic circuit board, method for making the same, and power module |
| JP5061442B2 (en) * | 2005-09-15 | 2012-10-31 | 三菱マテリアル株式会社 | Insulated circuit board and insulated circuit board with cooling sink |
| JP4747284B2 (en) * | 2005-09-15 | 2011-08-17 | 三菱マテリアル株式会社 | Insulated circuit board with cooling sink |
| JP4998100B2 (en) * | 2007-06-11 | 2012-08-15 | 三菱マテリアル株式会社 | Power module substrate and power module |
| JP5131204B2 (en) * | 2009-01-13 | 2013-01-30 | 三菱マテリアル株式会社 | Power module substrate manufacturing method |
| EP2492958B1 (en) * | 2009-10-22 | 2023-09-13 | Mitsubishi Materials Corporation | Substrate for power module, substrate with heat sink for power module, power module, method for producing substrate for power module, and method for producing substrate with heat sink for power module |
| JP5664038B2 (en) * | 2010-09-07 | 2015-02-04 | 三菱マテリアル株式会社 | Power module substrate, power module substrate manufacturing method, and power module |
| CN102054826B (en) * | 2010-11-04 | 2013-01-09 | 嘉兴斯达微电子有限公司 | Novel baseplate-free power module |
| JP5699882B2 (en) * | 2011-09-22 | 2015-04-15 | 三菱マテリアル株式会社 | Power module substrate, power module substrate manufacturing method, power module substrate with heat sink, and power module |
| JP5910166B2 (en) * | 2012-02-29 | 2016-04-27 | 三菱マテリアル株式会社 | Power module substrate manufacturing method |
-
1996
- 1996-08-22 JP JP22147896A patent/JP3152344B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1065296A (en) | 1998-03-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3171234B2 (en) | Ceramic circuit board with heat sink | |
| JP3152344B2 (en) | Ceramic circuit board | |
| JP3180677B2 (en) | Ceramic circuit board with heat sink | |
| KR100477866B1 (en) | Metal-Ceramic Composite Substrate, Method of Manufacturing the Same, and Soldering Materials Used in the Method | |
| JP3461829B2 (en) | Power semiconductor device having buffer layer | |
| EP1039539A2 (en) | Ceramic circuit board | |
| WO2005032225A1 (en) | Ceramic circuit board, method for making the same, and power module | |
| JP4104253B2 (en) | Board integrated structure | |
| JP2001332854A (en) | Ceramic circuit board | |
| JPH05218229A (en) | Ceramic circuit board | |
| JP2001144234A (en) | Semiconductor mounting insulation circuit substrate | |
| JPH05347469A (en) | Ceramic circuit board | |
| JP3997293B2 (en) | Method for manufacturing metal-ceramic composite substrate having point bonding or line bonding | |
| JP4467659B2 (en) | Ceramic circuit board | |
| JP5016756B2 (en) | Nitride-based ceramic member and metal member joined body and nitride-based ceramic circuit board using the same | |
| JP4244723B2 (en) | Power module and manufacturing method thereof | |
| JP2000119071A (en) | Ceramic substrate for semiconductor device | |
| JPH08102570A (en) | Ceramic circuit board | |
| JP2003007939A (en) | Ceramic circuit board with heat sink and manufacturing method therefor | |
| JP2003133662A (en) | Ceramic circuit board | |
| JP2712778B2 (en) | Manufacturing method of metal / ceramic composite substrate | |
| JP3833410B2 (en) | Ceramic circuit board | |
| JP2861357B2 (en) | Aluminum nitride-copper bonding method | |
| JP4407858B2 (en) | Module structure | |
| JP3190282B2 (en) | Circuit board manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20001228 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080126 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090126 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090126 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100126 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100126 Year of fee payment: 9 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100126 Year of fee payment: 9 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110126 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120126 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130126 Year of fee payment: 12 |
|
| EXPY | Cancellation because of completion of term |