JP4998100B2 - Power module substrate and power module - Google Patents

Description

The present invention relates to a power module substrate and a power module used in a semiconductor device that controls a large current and a high voltage.

In general, a power module for supplying power among semiconductor elements has a relatively high calorific value, and as a power module substrate, for example, a ceramic substrate made of AlN, Al ₂ O ₃ , Si ₃ N ₄ , SiC, or the like is used. In addition, an aluminum layer bonded with a brazing material such as Al—Si is used. This aluminum layer becomes a circuit layer by forming a circuit in etching in a later step. After the etching, an electronic component (power element such as a semiconductor chip) is mounted on the surface of the circuit layer via a solder material to form a power module.

  A conductor pattern (circuit) is formed on the circuit layer by the etching. In the conductor pattern, a gap or a hole is provided between the circuits, and the circuits are insulated from each other. In general, as the etching, a mask having a predetermined pattern is applied to the surface of the circuit layer with a resist film, and the circuit layer is dissolved by immersing or spraying this liquid to form a predetermined circuit shape. A so-called wet etching method is known.

  By the way, in recent years, power modules are required to have higher current and higher voltage for various applications, and downsizing and cost reduction of devices are required. How are they formed on this circuit layer? Attention has been paid to whether or not the gap between each circuit can be reduced. In order to reduce the distance between the circuits in the circuit layer, it is necessary to form the walls of the grooves and holes forming the gap as perpendicular to the surface of the circuit layer as possible.

 However, in actuality, during wet etching, as the etching solution dissolves in the shape of grooves and holes in the direction in which the circuit layer is laminated, the amount of liquid entering gradually decreases and the solution pools. The wall surface of the groove or hole that is lowered is gradually inclined toward the deep part, and is formed with a gentle gradient.

 If the deep part of the wall surface has a gentle slope and a gentle gradient, the adjacent wall surfaces may come into contact with each other, resulting in a poor insulation of the circuit. Further, if the distance between the circuits is made larger than necessary as a measure for preventing this insulation failure, it is difficult to reduce the size of the entire device.

Therefore, as a means for forming the wall surfaces forming the gaps between the circuits as vertically as possible, for example, Patent Document 1 discloses a method focusing on the components of the mixed solution constituting the etching solution. According to this method, the wall surface can be formed in a nearly vertical shape by specifying the components of the mixed solution. The wall surface has an inclined horizontal width dimension of 200 μm or less, or a ratio of the horizontal width dimension to the inclined thickness dimension of the circuit layer is 0.5 or less.
JP 2004-356502 A

 However, in the method of Patent Document 1, it is necessary to always keep the components of the mixed solution constituting the etching solution in a specific state. Since other elements such as components that dissolve from the circuit layer are also mixed, it was difficult to maintain and maintain this liquid with high precision. Also, the inclination of the wall surface has recently been required to be more perpendicular than the above-mentioned value, and these have been problems.

The present invention has been made in view of the above-described problems, and provides a power module substrate and a power module that can be well insulated from each other in a circuit layer and can be reduced in size and price. Objective.

In order to achieve the above object, the present invention proposes the following means. That is, the present invention is a power module substrate in which a circuit layer is formed by etching an aluminum layer bonded on a surface of a ceramic substrate, and the aluminum layer is made of aluminum having a purity of 99.99% or more. The circuit layer is characterized in that the Si content within 200 μm from the bonding interface with the ceramic substrate is 0.7 wt% or more and 1.2 wt% or less.

  According to the power module substrate according to the present invention, the circuit layer has a Si content within 200 μm from the bonding interface between the ceramic substrate and the circuit layer, and is 0.7 wt% or more and 1.2 wt% or less. When this circuit layer is formed by etching, the etching solution dissolves and forms the gaps between the circuits in the form of grooves or holes in the circuit layer in the stacking direction, and abundantly contains Si in the deep part. Since the layer contained in is exposed, the dissolution is satisfactorily performed to the deep part without reducing the dissolving power of the etching solution. Therefore, the inclination of the wall surface forming the gap can be formed as vertical as possible.

  In the power module substrate according to the present invention, the inclination of the wall surface between the circuits of the circuit layer is such that the width dimension in the bonding interface direction is 54 μm or less, or the ratio of the width dimension to the thickness dimension of the circuit layer is It may be 0.09 or less. The power module according to the present invention is characterized in that an electronic component is mounted on the surface of the circuit layer of the power module substrate.

 According to the power module substrate and the power module of the present invention, the inclination of the wall surface between the circuits formed in the circuit layer is such that the width dimension in the bonding interface direction is 54 μm or less, or the thickness dimension of the circuit layer is The width dimension ratio is 0.09 or less, and the width is as narrow as possible. And this wall surface is formed in the shape near perpendicular | vertical as much as possible with respect to the surface of the said circuit layer. Accordingly, the distance between the circuits in the circuit layer can be reduced as much as possible, and the circuits can be well insulated from each other.

According to the power module substrate and the power module of the present invention, the circuits in the circuit layer are well insulated from each other, and can be reduced in size and cost.

  Embodiments of the present invention will be described below with reference to the drawings. 1 to 5 are schematic views showing a manufacturing process of a power module substrate according to an embodiment of the present invention, and FIG. 6 is an enlarged view of a wall surface forming a gap between circuits of a circuit layer.

As shown in FIGS. 1 and 2, in order to manufacture this power module substrate, first, the purity of the flat ceramic substrate 1 made of AlN, Al ₂ O ₃ , Si ₃ N ₄ , SiC or the like is set on the surface. A flat aluminum layer 2 made of 99.99% or more of aluminum is disposed, and between them, Al-10.5% Si of 15 μm to 20 μm, or Al-7.5% Si of 25 μm to 30 μm. The following brazing material foils 3 are interposed, and these are brazed and joined while applying pressure in the laminating direction. The joined aluminum layer 2 is used as a circuit layer 2a for forming a circuit of the power module substrate in a later etching process.

Next, as shown in FIG. 3, a resist film 4 having a predetermined conductor pattern (circuit) shape is formed on the surface of the circuit layer 2 a (aluminum layer 2) on the ceramic substrate 1. Then, a ferric chloride solution (FeCl ₃ concentration of 44% or more, FeCl ₂ concentration of 0.13% or less, HCL (free acid) concentration of 0.15% or less, specific gravity (Baume degree) 47 as an etching solution in the circuit layer 2a. The circuit is formed by spraying using ± 2 ° and dissolving by etching. As shown in FIG. 4, the gap 5 between the groove-like and hole-like circuits formed by this etching is directed from the surface side of the resist film 4 to the surface side of the ceramic substrate 1 in the stacking direction. Will be formed.

 Then, the dissolution by this etching proceeds to the position of the bonding interface 6 between the ceramic substrate 1 and the circuit layer 2a as shown in FIG. In this melting, first, a wall surface 5a extending from the surface side of the circuit layer 2a is formed, and a wall surface 5b having a different inclination is formed as the wall surface 5a goes to the deep portion in the stacking direction, and the wall surface 5b reaches the bonding interface 6. Thus, this gap 5 is formed. The gap 5 electrically isolates the circuit 7a and the circuit 7b disposed on both sides of the gap 5 and insulates them. After the etching, the resist film 4 is removed, and the power module substrate 10 is obtained.

  As shown in FIG. 6, the wall surfaces 5a and 5b have different slopes. The wall surface 5a has a relatively steep slope and is formed with a slope that is nearly perpendicular to the surface of the circuit layer 2a. Further, the wall surface 5b is formed with a gentler slope than the wall surface 5a because the dissolving power slightly decreases as the etching solution enters the deep part of the gap 5 during etching.

  Here, the layer A adjacent to the bonding interface 6 of the circuit layer 2a contains 0.7 wt% or more and 1.2 wt% or less of Si diffused from the brazing material foil 3 at the time of brazing. In the present embodiment, the thickness t of the circuit layer 2a is 600 μm, and the layer A is 200 μm. The continuously formed wall surfaces 5a and 5b have a width dimension W1 in the direction of the bonding interface 6 of 54 μm or less. The wall surfaces 5a and 5b are formed such that the inclination thereof is 0.09 or less in terms of the ratio of the width dimension W1 to the thickness dimension t of the circuit layer 2a.

  By the way, in the conventional power module substrate, the layer A adjacent to the bonding interface 6 of the circuit layer 2a does not contain as much Si as in the present embodiment, and is generally less than 0.7 wt%. Further, as shown by a two-dot chain line in FIG. 6, the slope of the wall surface 5b formed by etching is also formed with a gentler slope than the wall surface 5b (solid line) of the present embodiment. Then, the width dimension W2 of the continuous wall surfaces 5a and 5b in the direction of the bonding interface 6 is formed larger than the width dimension W1 of the present embodiment.

 According to the embodiment of the present invention, the aluminum layer 2 made of aluminum having a purity of 99.99% or more is laminated on the surface of the ceramic substrate 1, and the Al-10. The brazing material foil 3 having a thickness of 15 μm or more and 20 μm or less made of 5% Si is interposed, or the brazing material foil 3 made of Al-7.5% Si and having a thickness of 25 μm or more and 30 μm or less is interposed. . The Si content in the layer A within 200 μm from the junction interface 6 of the circuit layer 2a of the manufactured power module substrate 10 is set to 0.7 wt% or more and 1.2 wt% or less.

 Then, during etching, as the etching solution dissolves and forms the gaps 5 between the circuits in the form of grooves or holes in the circuit layer 2a in the laminating direction, a layer rich in Si in the deep part. Since A is exposed, the dissolution is satisfactorily performed to the deep part without reducing the dissolving power of the etching solution. Specifically, the inclination of the wall surfaces 5a and 5b of the gap 5 that insulates the circuits formed on the circuit layer 2a is such that the width dimension W1 in the direction of the bonding interface 6 is 54 μm or less, or the thickness dimension of the circuit layer 2a. The ratio of the width dimension W1 in the direction of the bonding interface 6 to t is 0.09 or less, so that the width is as narrow as possible.

 Therefore, the wall surfaces 5a and 5b are formed in a shape that is as perpendicular as possible to the surface of the circuit layer 2a. As a result, the distance 5 between these circuits of the circuit layer 2a can be formed as narrow as possible, and the circuits can be well insulated from each other, and the size and cost of the apparatus can be reduced.

 In addition, when the Si content of the layer A is less than 0.7 wt% as in the conventional case, the dissolving power of the etching solution is reduced, so that a sufficient effect cannot be obtained. When exceeding, there exists a possibility that the joining reliability at the time of the thermal cycle of this board | substrate 10 for power modules may be reduced. Therefore, it is preferable that the range of Si content is 0.7 wt% or more and 1.2 wt% or less of the present invention. And according to this range of Si content, these Si components prevent the movement of dislocations in the microstructure of the bonding interface 6 and prevent the refinement of crystal grains, so that cracks occur along the crystal grain boundaries. Therefore, the bonding reliability between the ceramic substrate 1 and the circuit layer 2a during the thermal cycle can be improved.

 The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the present embodiment, the method for manufacturing the power module substrate 10 has been described. However, in the subsequent process, an electronic component such as a semiconductor chip may be mounted on the surface of the power module substrate 10 to form a power module.

 Further, in the power module substrate 10 of the present embodiment, the circuit layer 2a is merely bonded to the surface of the ceramic substrate 1. However, the present invention is not limited to this, and for example, the circuit layer 2a is provided on the surface of the ceramic substrate 1. As a configuration in which the metal layer for heat dissipation is bonded to the back surface, layers may be formed on both surfaces of the ceramic substrate 1.

 In the present embodiment, the brazing material foil 3 is made of Al-10.5% Si having a thickness of 15 μm to 20 μm, or Al-7.5% Si having a thickness of 25 μm to 30 μm. As long as the brazing material contains the same Si, the brazing material foil 3 is not limited, and for example, a pasty brazing material may be used.

 In the present embodiment, the thickness dimension t of the circuit layer 2a is 600 μm, but the thickness dimension t is not limited to this, and the thickness dimension t may be increased or decreased. The wall surfaces 5a and 5b forming the gap 5 may be formed to have a ratio of the width dimension W1 to the thickness dimension t of the circuit layer 2a being 0.09 or less.

In this embodiment, ferric chloride solution (FeCl ₃ concentration 44% or more, FeCl ₂ concentration 0.13% or less, HCL (free acid) concentration 0.15% or less, specific gravity (Baume degree) 47 ± as an etching solution in this embodiment. However, the etching solution is not limited to this, and other etching solutions may be used as long as the etching solution has the same effect. Further, the etching method may be performed by dipping instead of spraying.

  In the present embodiment, for convenience of explanation, the wall surface of the gap 5 has been described as the wall surfaces 5a and 5b having different inclinations in the shallow portion and the deep portion in the stacking direction. The cross-sectional shape of 5b may be an arc shape that gently curves.

Hereinafter, the present invention will be specifically described by way of examples. However, the present invention is not limited to these examples.
[Example 1]
First, a ceramic substrate 1 made of AlN is prepared, an aluminum layer 2 made of aluminum having a purity of 99.99% is arranged on the surface, and a brazing filler metal foil 3 having a thickness of 20 μm of Al-10.5% Si is interposed therebetween. And joined. This brazing is performed by heating the laminated body composed of the ceramic substrate 1, the brazing material foil 3, and the aluminum layer 2 at 560 ° C. for 90 minutes in a state of being pressurized in the laminating direction, and then heating at 645 ° C. for 45 minutes. I went. And the board | substrate 10 for power modules whose thickness dimension t of the circuit layer 2a after brazing is 600 micrometers was obtained.

Then, a resist film 4 is formed on the surface of the circuit layer 2a (aluminum layer 2) of the power module substrate 10, and ferric chloride solution (FeCl ₃ concentration of 44% or more, FeCl ₂ concentration of 0.13 is formed on the circuit layer 2a. % And below, HCL (free acid) concentration 0.15% or less, specific gravity (Baume degree 47 ± 2 °), temperature 55 ± 1 ° C., treatment time 3 minutes to 20 minutes are performed for etching, A circuit was formed.

 After the etching, the resist film 4 is removed, the surface state of the circuit layer 2a of the power module substrate 10 is observed using a laser microscope, image processing is performed, and the gap 5 between the formed circuits is measured. The width dimension W of the wall surfaces 5a and 5b was measured. Further, the ratio of the width dimension W to the thickness dimension t of the circuit layer 2a was calculated. Further, the Si content contained in the layer A within 200 μm from the bonding interface 6 of the circuit layer 2a was analyzed. These results are shown in Table 1.

[Example 2]
Evaluation was performed in the same manner as in Example 1 except that the brazing foil 3 was made of Al-7.5% Si with a thickness of 26 μm.
[Comparative example]
As a conventional example, evaluation was performed in the same manner as in Example 1 except that the brazing foil was changed to Al-7.5% Si having a thickness of 17 μm.

 As shown in Table 1, in Example 1 and Example 2, the width dimension W and the ratio of the width dimension W to the thickness dimension t are both very small, and the wall surfaces 5a and 5b are vertical. It can be said that it is in a close state and a good result. And the amount of Si contained in the layer A was 0.7 wt% or more and 1.2 wt% or less. On the other hand, in the comparative example, both the width dimension W and the ratio of the width dimension W to the thickness dimension t are larger than those in the first and second embodiments, and the wall surfaces 5 a and 5 b are inclined in the deep part of the gap 5. Formed in a loose skirt shape. Further, the amount of Si contained in the layer A was less than 0.7 wt%.

It is the schematic which shows the manufacturing process of the board | substrate for power modules which concerns on one Embodiment of this invention. It is the schematic which shows the manufacturing process of the board | substrate for power modules which concerns on one Embodiment of this invention. It is the schematic which shows the manufacturing process of the board | substrate for power modules which concerns on one Embodiment of this invention. It is the schematic which shows the manufacturing process of the board | substrate for power modules which concerns on one Embodiment of this invention. It is the schematic which shows the manufacturing process of the board | substrate for power modules which concerns on one Embodiment of this invention. It is an enlarged view which shows the wall surface which forms the clearance gap between each circuit of a circuit layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Ceramic substrate 2 Aluminum layer 2a Circuit layer 3 Brazing material foil 5a, 5b Wall surface 6 Bonding interface 10 Power module substrate A Circuit layer side layer near the bonding interface t Circuit layer thickness dimension W1, W2 In the gap between each circuit Width dimension in the direction of the bonding interface of the formed wall

Claims (3)

A power module substrate in which a circuit layer is formed by etching an aluminum layer bonded on a surface of a ceramic substrate,
The aluminum layer is a flat plate made of aluminum having a purity of 99.99% or more,
The power module substrate, wherein the circuit layer has an Si content within 200 μm from a bonding interface with the ceramic substrate of 0.7 wt% or more and 1.2 wt% or less. The power module substrate according to claim 1,
The inclination of the wall surface between the circuits of the circuit layer is characterized in that the width dimension in the bonding interface direction is 54 μm or less, or the ratio of the width dimension to the thickness dimension of the circuit layer is 0.09 or less. Power module substrate.   An electronic component is mounted on a surface of the circuit layer of the power module substrate according to claim 1 or 2.

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