JP3143893U - マルチチップ封止パッケージ - Google Patents
マルチチップ封止パッケージ Download PDFInfo
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/732—Location after the connecting process
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
【解決手段】基板110と、DRAMチップ120と、フラッシュメモリチップ130と、第1の封止樹脂体170と、第2の封止樹脂体180と、複数のはんだボール190とを備える。DRAMチップ120およびフラッシュメモリチップ130は基板110上に順次重ねられる。第1の封止樹脂体170は、第1の表面111上に形成されるとともに、DRAMチップ120、およびフラッシュメモリチップ130を被覆する。第2の封止樹脂体180は、基板110の開口部113内に形成されるとともに、開口部113を被覆している。複数のはんだボール190は、基板110の第2の表面112上に配置されている。このようなパッケージによると、複数のチップを一つの封止構造内に重ねて設けるため、電子機器における占有空間を小さくすることができる。
【選択図】図1A
Description
(考案の効果)
(第1実施例)
本考案の第1実施例によるマルチチップ封止パッケージの概略を示す断面概略図を図1Aに示す。本実施例におけるマルチチップ封止パッケージ100は、基板110と、DRAMチップ120と、フラッシュメモリチップ(Flash Memory)チップ130と、コントローラチップ140と、第1のワイヤ150と、第2のワイヤ160と、第1の封止樹脂体170と、第2の封止樹脂体180と、複数のはんだボール(Solder Ball)190とを備える。
本実施例において、コントローラチップ140の面積はフラッシュメモリチップ130の面積未満であるか、またはコントローラチップ140は一部のみがフラッシュメモリチップ130上に配置されている。
はんだボール190は、例えばはんだボールマウンタ(図示しない)を用いて基板110の第2の表面112上に配置される。このうちはんだボール190の材料は、例えばスズ、アルミ、ニッケル、銀、銅、インジウムまたはその合金である。はんだボール190の第2の表面112上における高さは第2の封止樹脂体180の高さより少なくとも0.1mm以上高いので、マルチチップ封止パッケージ100がキャリアボード上に電気的に接続されたとき、はんだボール190のキャリアボードへの接合に、第2の封止樹脂体180が影響を及ぼすことはない。
本考案の第2実施例によるマルチチップ封止パッケージを図2に示す。第1実施例と比較すると、本実施例におけるマルチチップ封止パッケージ100aの基板110は、開口部113内に凹状に設けられるとともに、第1の表面111に連続している環状段差部116aを更に備える。
本考案の第3実施例によるマルチチップ封止パッケージを図3に示す。第1実施例と比較すると、本実施例によるマルチチップ封止パッケージ100bの基板110における環状段差部116bは、開口部113内に凹状に設けられるとともに、第2の表面112上に配置されている。この場合、環状段差部116bにはコンタクトパッド115bが設けられている。第2のワイヤ160は、DRAMチップ120の中央コンタクトパッドおよび環状段差部116b上のコンタクトパッド115bに電気的に接続される。
本考案では好ましい実施例を上記のように開示したが、これは本考案を限定するためのものではなく、当業者であれば、本考案の技術的思想および範囲を逸脱することなく、各種の変更および付加を行うことができるので、本考案の保護範囲は実用新案登録請求の範囲による限定を基準と見なす。
Claims (9)
- 第1の表面と、第2の表面と、前記第1の表面と前記第2の表面との間に設けられる開口部とを有する基板と、
前記基板の前記第1の表面上に配置されるとともに、アクティブエリアが前記開口部に対向しているDRAMチップと、
前記DRAMチップ上に配置されているフラッシュメモリチップと、
前記フラッシュメモリチップと前記基板との間を接続する少なくとも一本の第1のワイヤと、
前記開口部を介して前記DRAMチップの前記アクティブエリアと前記基板の前記第2の表面とを接続する少なくとも一本の第2のワイヤと、
前記基板の前記第1の表面上に形成され、前記DRAMチップ、前記フラッシュメモリチップおよび前記複数の第1のワイヤを被覆する第1の封止樹脂体と、
前記基板の前記開口部内に形成され、前記DRAMチップの前記アクティブエリアおよび前記第2のワイヤを被覆する第2の封止樹脂体と、
前記基板の前記第2の表面上に配置され、前記第2の表面上における高さが前記第2の封止樹脂体の高さよりも高くなっている複数のはんだボールと、
を備えることを特徴とするマルチチップ封止パッケージ。 - 前記フラッシュメモリチップ上に配置され、前記基板に電気的に接続されているコントローラチップを更に備えることを特徴とする請求項1に記載のマルチチップ封止パッケージ。
- 前記基板の第1の表面上に配置され、前記基板に電気的に接続されているコントローラチップを更に備えることを特徴とする請求項1に記載のマルチチップ封止パッケージ。
- 前記複数のはんだボールの前記第2の表面上における高さは、前記第2の封止樹脂体の高さよりも少なくとも0.1mm以上高いことを特徴とする請求項1に記載のマルチチップ封止パッケージ。
- 前記マルチチップ封止パッケージは、携帯電話機のキャリアボード上に電気的に接続されていることを特徴とする請求項1に記載のマルチチップ封止パッケージ。
- 前記キャリアボードは、プリント回路基板、フレキシブル回路基板またはメインボードのいずれか一つであることを特徴とする請求項5に記載のマルチチップ封止パッケージ。
- 前記開口部内に凹状に設けられるとともに、前記第1の表面に連続し、前記DRAMチップが係合される環状段差部を更に備えることを特徴とする請求項1に記載のマルチチップ封止パッケージ。
- 前記開口部内に凹状に設けられるとともに、前記第2の表面上に配置されている環状段差部を更に備え、前記第2のワイヤが前記DRAMチップと前記環状段差部上に電気的に接続されていることを特徴とする請求項1に記載のマルチチップ封止パッケージ。
- 第1の表面と、第2の表面と、前記第1の表面と前記第2の表面との間に設けられる開口部とを有する基板と、
前記基板の第1の表面上に配置されるとともに、アクティブエリアが前記開口部に対向しているDRAMチップと、
前記DRAMチップ上に配置されているフラッシュメモリチップと、
前記基板の第1の表面上に配置されているコントローラチップと、
前記フラッシュメモリチップと前記基板との間を接続する少なくとも一本の第1のワイヤと、
前記開口部を介して前記DRAMチップの他方の側と前記基板の前記第2の表面とを接続する少なくとも一本の第2のワイヤと、
前記コントローラチップと前記基板との間を電気的に接続する少なくとも一本の第3のワイヤと、
前記基板の前記第1の表面上に形成され、前記DRAMチップ、前記フラッシュメモリチップ、前記コントローラチップおよび前記複数の第1のワイヤを被覆する第1の封止樹脂体と、
前記基板の前記開口部内に形成されるとともに、前記DRAMチップの前記アクティブエリアおよび前記第2のワイヤを被覆する第2の封止樹脂体と、
前記基板の前記第2の表面上に配置され、前記第2の表面上における高さが前記第2の封止樹脂体の高さよりも高くなっている複数のはんだボールと、
前記基板内に埋設されている少なくとも一つの受動素子と、
を備えることを特徴とするマルチチップ封止パッケージ。
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US8405207B1 (en) | 2011-10-03 | 2013-03-26 | Invensas Corporation | Stub minimization for wirebond assemblies without windows |
US8436477B2 (en) | 2011-10-03 | 2013-05-07 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate |
US8441111B2 (en) | 2011-10-03 | 2013-05-14 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8502390B2 (en) | 2011-07-12 | 2013-08-06 | Tessera, Inc. | De-skewed multi-die packages |
US8513817B2 (en) | 2011-07-12 | 2013-08-20 | Invensas Corporation | Memory module in a package |
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US8670261B2 (en) | 2011-10-03 | 2014-03-11 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals |
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US8917532B2 (en) | 2011-10-03 | 2014-12-23 | Invensas Corporation | Stub minimization with terminal grids offset from center of package |
US8981547B2 (en) | 2011-10-03 | 2015-03-17 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
JP2015103782A (ja) * | 2013-11-28 | 2015-06-04 | 株式会社東芝 | 半導体装置 |
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US9123555B2 (en) | 2013-10-25 | 2015-09-01 | Invensas Corporation | Co-support for XFD packaging |
US9281296B2 (en) | 2014-07-31 | 2016-03-08 | Invensas Corporation | Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design |
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US9484080B1 (en) | 2015-11-09 | 2016-11-01 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
US9679613B1 (en) | 2016-05-06 | 2017-06-13 | Invensas Corporation | TFD I/O partition for high-speed, high-density applications |
CN112349705A (zh) * | 2019-08-08 | 2021-02-09 | 南茂科技股份有限公司 | 电子封装装置 |
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TWI401786B (zh) * | 2009-11-11 | 2013-07-11 | Optromax Electronics Co Ltd | 封裝結構 |
US9691437B2 (en) | 2014-09-25 | 2017-06-27 | Invensas Corporation | Compact microelectronic assembly having reduced spacing between controller and memory packages |
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2008
- 2008-02-14 TW TW097202729U patent/TWM338433U/zh not_active IP Right Cessation
- 2008-05-29 JP JP2008003543U patent/JP3143893U/ja not_active Expired - Lifetime
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