JP3109687B2 - Method for manufacturing conductive layer connection structure of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a conductive layer connection structure of a semiconductor device for electrically connecting an upper conductive layer and a lower conductive layer. The present invention relates to a method for manufacturing a conductive layer connection structure of a semiconductor device , which removes a film.

[0002]

2. Description of the Related Art Sputtering and CV are known as film forming techniques.
D (Chemical Vapor Deposition)
n). Sputtering has the characteristic that a film can be easily obtained without the need for adjusting the gas flow rate and temperature as in CVD. A method for forming the upper conductive layer using sputtering will be described below.

Referring to FIG. 12, an interlayer insulating film 3 is formed on lower conductive layer 5. A through hole 9 reaching the lower conductive layer 5 is formed in the interlayer insulating film 3. A
When r ions collide with the aluminum plate 1, aluminum atoms are repelled. If this is continued for a predetermined time, the state of FIG. 13 is changed to the state of FIG. Reference numeral 7 denotes an upper conductive layer made of aluminum.

In practice, however, aluminum atoms do not drop vertically as shown in FIG. 12, but aluminum atoms repelled by Ar ions are repelled to various directions as shown in FIG. Therefore, it is difficult to form an aluminum film at the corner 10 of the through hole 9.

With the miniaturization of devices, the opening size of the through hole 9 has been reduced. On the other hand, the interlayer insulating film 3
Is fixed at a substantially constant value in consideration of the danger of pinholes and the like. For this reason, the aspect ratio of the through hole (hole depth / hole opening size) must be increased. If the aspect ratio is high, the corners 10 of the through holes 9
Aluminum atoms are more difficult to reach. Therefore, the following problem occurs.

FIG. 16 shows a state in which the upper conductive layer 7 made of aluminum is formed on the interlayer insulating film 3 having the through hole 9 having a high aspect ratio. And FIG.
7 shows a state after the formation of the upper conductive layer 7 is completed. Before the through hole 9 is completely filled with aluminum, the opening of the through hole 9 is closed with aluminum.
Therefore, a void 11 is formed in the through hole 9.
The electrical resistance of the aluminum film in the through hole 9 increases due to the presence of the gap 11. Therefore, electromigration is likely to occur in this portion. Electromigration refers to a phenomenon in which metal atoms move when a large current stress is applied to the metal. When the metal atoms move in the opposite direction to the current, aluminum disappears on the cathode side and voids are generated, and on the anode side, aluminum hardens and hillocks and whiskers are generated. Failure due to electromigration is an increase in wiring resistance due to voids, and a short circuit between multilayer wiring due to disconnection and hillocks or whiskers.

Therefore, when the aspect ratio of the through hole is large, the upper conductive layer is formed by using the CVD method.
In the CVD method, a film is formed by the gas touching the surface on which the film is formed. If it is a gas, it can easily enter even the corner of the through hole. Therefore, even in a through hole having a large aspect ratio, the inside of the through hole can be completely buried.

A method for filling a through hole with a conductive layer using the CVD method will be described below. This method is, for example, 19
90 IEEE June 12-13, 1990 V
MIC Conference pp. 219-225 "CONTACT HOLE FILL WITH"
LOW TEMPERATURE LPCVD Ti
N "Ivo J. N. Raajijmakers et a
l.

As shown in FIG. 18, interlayer insulating film 19 is selectively etched away to form through hole 21 reaching impurity region 17. 13 is a silicon substrate, and 15 is a field oxide film. As shown in FIG. 19, a native oxide film 23 is formed on exposed impurity region 17 by oxygen in the atmosphere. If the natural oxide film 23 is present, the electrical connection between the impurity region 17 and a TiN film to be formed later cannot be made well, so the natural oxide film 23 is reduced as follows.

As shown in FIG. 20, a Ti film 25 is formed on the entire main surface of the silicon substrate 13 by using sputtering.

As shown in FIG. 21, a heat treatment is performed on the silicon substrate 13 in a nitrogen atmosphere. The temperature is 650 ° C. and the time is 30 seconds. Thereby, the portion of the Ti film that is in contact with the interlayer insulating film 19 becomes the TiN (O) film 29. The TiN (O) film is a film in which oxygen is dispersed in the TiN film.

In the portion of the Ti film that is in contact with the impurity region 17, Ti penetrates into the impurity region 17 and combines with Si in the impurity region 17 to form TiSi _x 27 (0 <x <2). Since TiSi _x may reductive, some of TiSi _x becomes TiSiO react with O in a natural oxide film. Thereby, the natural oxide film is reduced.

As shown in FIG. 22, a TiN film 31 is formed on the entire main surface of the silicon substrate 13 by using the CVD method. Since the through hole 21 is formed by the CVD method, the through hole 21 can be filled with the TiN film 31 even if the aspect ratio of the through hole 21 is high.

[0014] As shown in FIG.
An l-Cu film 33 is formed. The Al-Cu film 33 is formed to improve the conductivity of the wiring layer.

[0015]

However, in the conventional method, Si used to form TiSi _x 27 is supplied from impurity region 17. Thus, the reaction between Ti and Si progresses excessively, as shown in FIG. 24, TiSi _x
27 may penetrate impurity region 17. This destroys the pn junction and causes current leakage.

The present invention has been made to solve such a conventional problem. An object of the present invention is to provide a method for manufacturing a conductive layer connection structure of a semiconductor device, which can prevent a conductive layer used for reducing a native oxide film from excessively entering a lower conductive layer.

[0017]

[0018]

A method of manufacturing a conductive layer connection structure for a semiconductor device according to the present invention, which solves the above problem, selectively removes an insulating layer formed on a lower conductive layer by etching. Forming a through-hole reaching the surface of the through-hole and a CVD method using a gas containing titanium and a gas containing silicon to form a molecular structure of TiSi _x (0 <x <2) on at least the bottom surface of the through-hole.
Forming a titanium silicide layer having this Chitanshirisa
Forming a nitride layer to reduce a natural oxide film formed on the surface of the lower conductive layer forming the bottom surface of the through hole; and filling the entire through hole with the titanium silicide layer with TiN to form an upper conductive layer. forming a connection conductive layer which electrically connects the lower Bushirube conductive layer and an insulating layer
Contact connecting connection conductive layer and electrically to and forming an upper conductive layer.

[0019]

[0020]

[Action] In the manufacturing method of the conductive layer connecting structure of a semiconductor device of the present invention, Ru is formed by a CVD method TiSi
_The natural oxide film is reduced using a titanium silicide layer having a molecular structure of _x (0 <x <2) . That is , this
The silicon used to form the titanium silicide layer is
Supplied from a gas containing silicon , the natural oxide film is reduced when the titanium silicide layer is formed. Therefore,
The titanium silicide layer can prevent the lower conductive layer from excessively penetrating.

[0021]

[0022]

FIG. 1 shows an MO using the first embodiment of the present invention.
It is sectional drawing of an S field effect transistor. Impurity regions 37 are formed on silicon substrate 35 with a space therebetween. 39 is a gate oxide film, and 41 is a gate electrode. On the silicon substrate 35, an interlayer insulating film 43 is formed. In the interlayer insulating film 43, a through hole 49 reaching the impurity region 37 is formed. Through hole 49
The side walls of the impurity regions 37 and on the through-hole 49 of the inner TiSi _x film (titanium silicide film) 51 is formed. The through hole 49 is buried with the TiN film 53. An Al film 55 is formed on the interlayer insulating film 43, and the Al film 55 is electrically connected to the TiN film 53. 45 is an insulating film.

The first embodiment of the present invention will be described below. As shown in FIG. 2, an impurity region 59 is formed in the silicon substrate 57. 65 is a field oxide film. On the entire surface of the silicon substrate 57, an interlayer insulating film 61 is formed. In the interlayer insulating film 61, a through hole 63 reaching the impurity region 59 is formed.

As shown in FIG. 3, a natural oxide film 67 is formed on impurity region 59 by oxygen in the atmosphere.

In order to reduce the natural oxide film 67, a titanium silicide film 69 was formed by a CVD method as shown in FIG. The conditions are as follows.

Temperature: 700 to 800 ° C. Pressure: 20 to 40 Pa Gas flow rate: TiCl ₄ 25 sccm SiH ₄ 50 to 200 sccm Deposition rate: 20 to 40 nm / min The titanium silicide film formed by this CVD is:
A TiSi _x. Here, x is 0 <x <2. x <
The reason for setting the value to 2 is that when x = 2, titanium silicide becomes stable and the reducing property is weak. The reaction formula showing that the natural oxide film is reduced is as follows.

[0027] TiSi _x + SiO _y → TiSi _x O _y + Si SiO _y indicates a natural oxide film. y is a value close to 2. This is because the natural oxide film is not formed by actively supplying oxygen to silicon, and is not formed of SiO ₂ . All titanium silicides are made of TiS
i _x O _y become the not be. Most of the titanium silicide remains, and only a small amount of TiSi _x O _y is present in the titanium silicide. The above equation is an example showing the reduction of the natural oxide film, and the natural oxide film is actually reduced by various reactions.

As shown in FIG. 5, Ti is deposited by CVD.
An N film 71 was formed on the titanium silicide film 69. The conditions are as follows.

Temperature: 500 to 800 ° C. Pressure: _{1 to} 100 Pa Gas flow rate: TiCl ₄ 25 sccm NH ₃ 25 to 100 sccm Diluent gas: N ₂ 250 sccm Deposition rate: 7 to 15 nm / min Ar is used as a diluent gas. It is possible.

As shown in FIG. 6, the entire surface of the TiN film 71 and the titanium silicide film 69 is etched, and the titanium silicide film 69 and the TiN film 71 in the through hole 63 are etched.
To remove.

Next, as shown in FIG. 7, an Al film 73 was formed on the interlayer insulating film 61 by using a sputtering method. Thus, the first embodiment of the present invention has been completed.

In the first embodiment of the present invention, since the titanium silicide film 69 and the TiN film 71 are continuously formed by using the CVD method, the manufacturing time can be reduced.
Also, since the titanium nitride film is made of only TiN,
The electric resistance value can be reduced. That is, as the amount of oxygen contained in TiN increases, the electric resistance value increases. This is because 1987 American
Vacuum Society 1723-1729
Page "Nitrogen, oxygen, and
argon incorporation durin
g reactive sputter deposi
Tion of titanium nitride.

FIG. 8 is a sectional view of a conductive layer connection structure manufactured by using the second embodiment of the present invention. In the second embodiment, the natural oxide film on the impurity region 77 is formed by using the titanium silicide film 81 formed on the impurity region 77 by using the selective CVD method. 83 is a TiN film formed by using the CVD method. 75 is a silicon substrate, 79
Denotes a field oxide film, 85 denotes an interlayer insulating film, 87 denotes a through hole, and 89 denotes an Al film.

FIG. 9 is a sectional view of a conductive layer connection structure manufactured by using the third embodiment of the present invention. In the third embodiment, a W film 105 is used as an upper conductive layer. W film 10
5 has poor adhesion to the interlayer insulating film 101, so that the TiN film 9
9. The titanium silicide film 97 is left without being entirely etched. 91 is a silicon substrate, 93 is an impurity region, 9
Reference numeral 5 denotes a field oxide film, and reference numeral 103 denotes a through hole.

FIG. 10 is a sectional view of a conductive layer connection structure manufactured by using the fourth embodiment of the present invention. In the fourth embodiment,
In this case, a titanium silicide film 113 and a TiN film 115 are used as an upper conductive layer. In the fourth embodiment, since the conductive layer embedded in the through hole 119 is used as the upper conductive layer, the process of forming the upper conductive layer can be simplified.
Note that 107 is a silicon substrate, 109 is an impurity region, 1
Reference numeral 11 denotes a field oxide film, and 117 denotes an interlayer insulating film.

FIG. 11 is a reference example relating to the present invention.
It is a cross-sectional view of that conductive layer connecting structure. In this reference example, the through-hole 135 is not completely filled with the TiN film 129, and the W film 131 is formed in an open space. W
The film 131 is formed by a CVD method. W is TiN
Because of the low electrical resistance compared to, according to this reference example be from the first embodiment lowers the electric resistance becomes possible. In addition,
121 is a silicon substrate, 123 is an impurity region, 125 is a field oxide film, 127 is a titanium silicide film, 13
Reference numeral 3 denotes an interlayer insulating film, and 137 denotes an Al film.

[0037]

According to the present invention , TiSi _x (0 <x
CVD of titanium silicide layer having molecular structure of <2)
Reduces the native oxide film by forming
Therefore, it is possible to prevent the titanium silicide layer from biting into the lower conductive layer excessively . As a result, it is possible to prevent inconvenience such as destruction of a pn junction caused by excessive penetration of the titanium silicide layer into the lower conductive layer.

[0038]

[Brief description of the drawings]

FIG. 1 shows a MOS manufactured using a first embodiment of the present invention.
It is sectional drawing of a field effect transistor.

FIG. 2 is a sectional view showing a first step of the first embodiment of the present invention.

FIG. 3 is a sectional view showing a second step of the first embodiment of the present invention.

FIG. 4 is a sectional view showing a third step of the first embodiment of the present invention.

FIG. 5 is a sectional view showing a fourth step of the first embodiment of the present invention.

FIG. 6 is a sectional view showing a fifth step of the first embodiment of the present invention.

FIG. 7 is a sectional view showing a sixth step of the first embodiment of the present invention.

FIG. 8 is a sectional view of a conductive layer connection structure manufactured by using the second embodiment of the present invention.

FIG. 9 is a cross-sectional view of a conductive layer connection structure manufactured using a third embodiment of the present invention.

FIG. 10 is a sectional view of a conductive layer connection structure manufactured by using a fourth embodiment of the present invention.

FIG. 11 is a cross-sectional view of a conductive layer connection structure according to a reference example relating to the present invention.

FIG. 12 is a first process diagram showing a state in which an aluminum film is formed using ideal sputtering.

FIG. 13 is a second process diagram showing a state in which an aluminum film is formed using ideal sputtering.

FIG. 14 is a third process diagram showing a state in which an aluminum film is formed using ideal sputtering.

FIG. 15 is a diagram showing a state in which an aluminum film is formed by using actual sputtering.

FIG. 16 is a first process diagram showing a state in which an aluminum film is formed in a through hole having a high aspect ratio by using sputtering.

FIG. 17 is a second process diagram showing a state where an aluminum film is formed in a through hole having a high aspect ratio by using sputtering.

FIG. 18 is a cross-sectional view showing a first step in a conventional method for manufacturing a conductive layer connection structure of a semiconductor device.

FIG. 19 is a cross-sectional view showing a second step in the conventional method for manufacturing a conductive layer connection structure in a semiconductor device.

FIG. 20 is a cross-sectional view showing a third step in the conventional method for manufacturing a conductive layer connection structure in a semiconductor device.

FIG. 21 is a cross-sectional view showing a fourth step in the conventional method for manufacturing a conductive layer connection structure in a semiconductor device.

FIG. 22 is a cross-sectional view showing a fifth step of the conventional method for manufacturing a conductive layer connection structure of a semiconductor device.

FIG. 23 is a cross-sectional view showing a sixth step in the conventional method for manufacturing a conductive layer connection structure in a semiconductor device.

FIG. 24 is a cross-sectional view showing a state in which a titanium silicide film breaks a pn junction.

[Explanation of symbols]

 37 impurity region 43 interlayer insulating film 49 through hole 51 titanium silicide film 53 TiN film 55 Al film

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-5-62933 (JP, A) JP-A-63-172463 (JP, A) JP-A-3-224223 (JP, A) JP-A-1- 264258 (JP, A) JP-A-61-221376 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/28 H01L 21/768

Claims (1)

(57) [Claims] 1. A method for manufacturing a conductive layer connection structure of a semiconductor device for electrically connecting an upper conductive layer and a lower conductive layer, wherein the insulating layer formed on the lower conductive layer is selectively removed by etching. Forming a through hole reaching the surface of the lower conductive layer; and C using a gas containing titanium and a gas containing silicon.
The VD method, the at least on the bottom surface of the through _{hole, TiSi x (0 <x <} 2) to form a titanium <br /> emissions silicide layer having a molecular structure, form the titanium silicide layer
By forming the steps of reducing the natural oxide film the generated on the surface of the lower conductive layer constituting the bottom surface of the through hole, a TiN by CVD on the whole the through hole where the titanium silicide layer is formed Embedding, forming a connection conductive layer electrically connecting the upper conductive layer and the lower conductive layer, and forming the upper conductive layer electrically connected to the connection conductive layer on the insulating layer A method for manufacturing a conductive layer connection structure of a semiconductor device, comprising: