JP3095194U - Semiconductor device package structure - Google Patents
Semiconductor device package structureInfo
- Publication number
- JP3095194U JP3095194U JP2003000096U JP2003000096U JP3095194U JP 3095194 U JP3095194 U JP 3095194U JP 2003000096 U JP2003000096 U JP 2003000096U JP 2003000096 U JP2003000096 U JP 2003000096U JP 3095194 U JP3095194 U JP 3095194U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- package structure
- lead frame
- semiconductor device
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Abstract
(57)【要約】
【課題】 製造コストを削減して安価にできると共に、
厚みも薄くできる半導体素子のパッケージ構造を提供す
る。
【解決手段】 リードフレーム１０と、チップ２０と、
封止体３０とを有する半導体素子のパッケージ構造にお
いて、リードフレーム１０はプレート状であり、相対す
る中央の相対側及び外側に複数の接触端１１が設けら
れ、接触端１１同士の間に隙間１２が形成されると共
に、各接触端１１の底部にエッチングによって凹部１３
が形成され、前記チップ２０は両面テープ２２によって
リードフレーム１０における接触端１１の内面側に設置
されると共に、チップ２０におけるI／O接点がリード２
１によって接触端１１と接続され、封止体３０はチップ
２０を有するリードフレーム１０の一側に被覆されると
共に、隙間１２と凹部１３にも充填されることにより、
チップ２０、接触端１１及びリード２１がパッケージさ
れる構成とした。
(57) [Summary] [Problem] To reduce the manufacturing cost and reduce the cost,
Provided is a semiconductor device package structure that can be reduced in thickness. SOLUTION: A lead frame 10, a chip 20,
In the package structure of the semiconductor element having the sealing body 30, the lead frame 10 is plate-shaped, and a plurality of contact ends 11 are provided on the opposite side and outside of the center, and a gap 12 is provided between the contact ends 11. Are formed, and a recess 13 is formed in the bottom of each contact end 11 by etching.
The chip 20 is mounted on the inner surface of the contact end 11 of the lead frame 10 by the double-sided tape 22, and the I / O contact of the chip 20 is connected to the lead 2.
1, the sealing body 30 is coated on one side of the lead frame 10 having the chip 20 and is also filled in the gap 12 and the concave portion 13.
The chip 20, the contact end 11, and the lead 21 are configured to be packaged.
Description
【０００１】[0001]
本考案は、特に、製造コストを削減でき、且つ厚みを薄くできる半導体素子の パッケージ構造に関するものである。 The present invention is particularly applicable to a semiconductor device which can reduce the manufacturing cost and can reduce the thickness. It concerns the package structure.
【０００２】[0002]
図３に示すように、従来の半導体素子のパッケージ構造では、上方へ折り曲げ るように延伸する複数の接触端４１を有するリードフレーム４０に両面テープ５ ２によってチップ５０が設けられると共に、そのチップ５０におけるI／O接点が リード５１によって接触端４１と接続された後、封止体６０によって接触端４１ とチップ５０とがパッケージされる。 As shown in FIG. 3, the conventional semiconductor device package structure is bent upwards. The double-sided tape 5 on the lead frame 40 having a plurality of contact ends 41 extending so that The chip 50 is provided by 2 and the I / O contact in the chip 50 is After being connected to the contact end 41 by the lead 51, the contact end 41 is connected by the sealing body 60. And the chip 50 are packaged.
【０００３】 しかし、上記パッケージ構造によれば、チップ５０が完全に封止体６０の内部 にパッケージされ、チップ５０において発生する熱を放散できないことから、図 ４に示すような、二つのリードフレームを有するパッケージ構造が開発された。 この二つのリードフレームを有するパッケージ構造は、上方へ折り曲げるように 延伸する複数の接触端７１を有する第一リードフレーム７０に両面テープ８２に よってチップ８０が設けられると共に、そのチップ８０におけるI／O接点がリー ド８１によって接触端７１と接続され、該チップ８０の上面に接着剤によってチ ップパッド１０１である第二リードフレーム１００が設けられた後、封止体９０ によって接触端７１とチップ８０とがパッケージされるものである。[0003] However, according to the package structure described above, the chip 50 is completely inside the sealing body 60. Packaged in a chip and cannot dissipate the heat generated in the chip 50. A package structure with two leadframes has been developed, as shown in FIG. The package structure with these two lead frames is designed to bend upwards. A double-sided tape 82 on a first lead frame 70 having a plurality of extending contact ends 71 Therefore, the chip 80 is provided and the I / O contact on the chip 80 is releasable. It is connected to the contact end 71 by means of a cord 81 and is attached to the upper surface of the chip 80 by an adhesive. After the second lead frame 100 which is the pad pad 101 is provided, the sealing body 90 The contact end 71 and the chip 80 are packaged by.
【０００４】[0004]
しかしながら、上記の二種類のパッケージ構造は以下の欠点を有する。 １．従来のパッケージ構造によれば、加工設備によってリードフレームの接 触端を上方へ折り曲げる加工が必要となるので、パッケージ構造の製造コストが 高くなってしまう。 ２．又、リードフレームにおける接触端は上方へ折り曲げられるように延伸 すると共に、接触端の上方にチップが設けられた後、封止体によって接触端とチ ップとがパッケージされるので、パッケージの厚みが厚くなってしまう。 However, the above two types of package structures have the following drawbacks. 1. According to the conventional package structure, the lead frame is connected by the processing equipment. The manufacturing cost of the package structure is reduced because it is necessary to bend the contact tips upward. It gets expensive. 2. Also, the contact end of the lead frame is stretched so that it can be bent upward. In addition, after the chip is provided above the contact end, the encapsulant seals the contact end with the chip. Since the package is packaged, the package becomes thicker.
【０００５】 そこで、案出されたのが本考案であって、製造コストを削減できると共に、厚 みを薄くできる半導体素子のパッケージ構造を提供することを目的としている。[0005] Therefore, the present invention was devised, which can reduce the manufacturing cost and increase the thickness. It is an object of the present invention to provide a semiconductor element package structure that can be thinned.
【０００６】[0006]
本願の請求項１の考案は、リードフレーム１０と、チップ２０と、封止体３０ とを有する半導体素子のパッケージ構造であって、 リードフレーム１０はプレート状であり、中央の相対側及び外側に複数の接触 端１１が設けられ、接触端１１同士の間に隙間１２が形成されると共に、各接触 端１１の底部にエッチングによって凹部１３が形成され、チップ２０は両面テー プ２２によってリードフレーム１０における接触端１１の内面側に設置されると 共に、チップ２０におけるI／O接点がリード２１によって接触端１１と接続され 、封止体３０はチップ２０を有するリードフレーム１０の一側に被覆されると共 に、隙間１２と凹部１３にも充填されることにより、チップ２０、接触端１１及 びリード２１がパッケージされることを特徴とする。 本願の請求項２の考案は、請求項１に記載の半導体素子のパッケージ構造にお いて、チップ２０は封止体３０の内部に完全にパッケージされることを特徴とす る。 本願の請求項３の考案は、請求項１に記載の半導体素子のパッケージ構造にお いて、チップ２０の上面は封止体３０から外側へ露出すること特徴とする。 The invention of claim 1 of the present application provides a lead frame 10, a chip 20, and a sealing body 30. A package structure of a semiconductor device having The lead frame 10 has a plate shape, and has a plurality of contacts on the opposite side and the outside of the center. Ends 11 are provided, a gap 12 is formed between the contact ends 11, and each contact is made. A recess 13 is formed in the bottom of the end 11 by etching, so that the chip 20 has a double-sided tape. When the lead frame 10 is installed on the inner surface side of the contact end 11 of the lead frame 10, In both cases, the I / O contact on the chip 20 is connected to the contact end 11 by the lead 21. When the encapsulant 30 is coated on one side of the lead frame 10 having the chip 20, In addition, by filling the gap 12 and the recess 13 as well, the chip 20, the contact end 11 and the And the lead 21 are packaged. The invention of claim 2 of the present application is based on the package structure of a semiconductor device according to claim 1. The chip 20 is completely packaged inside the encapsulant 30. It The invention of claim 3 of the present application is based on the package structure of a semiconductor device according to claim 1. In addition, the upper surface of the chip 20 is exposed to the outside from the sealing body 30.
【０００７】[0007]
本考案は上述した課題を解決するものであり、上方へ折り曲げる接触端をなく したので、リードフレームとプレート状の接触端によってパッケージ構造の厚み を薄くすることができるだけでなく、接触端をリードフレームから上方へ折り曲 げる加工を必要としないため、製造コストも削減することができる。 The present invention solves the above-mentioned problems and eliminates the contact end that bends upward. Since the lead frame and the plate-shaped contact edge Not only can be thinned, but the contact end can be bent upward from the lead frame. The manufacturing cost can also be reduced since no peeling process is required.
【０００８】[0008]
以下、添付図面を参照して本考案の好適な実施の形態を詳細に説明する。勿論 、下記実施例は、本考案の好適な実施の形態を示したものにすぎず、本考案の技 術的範囲は、下記実施例そのものに何ら限定されるものではない。 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Of course The following examples merely show preferred embodiments of the present invention, and the technique of the present invention is described below. The surgical range is not limited to the examples below.
【０００９】 図１は本考案に係わる半導体素子のパッケージ構造の断面図であり、図２は本 考案に係わる半導体素子のパッケージ構造の他の実施例を示す断面図である。 図１及び図２に示すように、本考案に係わる半導体素子のパッケージ構造はリ ードフレーム１０と、チップ２０と、封止体３０とを有し、リードフレーム１０ は、プレート状であり、中央の相対側及び外側に複数の接触端１１が設けられ、 その接触端１１同士の間に隙間１２が形成されると共に、各接触端１１の底部に エッチングによって凹部１３が形成される。 なお、該凹部１３の高さはリードフレームの厚さの１／２以下であることが好 ましい。[0009] FIG. 1 is a sectional view of a package structure of a semiconductor device according to the present invention, and FIG. FIG. 6 is a cross-sectional view showing another embodiment of the package structure of the semiconductor device according to the invention. As shown in FIG. 1 and FIG. 2, the package structure of the semiconductor device according to the present invention is as follows. The lead frame 10, the chip 20, and the sealing body 30. Is a plate-like shape, and is provided with a plurality of contact ends 11 on the opposite side and outside of the center, A gap 12 is formed between the contact ends 11 and at the bottom of each contact end 11. The recess 13 is formed by etching. The height of the recess 13 is preferably 1/2 or less of the thickness of the lead frame. Good
【００１０】 前記チップ２０は、両面テープ２２によってリードフレーム１０における接触 端１１の内面（凹部１３の反対側）側に設置されると共に、チップ２０における I／O接点がリード２１によって接触端１１と接続される。[0010] The chip 20 contacts the lead frame 10 with a double-sided tape 22. It is installed on the inner surface of the end 11 (on the side opposite to the concave portion 13) and at the same time in the chip 20. The I / O contact is connected to the contact end 11 by the lead 21.
【００１１】 前記封止体３０はチップ２０を有するリードフレーム１０の一側に被覆される と共に、隙間１２と凹部１３にも充填されることにより、チップ２０、接触端１ １及びリード２１がパッケージされる。[0011] The sealing body 30 covers one side of the lead frame 10 having the chip 20. At the same time, the gap 12 and the recess 13 are filled so that the chip 20 and the contact end 1 are 1 and the lead 21 are packaged.
【００１２】 又、図１に示すように、本考案に係わる半導体素子のパッケージ構造によれば 、熱を放散させるために、チップ２０の上面を封止体３０から露出させる構造と してもよく、或いは図２の示すように、チップ２０を完全に封止体３０の内部に パッケージする構造にしてもよい。[0012] Further, as shown in FIG. 1, according to the package structure of the semiconductor device according to the present invention, , A structure in which the upper surface of the chip 20 is exposed from the sealing body 30 in order to dissipate heat Alternatively, as shown in FIG. 2, the chip 20 may be completely enclosed in the encapsulant 30. It may be packaged.
【００１３】[0013]
【考案の効果】 本考案は上記の構成を有するので、以下に示すような効果を達成できる。 本考案に係わる半導体素子のパッケージ構造は接触端をリードフレームか ら上方へ折り曲げる加工を施す必要がないため、製造コストを安価にすることが できる。 本考案に係わる半導体素子のパッケージ構造における接触端は、上方へ折 れ曲がる構成ではないので、リードフレームとプレート状のストレートになる接 触端によってパッケージの厚みを薄くすることができる。 本考案に係わる半導体素子のパッケージ構造における接触端は上方へ折れ 曲がる構造ではないから、より短い接触端によって信号の伝送を行うことができ るので、信号の伝送速度を向上させることができる。[Effect of device] Since the present invention has the above configuration, the following effects can be achieved. In the package structure of the semiconductor device according to the present invention, the contact end is a lead frame. Since it is not necessary to bend it upwards, the manufacturing cost can be reduced. it can. The contact end of the semiconductor device package structure according to the present invention is bent upward. Since it does not bend, the lead frame and plate-shaped straight contact The tip can reduce the thickness of the package. The contact end of the semiconductor device package structure according to the present invention is bent upward. Due to the non-bending structure, the shorter contact end allows signal transmission. Therefore, the signal transmission speed can be improved.
【図１】本考案に係わる半導体素子のパッケージ構造の
断面図である。FIG. 1 is a cross-sectional view of a semiconductor device package structure according to the present invention.
【図２】本考案に係わる半導体素子のパッケージ構造の
他の実施例を示す断面図である。FIG. 2 is a cross-sectional view showing another embodiment of a semiconductor device package structure according to the present invention.
【図３】従来の半導体素子のパッケージ構造の第一例を
示す断面図である。FIG. 3 is a cross-sectional view showing a first example of a conventional semiconductor device package structure.
【図４】従来の半導体素子のパッケージ構造の第二例を
示す断面図である。FIG. 4 is a sectional view showing a second example of a conventional semiconductor device package structure.
１０ リードフレーム １１ 接触端 １２ 隙間 １３ 凹部 ２０ チップ ２１ リード ２２ 両面テープ ３０ 封止体 ４０ リードフレーム ４１ 接触端 ５０ チップ ５１ リード ５２ 両面テープ ６０ 封止体 ７０ 第一リードフレーム ８０ チップ ８１ リード ８２ 両面テープ ９０ 封止体 １００ 第二リードフレーム １０１ チップパッド 10 lead frame 11 Contact end 12 gaps 13 recess 20 chips 21 lead 22 double-sided tape 30 sealed body 40 lead frame 41 contact end 50 chips 51 lead 52 double-sided tape 60 sealed body 70 First lead frame 80 chips 81 lead 82 double-sided tape 90 sealed body 100 second lead frame 101 chip pad
Claims (3)
封止体３０とを有する半導体素子のパッケージ構造であ
って、 リードフレーム１０はプレート状であり、中央の相対側
及び外側に複数の接触端１１が設けられ、接触端１１同
士の間に隙間１２が形成されると共に、各接触端１１の
底部にエッチングによって凹部１３が形成され、 チップ２０は、両面テープ２２によってリードフレーム
１０における接触端１１の内面側に設置されると共に、
チップ２０におけるI／O接点がリード２１によって接触
端１１と接続され、 封止体３０は、チップ２０を有するリードフレーム１０
の一側に被覆されると共に、隙間１２と凹部１３にも充
填されることにより、チップ２０、接触端１１及びリー
ド２１がパッケージされることを特徴とする半導体素子
のパッケージ構造。1. A lead frame 10, a chip 20, and
A package structure of a semiconductor device having a sealing body 30, wherein the lead frame 10 is plate-shaped, and a plurality of contact ends 11 are provided on the center relative side and outside, and a gap 12 is provided between the contact ends 11. And the recess 13 is formed in the bottom of each contact end 11 by etching, and the chip 20 is installed on the inner surface side of the contact end 11 in the lead frame 10 by the double-sided tape 22.
The I / O contact in the chip 20 is connected to the contact end 11 by the lead 21, and the sealing body 30 is the lead frame 10 having the chip 20.
A package structure for a semiconductor device, characterized in that the chip 20, the contact end 11 and the lead 21 are packaged by being coated on one side and also being filled in the gap 12 and the recess 13.
パッケージされることを特徴とする請求項１に記載の半
導体素子のパッケージ構造。2. The semiconductor device package structure as claimed in claim 1, wherein the chip 20 is completely packaged inside the encapsulant 30.
へ露出すること特徴とする請求項１に記載の半導体素子
のパッケージ構造。3. The package structure for a semiconductor device according to claim 1, wherein the upper surface of the chip 20 is exposed from the sealing body 30 to the outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003000096U JP3095194U (en) | 2003-01-10 | 2003-01-10 | Semiconductor device package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003000096U JP3095194U (en) | 2003-01-10 | 2003-01-10 | Semiconductor device package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP3095194U true JP3095194U (en) | 2003-07-25 |
Family
ID=43249134
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003000096U Expired - Lifetime JP3095194U (en) | 2003-01-10 | 2003-01-10 | Semiconductor device package structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3095194U (en) |
-
2003
- 2003-01-10 JP JP2003000096U patent/JP3095194U/en not_active Expired - Lifetime
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