JP2521944B2 - Integrated circuit package - Google Patents

Integrated circuit package

Info

Publication number
JP2521944B2
JP2521944B2 JP62044295A JP4429587A JP2521944B2 JP 2521944 B2 JP2521944 B2 JP 2521944B2 JP 62044295 A JP62044295 A JP 62044295A JP 4429587 A JP4429587 A JP 4429587A JP 2521944 B2 JP2521944 B2 JP 2521944B2
Authority
JP
Japan
Prior art keywords
case
integrated circuit
cap
side wall
height
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62044295A
Other languages
Japanese (ja)
Other versions
JPS63211652A (en
Inventor
政彦 本田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP62044295A priority Critical patent/JP2521944B2/en
Publication of JPS63211652A publication Critical patent/JPS63211652A/en
Application granted granted Critical
Publication of JP2521944B2 publication Critical patent/JP2521944B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積回路素子を搭載したパッケージケース裏
面にはんだ付け用の電極が引出されていて、プリント基
板の導体面に直接はんだ付けで実装されるリードレスチ
ップキャリア型の集積回路パッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention has electrodes for soldering drawn out from the back surface of a package case on which an integrated circuit element is mounted, and the electrodes are mounted directly on the conductor surface of a printed circuit board by soldering. The present invention relates to a leadless chip carrier type integrated circuit package.

〔従来の技術〕[Conventional technology]

第４図（ａ）は従来のこの種のパッケージに集積回路
素子（以下ICチップという）を搭載したキャップなしの
状態を示す平面図、同図（ｂ）は同図（ａ）のＡ−Ａ断
面図、同図（ｃ）は同図（ａ）のＢ−Ｂ断面図である。
第２図（ａ）において、パッケージケース11の中央凹所
にICチップ10が固着され、チップ10のパッド部とケース
11の内部リード２との間はボンディング線３で接続され
ている。ケース11の周辺には側壁４があり、この側壁４
の上面のキャップとの封止面６は、第４図（ｂ）に見ら
れるように、山なりに曲げられているボンディング線３
の最高到達点より高い位置にあり、キャップをかぶせて
封止する場合、キャップの下面が、ボンディング線３に
接触しないようになっている。FIG. 4 (a) is a plan view showing a state in which an integrated circuit element (hereinafter referred to as an IC chip) is mounted on a conventional package of this type without a cap, and FIG. 4 (b) is an AA line of FIG. 4 (a). A sectional view and the same figure (c) are BB sectional views of the same figure (a).
In FIG. 2A, the IC chip 10 is fixed in the central recess of the package case 11, and the pad portion of the chip 10 and the case
The internal lead 2 of 11 is connected by a bonding wire 3. There is a side wall 4 around the case 11, and the side wall 4
As shown in FIG. 4 (b), the sealing surface 6 with the cap on the upper surface of the bonding wire 3 is bent in a mountain shape.
Is higher than the highest reaching point of, and the lower surface of the cap does not come into contact with the bonding wire 3 when the cap is covered and sealed.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

近年、ICは高速動作で多機能化が要求される様になっ
ている為、チップも大きくなりつつある。それに対しパ
ッケージは高密度実装が要求される為、できるだけ小さ
くしなければならないという問題が生じてきている。し
かしながら、上述した従来のパッケージは、ボンディン
グ時の制約等からパッケージにとう載することができる
チップサイズはかなり制限を受ける。すなわち、第５図
はパッケージにICチップをとう載した後、アルミニウム
線を超音波ボンディングしている時の断面図を示したも
のであり、第５図において、パッケージケース11の側壁
４の高さｈに対し、キャップをかぶせてふたをし封止し
た時に、ボンディング装置のボンディングヘッド12によ
りボンディングされるボンディング線３に接触しない様
にボンディング線３の最高到達点の高さＨに対して、 ｈ＞Ｈ の関係がある。一方とう載できるチップサイズに大きな
影響をあたえるパッケージケース11の内部リード２のリ
ード長Ａは、ボンディング装置のボンディングヘッド12
によりボンディングされるボンディング線３が側壁４に
引かからないためには下記に示す以上の長さが必要とな
る。In recent years, ICs are required to have high-speed operation and multi-functionality, and therefore the size of chips is also increasing. On the other hand, since the package is required to be mounted at high density, there has been a problem that it must be made as small as possible. However, in the above-described conventional package, the chip size that can be mounted on the package is considerably limited due to restrictions at the time of bonding. That is, FIG. 5 shows a cross-sectional view when the aluminum wire is ultrasonically bonded after the IC chip is mounted on the package. In FIG. 5, the height of the side wall 4 of the package case 11 is shown. With respect to h, the height H of the highest reaching point of the bonding line 3 is set so that it does not come into contact with the bonding line 3 to be bonded by the bonding head 12 of the bonding device when the cap is covered and the lid is sealed. > H. On the other hand, the lead length A of the inner lead 2 of the package case 11, which has a great influence on the size of the chip that can be mounted, is determined by the bonding head 12 of the bonding apparatus.
In order to prevent the bonding line 3 bonded by the method from being drawn to the side wall 4, the length longer than that shown below is required.

例えば、θ＝30゜、ｈ＝300μｍの場合、Ａは520μｍ
以上必要である。しかし実際には、ボンディング時の位
置的バラツキ、リード部に使用されているAuパターンの
ズレ等を考慮してさらに余分の長さを必要とする。もち
論、この内部リード長Ａが短かければ、一定の大きさの
パッケージに対し、より大きなICチップを搭載できるわ
けであるから、成り可く短くできることが望まれる。 For example, when θ = 30 ° and h = 300μm, A is 520μm
The above is necessary. However, in reality, an extra length is required in consideration of positional variations during bonding, deviation of the Au pattern used in the lead portion, and the like. The theory is that if the internal lead length A is short, a larger IC chip can be mounted on a package of a certain size, so it is desirable that the length can be shortened as much as possible.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の集積回路パッケージは、集積回路素子をとう
載するリードレスチップキャリア型の集積回路パッケー
ジであって、パッケージケースの封止用キャップとの４
辺の縁辺にある封止面のうち、対向する一辺の２辺の縁
辺にある封止面が、ケースに搭載するICチップのパッド
部とケース周辺の内部リードとの間を接続するボンディ
ング線の高さ方向の最高到達点より低くし、他の一対の
対向する２辺の縁辺の封止面を高くしている。The integrated circuit package of the present invention is a leadless chip carrier type integrated circuit package on which an integrated circuit element is mounted, and is provided with a cap for sealing a package case.
Among the sealing surfaces at the edges of the sides, the sealing surfaces at the edges of the two opposite sides are the bonding wires connecting the pad part of the IC chip mounted in the case and the internal leads around the case. The height is set lower than the highest point in the height direction, and the sealing surfaces of the other two edges that face each other are raised.

〔実施例〕〔Example〕

つぎに本発明を実施例により説明する。 Next, the present invention will be described with reference to examples.

第１図（ａ）は本発明の一実施例のキャップなしの平
面図、同図（ｂ）は同図（ａ）のＡ−Ａ断面図、同図
（ｃ）は同図（ａ）のＢ−Ｂ断面図である。これらの図
において、パッケージケース１の中央凹所に集積回路チ
ップ10が固着され、チップ10の周辺のパッド部とこのパ
ッドに対応して設けられたケース１の周辺の台上に設け
られている内部リード２との間は山なりに曲げられたボ
ンディング線３により接続されている。長方形のケース
１の相対向する短辺の縁部には、ボンディング線３の最
高到達点の高さより高い側壁４が設けられている。一
方、ケース１の対向する長辺の縁部にはチップ10のパッ
ド面と同じ高さの内部リード形成台部そのままである。
したがって、内部リード形成台部の幅のうち、キャップ
との封止面６の幅を除いたチップ１の長辺側の内部リー
ド長Ａは、リード長を長くする側壁がないので、ボンデ
ィングに必要な最短の長さで事足りるため、短くなって
いる。よってその分だけ、従来のパッケージの横幅より
小さくできる。換言すれば、同じ大きさのパッケージな
ら、横幅の大きい集積回路チップが搭載できることにな
る。FIG. 1 (a) is a plan view of an embodiment of the present invention without a cap, FIG. 1 (b) is a sectional view taken along line AA of FIG. 1 (a), and FIG. 1 (c) is of FIG. It is a BB sectional view. In these figures, an integrated circuit chip 10 is fixed in a central recess of a package case 1, and is provided on a pad portion around the chip 10 and on a stand around the case 1 provided corresponding to the pad. The inner leads 2 are connected to each other by bonding wires 3 which are bent in a mountain shape. Side walls 4 that are higher than the height of the highest reaching point of the bonding line 3 are provided at the edges of the opposite short sides of the rectangular case 1. On the other hand, the inner lead forming base portions having the same height as the pad surface of the chip 10 are left as they are on the edges of the opposing long sides of the case 1.
Therefore, the internal lead length A on the long side of the chip 1 excluding the width of the sealing surface 6 with the cap, out of the width of the internal lead forming base portion, is not necessary for bonding because there is no side wall for increasing the lead length. It is shorter because the shortest length is enough. Therefore, the width can be made smaller than that of the conventional package. In other words, if the packages have the same size, an integrated circuit chip having a large width can be mounted.

第２図は第１図の実施例に適合するキャップ８の斜視
図である。キャップ８は、従来の平板形のキャップと異
なり、長辺側の縁部には、ケース１の側壁のない台部の
封止面と接触封止するために、短辺縁部の側壁４と同じ
高さの突出ふち8aが形成されている。FIG. 2 is a perspective view of the cap 8 adapted to the embodiment of FIG. The cap 8 is different from the conventional flat plate-shaped cap in that the edge portion on the long side is connected to the side surface 4 of the short side edge portion in order to contact and seal with the sealing surface of the base portion without the side wall of the case 1. A protruding edge 8a having the same height is formed.

第３図は本発明の第２の実施例のパッケージケースに
ICチップを搭載したのち、アルミのボンディング線３を
超音波ボンディングしている状態を示す部分断面図であ
る。図において、これを第１図の実施例と比べた場合、
ケース７の長辺側の縁部にはボンディング線３の最高到
達点の高さより充分低い側壁５を有することが異なって
いる。FIG. 3 shows the package case of the second embodiment of the present invention.
FIG. 6 is a partial cross-sectional view showing a state in which an aluminum bonding wire 3 is ultrasonically bonded after mounting an IC chip. In the figure, when comparing this with the embodiment of FIG.
The edge of the case 7 on the long side is different in that it has a side wall 5 which is sufficiently lower than the height of the highest reaching point of the bonding wire 3.

本例では、側壁５があっても、その高さが低いので、
ボンディング装置のボンディングヘッド12と側壁５とは
十分近付けるので、内部リード長Ａは従来のものに比べ
て短くでき、その分パッケージの横幅を小さくできる。In this example, since the height of the side wall 5 is low,
Since the bonding head 12 of the bonding apparatus and the side wall 5 are sufficiently close to each other, the internal lead length A can be shortened as compared with the conventional one, and the lateral width of the package can be reduced accordingly.

なお上例は、長方形のパッケージの四つ縁辺のうちの
対向する２つの長辺側の側壁を低くしているが、長辺側
は従来通り高くして、短辺側を低くすることもできるの
はいうまでもない。In the above example, the side walls on the two long sides facing each other out of the four edges of the rectangular package are made low, but the long sides can be made high and the short sides can be made low as before. Needless to say.

〔発明の効果〕〔The invention's effect〕

本発明によれば、ボンディング時の制約を受けないた
め、内部リード長を短かくすることができる。従がっ
て、従来パッケージに比べて大きなチップサイズまでと
う載できる効果がある。また、ボンディング線の最高到
達点より低い封止面が２方向の為、ICチップのとう載か
ら封止までの間に不慮の事故（裏返し等）があってもボ
ンディング線への影響は、従来品と同等である。According to the present invention, since there is no restriction during bonding, the internal lead length can be shortened. Therefore, there is an effect that a larger chip size can be mounted than the conventional package. In addition, since the sealing surface that is lower than the highest point of the bonding wire is in two directions, the effect on the bonding wire is not affected even if there is an unexpected accident (upside-down, etc.) between the mounting of the IC chip and the sealing. It is equivalent to the product.

【図面の簡単な説明】[Brief description of drawings]

第１図（ａ）は本発明の一実施例にICチップを搭載した
キャップなしの平面図、同図（ｂ）は同図（ａ）のＡ−
Ａ断面図、同図（ｃ）は同図（ａ）のＢ−Ｂ断面図、第
２図は第１図の実施例に付属するキャップの斜視図、第
３図は本発明の他の実施例にICチップを搭載後のボンデ
ィング線のボンディングを示す部分断面図、第４図
（ａ），（ｂ），（ｃ）は第１図の実施例に対応する従
来例の平面図、およびそのＡ−ＡならびにＢ−Ｂ断面
図、第５図は従来のボンディング線ボンディング時の内
部リード長と側壁の高さの関係を説明するための断面図
である。 1,7,11……パッケージケース、２……内部リード、３…
…ボンディング線、４……高い側壁、５……低い側壁、
６……封止面、８……キャップ、8a……突出ふち、10…
…ICチップ、12……ボンディングヘッド。FIG. 1 (a) is a plan view without an IC chip mounting IC chip according to an embodiment of the present invention, and FIG. 1 (b) is an A- line in FIG. 1 (a).
A sectional view, FIG. 3C is a sectional view taken along line BB of FIG. 2A, FIG. 2 is a perspective view of a cap attached to the embodiment of FIG. 1, and FIG. 3 is another embodiment of the present invention. An example is a partial cross-sectional view showing bonding of a bonding line after mounting an IC chip, FIGS. 4 (a), (b) and (c) are plan views of a conventional example corresponding to the embodiment of FIG. FIG. 5 is a cross-sectional view taken along the lines AA and BB, and FIG. 5 is a cross-sectional view for explaining the relationship between the internal lead length and the height of the side wall during the conventional bonding wire bonding. 1,7,11 …… Package case, 2… Internal lead, 3…
… Bonding line, 4 …… High side wall, 5 …… Low side wall,
6 ... Sealing surface, 8 ... Cap, 8a ... Projection edge, 10 ...
… IC chip, 12… bonding head.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】集積回路素子を搭載するケースと、このケ
ースにふたをし封止するキャップとを有するリードレス
チップキャリア型の集積回路パッケージにおいて、前記
ケースは前記搭載した集積回路素子のパッド部の高さと
ほぼ同じ高さである前記ケースの４辺上に設けられた周
縁部と、前記周縁部上に設けられた複数の内部リード
と、前記ケースの４辺のうちの１対の対向する２辺にあ
る前記周縁部上に設けられた前記キャップとの封止面が
前記搭載した集積回路素子のパッド部と前記内部リード
部とを接続するボンディング線の最高到達点の高さより
も高い側壁部とを有し、他の１対の対向する２辺にある
前記周縁部上には側壁部が設けられないか又は前記キャ
ップとの封止面が前記ボンディング線の最高到達点の高
さよりも低い側壁部が設けられることを特徴とする集積
回路パッケージ。1. A leadless chip carrier type integrated circuit package having a case for mounting an integrated circuit element and a cap for covering and sealing the case, wherein the case is a pad portion of the mounted integrated circuit element. And a plurality of inner leads provided on the four sides of the case, which are substantially the same height as the height of the case, and a plurality of inner leads provided on the four sides of the case. A side wall whose sealing surface with the cap provided on the peripheral edge on two sides is higher than the height of the highest reaching point of a bonding line connecting the pad section of the mounted integrated circuit element and the internal lead section. And a side wall portion is not provided on the peripheral edge portions on the other pair of two opposite sides, or the sealing surface with the cap is higher than the height of the highest reaching point of the bonding line. Lower side wall Integrated circuit package, characterized in that provided.
JP62044295A 1987-02-26 1987-02-26 Integrated circuit package Expired - Lifetime JP2521944B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62044295A JP2521944B2 (en) 1987-02-26 1987-02-26 Integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62044295A JP2521944B2 (en) 1987-02-26 1987-02-26 Integrated circuit package

Publications (2)

Publication Number Publication Date
JPS63211652A JPS63211652A (en) 1988-09-02
JP2521944B2 true JP2521944B2 (en) 1996-08-07

Family

ID=12687517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62044295A Expired - Lifetime JP2521944B2 (en) 1987-02-26 1987-02-26 Integrated circuit package

Country Status (1)

Country Link
JP (1) JP2521944B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11600687B2 (en) 2020-03-13 2023-03-07 Samsung Display Co., Ltd. Electronic device package and display device including the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2710174B2 (en) * 1991-06-27 1998-02-10 日本電気株式会社 One-dimensional image sensor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6247135U (en) * 1985-09-10 1987-03-23

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11600687B2 (en) 2020-03-13 2023-03-07 Samsung Display Co., Ltd. Electronic device package and display device including the same

Also Published As

Publication number Publication date
JPS63211652A (en) 1988-09-02

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