JP3069630B2 - Lead frame for semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame used for assembling a semiconductor device, and more particularly to a lead frame for a semiconductor device having a plurality of dimples on the back surface of a pad on which a semiconductor chip is to be mounted.

[0002]

2. Description of the Related Art As shown in FIG. 2, for example, a lead frame used for a semiconductor device such as an LSI is provided in a region surrounded by two side rails 1 and a partition frame 2 orthogonal to the side rails.
Pads 3, support bars 4 for supporting the pads, inner leads 5 for establishing electrical continuity with the semiconductor chip, tie bars 6 for interconnecting the inner leads 5, extending from the inner leads 5 and electrically connected to external electronic components. The outer lead 7 is connected to the outer lead 7.

By the way, as semiconductor devices become more multifunctional and larger in capacity, and as semiconductor chips become larger, the area of pads 3 in a lead frame used also tends to increase, while the package size decreases. As a result, the area occupied by the pads 3 with respect to the package size has increased.

[0004] The thermal expansion coefficient of, for example, 42 alloy used as a material of the lead frame and the thermal expansion coefficient of the molding resin are different by about 4 to 6 times. In addition, the adhesion between the pad 3 and the mold resin is deteriorated, which causes problems such as generation of package cracks and deterioration of moisture resistance.

Therefore, as disclosed in Japanese Patent Application Laid-Open No. 55-160449, a plurality of dimples 8
It is known to use a lead frame formed with a lead frame.

[0006]

When the dimple 8 is formed by pressing, the dimple punch 1 having a plurality of quadrangular pyramid-shaped projections as shown in FIG.
A progressive die apparatus in which 1 is arranged in one station is used.

As described above, when the dimple 8 is formed by the press working, as shown in FIG. Pushed up, dimple 8
Is formed around the periphery of the substrate.

[0008] Usually, in a lead frame maker, Ag or Pd
After precious metal plating, etc., and cutting into several pieces as shown in FIG. 5, the product is inspected, a plurality of sheets are stacked, put in a case, and shipped to a semiconductor manufacturer. As shown in FIG. 6, the protrusion 10 formed around the dimple 8 rubs against the surface of the pad 3 of the lead frame laminated thereunder, causing a problem that the noble metal plating surface is damaged.

Here, it is conceivable to crush the protruding portion 10 around the dimple 8 by means such as coin processing. Was greatly reduced, and the expected effect could not be obtained.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has been made for the purpose of preventing a noble metal plating from being damaged by a projection 10 generated around a dimple 8. And a concave portion 9 provided on the surface of the pad 3 and at a portion facing the dimple 8.

Preferably, a recess 9 having a larger opening area than the dimple 8 is provided on the surface of the pad 3 and at a portion facing the dimple 8, and more preferably, the opening area is larger than the dimple 8 and A recess 9 shallower than the dimple 8 is provided.

[0012]

The concave portion 9 is provided on the surface of the pad 3 facing the dimple 8 provided on the back surface of the pad 3, so that the projection 1 generated around the dimple 8 is provided along with the processing of applying the dimple 8.
0 can prevent the noble metal plating of the lead frame contacting the back surface in the laminated state from being damaged.

Further, since the concave portion 9 on the surface of the pad 3 has an opening larger than the dimple 8, even if the opening area is reduced due to the thickness of the noble metal plating applied to the pad 3, the concave portion 9 is formed around the dimple 8. The depth of the dimple 8 can be sufficiently obtained by setting the depth of the concave portion 9 provided on the surface of the pad 3 to be shallower than the depth of the dimple 8, as well as being able to accommodate the projected portion 10 sufficiently. be able to.

[0014]

An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an enlarged view of a part of a pad 3 in a state where a plurality of lead frames according to the present invention are stacked, and the pad 3 is supported by a support bar 4 as shown in FIG. Around the dimple 8 provided on the back surface of the pad 3, the excess
0 is formed, and the projection 10 does not enter the recess 9 provided in the pad 3 of the lead frame laminated thereunder, and does not come into contact with the noble metal plating.

Even if there is some deviation in the laminated state, the protrusion 10 generated around the dimple 8 moves only inside the recess 9 provided in the pad 3 of the lead frame under the dimple 8, and the pad 3 It does not adversely affect the noble metal plating on the surface.

The recess 9 is easily formed on the surface of the pad 3 by pressing a desired portion with a punch for forming the recess 9 provided at one station of the progressive die apparatus after or before the dimple processing. be able to.

The shape of the opening of the recess 9 provided on the surface of the pad 3 can be variously selected, such as a circle or a square, and can be changed by the shape of the punch in one station of the progressive die apparatus. It can respond accordingly.

Further, a concave portion 9 provided on the surface of the pad 3
In a region where the degree of noble metal plating does not matter, such as a region where a semiconductor chip is not mounted, it is not necessary to provide corresponding portions of the dimples 8. It may be in communication.

After the recess 9 is formed on the surface of the pad 3,
For example, Ag is applied to the tip of the pad 3 and the inner lead.
Noble metal plating such as Pd or Pd is applied.

[0020]

As described above in detail, according to the lead frame according to the present invention, the protrusions 10 generated around the dimples 8 in contact with the dimples 8 are brought into contact with the back surface in the laminated state. It is possible to prevent the noble metal plating from being damaged.

It is known that the pad 3 is warped by the work of applying the dimple 8 by the press working. However, according to the present invention, the processing distortion on the front side of the pad 3 is the same as that on the back side. As a result, the occurrence of warpage is canceled out, and a lead frame with good dimensional accuracy without deformation can be obtained.

Incidentally, the residual strain remaining inside the pad 3 can be easily removed by annealing.

[Brief description of the drawings]

FIG. 1 is a diagram showing a pad portion in a laminated state of a lead frame according to the present invention.

FIG. 2 is a schematic external view of a lead frame.

FIG. 3 is a conceptual diagram of a main part of a depressing punch.

FIG. 4 is a diagram showing a processing state of a dimple.

FIG. 5 is a view showing a laminated state of a lead frame cut in units of five pieces;

FIG. 6 is a diagram showing a pad portion in a laminated state of a lead frame according to the related art.

[Explanation of symbols]

 1 ... Side rail 2 ... Partition frame 3 ... Pad 4 ... Support bar 5 ... Inner lead 6 ... Tie bar 7 ... Outer lead 8 ... ··· Dimple 9 ··· Recess 10 ··· Projection 11 ··· Punch for dimple processing

Claims (2)

(57) [Claims] 1. A lead frame for a semiconductor device having a plurality of dimples on a back surface side of a pad on which a semiconductor chip is to be mounted, a portion having an opening area larger than that of the dimple on a surface of the pad and opposed to the dimple. A lead frame for a semiconductor device, wherein a large recess is provided. 2. A lead frame for a semiconductor device having a plurality of dimples on a back surface side of a pad on which a semiconductor chip is to be mounted, wherein an opening area is larger on the surface of the pad and on a portion facing the dimple than on the dimple. A lead frame for a semiconductor device, wherein a concave portion which is large and has a depth smaller than that of the dimple is provided.