JP3054388B2 - Manufacturing method of wiring board - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a wiring board having a wiring pattern formed via a resin insulating layer and a via penetrating the resin insulating layer and conducting between a plurality of wiring patterns.

[0002]

2. Description of the Related Art In general, a multilayer wiring board 40 having a resin insulating layer interposed between wiring patterns has a lower wiring pattern 4 formed on the upper surface of a core substrate 41 as shown in FIG.
A photosensitive resin paste having a predetermined thickness is applied to the upper part of the substrate 2 and dried to form a resin insulating layer 44. As shown in FIG. 6B, the via hole 46 for exposing the upper surface of the lower wiring pattern 42 is formed on the resin insulating layer 44 by exposure and development or laser processing, and then the upper surface of the resin insulating layer 44 is formed. The upper wiring pattern 52 is formed by electroless copper plating, electrolytic copper plating, exposure and development. At the same time, a via 48 that conducts between the upper and lower wiring patterns 52 and 42 is formed in the via hole 46.

[0003]

The via hole 4
In the developing step for forming 6, the resin melted out by the developing solution may accumulate at the bottom of the via hole 46 during the formation. The melted resin is formed in the via hole 46.
When it accumulates at the bottom of the via hole 46, it becomes difficult to supply a new developing solution to the bottom of the via hole 46 during the formation, and development in the depth direction from the bottom is hindered. As a result, as shown in FIG. 6C, the resin piece 45 may remain between the bottom surface of the via 48 and the upper surface of the lower wiring pattern 42 due to insufficient opening of the via hole 46. In order to remove the resin piece 45, a method of lengthening the development time may be considered. However, in a state where the melted resin is accumulated at the bottom of the via hole 46, development in the depth direction is still difficult. There was also a problem that the diameter became too large.

In addition, when the developing time is prolonged, the resin insulating layer 44 around the via hole 46 swells, causing a problem that the shape of the via hole 46 varies. Further, when the development is performed simultaneously on the upper and lower surfaces in a state where the multilayer wiring board 40 having the resin insulation layers 44 on both surfaces is horizontally held, the lower surface side has less resin pool and is easy to develop in the depth direction. On the upper surface side, a resin pool is easily generated, and it is difficult to develop in the depth direction. Therefore, a difference occurs in the developing speed between the upper and lower resin insulating layers 44. Due to this difference in the developing speed, the upper via hole 46 tends to be insufficiently perforated as shown in FIG. 6C, and the lower via hole 46 tends to undergo excessive development as shown in FIG. 6D. . If the over-development forms a substantially cylindrical via hole 46 with a lower portion extending obliquely, the above-mentioned poor adhesion with copper plating may occur, and a narrow portion 50 may be formed at the bottom of the via 48. If these resin pieces 45 remain or there is a narrow portion 50, conduction between the upper and lower wiring patterns 52 and 42 due to the via 48 becomes unstable, which may cause a case where a three-dimensional circuit is not formed.

In order to prevent such a conduction failure, the upper surface of the resin insulating layer 44 in which the via hole 46 is formed is polished and removed to a thickness of about 5 μm to flatten the surface. The surface of the resin insulating layer 44 was roughened by contact with an etching solution such as potassium acid. After that, the surface of the roughened resin insulating layer 44 is coated with Sn / P
d. Adsorb a plating catalyst core (not shown) of a colloid type, and form the upper wiring pattern 52 by electroless copper plating or the like.
Had formed. In this method, since the upper surface of the resin insulating layer 44 is planarized by polishing,
Although the above-mentioned defective shape of the via 48 due to a variation in the development when forming No. 6 can be slightly reduced, it is still insufficient and lacks stability.

[0006] Further, the resin piece 4
5 can be considered, but the upper surface of the resin insulating layer 44 is excessively roughened at the time of etching to remove the resin piece 45, and the upper wiring pattern 52 and the resin insulating layer 44 formed on the upper surface are roughened. There is also a problem that the adhesion strength of the resin decreases. Further, a method of strongly irradiating the laser so that the resin piece 45 does not remain in the via hole 46 can be considered.
If the laser irradiation becomes excessive, there is a problem that the narrow portion 50 shown in FIG. 6D is formed in the via 48 carelessly.

The present invention solves the above-mentioned problems in the prior art, eliminates resin residue and defective shape at the bottom of the via, makes the shape of the via accurate, and ensures conduction between the upper and lower wiring patterns. It is another object of the present invention to provide a method of manufacturing a multilayer wiring board which enables formation of relatively fine via holes and vias.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a cleaning and post-exposure developing step for forming an accurate via hole in a resin insulating layer formed on a lower wiring pattern. This was achieved with the idea of once interrupting the drying process and performing the development again. That is, the method of manufacturing a wiring board according to the present invention includes the steps of forming a resin insulating layer on a lower wiring pattern, exposing and developing the resin insulating layer, and forming a via hole in the resin insulating layer. A method of manufacturing a wiring board which is to form a multilayer wiring pattern including: a step of dividing the developing step into a plurality of steps, and washing and drying the resin insulating layer during the developing step. It is characterized by.

According to this method, by cleaning the wiring board immediately before the drying step, even if the diameter of the via hole is as small as 100 μm or less, the peeled resin piece in the via hole being formed can be removed. Since it can be removed to the outside, development in the depth direction inside the via hole is not hindered. Therefore, a fine via hole having a diameter of, for example, 90 μm or less can be formed. In addition, the immediately preceding development is stopped or the development speed is reduced by the drying process in the middle, so that the variation in the diameter of the via hole can be suppressed as much as possible, and the diameter of the via can be easily controlled. After that, for example, the next development step can be performed by changing the posture of the substrate and the like, so that there is no resin residue or shape defect, and a required via hole can be reliably formed in both shape and size. Therefore, the via formed in the via hole can reliably conduct the lower wiring pattern and the upper wiring pattern formed in succession.

It is also possible to adopt a method in which the developing step divided into three or more times includes a washing and drying step for each developing step other than the first developing step. This can also reduce the variation in the diameter of the via hole,
The formation of required via holes is further ensured. In addition, the drying step may be performed by heating the resin insulating layer to about 80 to 150 ° C. for several minutes.
A manufacturing method in which heating and holding are performed for several tens of minutes can be used. According to this, the development in the via hole can be reliably stopped, and the inside of the via hole can be formed in a required shape in the next development step. The method also includes a method of manufacturing a wiring board having a multilayer wiring pattern, including a step of forming an upper wiring pattern on the resin insulating layer after forming the via hole and forming a via in the via hole. According to this,
A multilayer wiring board having a three-dimensional circuit in which upper and lower wiring patterns are reliably conducted through vias can be provided.

Further, the present invention also includes a method of manufacturing a wiring board in which the exposure and development are performed in a negative mold. Generally, in the case of a positive resist, the exposed resin portion flows down during development. This is a method of developing using a time difference in which a portion irradiated with light (photosensitive portion) melts faster than a portion not exposed to light (unexposed portion) by irradiating light. Therefore, if the developing time is lengthened, the unexposed portion also melts out and the resist becomes thin. On the other hand, the negative type has an advantage that the unexposed portion is melted, and the exposed portion is photo-cured, so that the resist is less dissolved (film loss). According to this, it is possible to accurately and easily form a via hole having a required shape in an unexposed portion of the resin insulating layer masked from the exposure.

The plurality of developing steps are performed while the wiring board is held substantially horizontally, and after the first or intermediate development in the plurality of developing steps, the wiring board held substantially horizontally is held. The method also includes a method of manufacturing a wiring board in which the next development is performed after the upper and lower surfaces are turned upside down. According to this, it is possible to eliminate the shape defect and the variation in the shape of the via hole caused by the difference in the developing speed between the upper and lower surfaces, so that the via holes having the required shape are formed uniformly and simultaneously on the resin insulating layers on the upper and lower surfaces of the wiring board. It becomes possible.

Further, the present invention also includes a method of manufacturing a wiring board in which the developing step is performed in a state where the lower wiring pattern and the resin insulating layer are positioned on the lower surface side of the wiring board held substantially horizontally. According to this, a desired number of via holes having accurate shapes and dimensions can be simultaneously formed in the same resin insulating layer. When via holes are formed in the resin insulating layers on both the upper and lower surfaces of the wiring board by this method, each developing step is performed by sequentially turning the upper and lower surfaces of the substrate upside down with a washing and drying step therebetween.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of each step showing an outline of a method for manufacturing a multilayer wiring board. As shown in FIG. 1A, a lower wiring pattern made of copper having a thickness of 28 μm is formed on both upper and lower surfaces of a core substrate 1 made of a glass-BT (bismaleimide / triazine) resin composite material having a thickness of 0.8 mm. 4 are formed. The core substrate 1 has a diameter of 300
A large number of through holes 2 having a thickness of μm are formed by drilling, and a conductive portion 3 having a cylindrical shape and a peripheral wall thickness of 15 μm is formed in each through hole 2. This conducting part 3
Plays a role of conducting the lower wiring patterns 4 on both surfaces of the core substrate 1. The hollow portion of each conductive portion 3 is filled with a thermosetting resin (not shown).

The core substrate 1 and the lower wiring pattern 4
Is formed as follows. First, copper foil having a thickness of about 12 μm is attached to both upper and lower surfaces of the core substrate 1. Drilling is performed on the obtained copper-clad laminate to form a large number of through holes 2. Next, Pd catalyst nuclei are adhered to both the upper and lower surfaces of the laminate and the inside of the through-hole 2, and then electroless plating and electrolytic plating are performed so that the thickness of copper is about 28 μm on each surface. Further, a resist is applied on the copper, exposed and developed, and then unnecessary portions are removed by etching, whereby the lower wiring pattern 4 is formed.

Next, as shown in FIG. 1B, a photosensitive epoxy resin insulating layer 6 having a thickness of 55 μm is formed on the entire surface above the lower wiring pattern 4. Exposure and development are performed on a predetermined position of the resin insulating layer 6 to form a substantially conical via hole 7. At the bottom of this via hole 7,
The upper surface of the lower wiring pattern 4 is exposed. Depending on the developing method for forming the via hole 7, the above-described resin residue may occur, or the via hole 7 itself may have a defective shape. Therefore, the surface of the resin insulating layer 6 including the via holes 7 is subjected to a plurality of times of development, and washing and drying during the development. This will be described later in detail with reference to FIG.

Next, the entire surface of the resin insulating layer 6 including the via holes 7 is roughened with a potassium permanganate solution (45 g / liter), and then the upper surface of the lower wiring pattern 4 is etched with a sulfuric acid-hydrogen peroxide etching solution ( Okuno Pharmaceutical; trade name OPC-40
0) Soft etching was performed. These are all applied to improve the adhesion to the electroless plating layer described below.
Next, it was immersed in a Sn-Pd colloid solution (manufactured by Okuno Pharmaceutical Co., Ltd .; trade name OPC-80) to adsorb the Pd catalyst nucleus. 2), an electroless plating layer 8 is formed on the entire surface of the resin insulating layer 6 including the via holes 7.

Further, when a photosensitive resin of a water-soluble dry film is stuck on the entire upper surface of the electroless plating layer 8 and exposed and developed, as shown in FIG. A plating resist (resin pattern) 10 is formed. Next, when the electroless plating layer 8 on which the plating resist 10 is formed is subjected to sulfuric acid-based electrolytic copper plating, as shown in FIG. 1E, the electroless plating layer not covered with the plating resist 10 is formed. 8 having an electroplating layer 1 having a thickness of 15 μm
4 are formed. At the same time, the electroplating layer 1 having the same thickness is also formed on the base 9 of the electroless plating layer 8 in the via hole 7.
4 are formed.

Thereafter, the plating resist 10 is replaced with NaO
HB aqueous solution, and peeled off. Further, a persulfate-based etching solution (manufactured by Ebara Uzilite; trade name PB-2)
28), the exposed electroless plating layer 8 is removed,
An upper wiring pattern 15 and a via 12 comprising an electrolytic plating layer 14 and an electroless plating layer 8 thereunder are formed.
This state is shown in FIG. Thus, a three-dimensional circuit in which the upper and lower wiring patterns 15 and 4 are conducted by the via 12 is formed. Further, as shown in FIG. 1 (G), a resin insulating layer 16 having a thickness of 55 μm is formed on the entire upper surface of the resin insulating layer 6 and the upper wiring pattern 15, and exposure and multiple development and the After cleaning and drying, via holes 17 are formed at predetermined positions of the resin insulating layer 16.

An electroless plating layer (not shown) and a plating resist (not shown) are formed on the upper surface of the resin insulating layer 16 as described above.
When a sulfuric acid-based electrolytic copper plating is applied thereto, an uppermost wiring pattern 20 having a thickness of 15 μm is formed on the upper surface of the electroless plating layer without the plating resist, and at the same time, a via 18 similar to the above is formed in the via hole 17. Is done. Thus, as shown in FIG. 1 (G), a three-dimensional circuit including the lower, upper, and uppermost wiring patterns 4, 15, and 20, and the vias 12 and 18 connecting these wiring patterns is formed. Then, as shown in FIG. 1H, the resin insulating layer 16 and the uppermost wiring pattern 2 are formed.
A solder resist 22 made of a photosensitive epoxy-modified resin is formed on the entire upper surface of the wiring pattern 0, and is exposed and developed to form an opening 24 on the upper surface of the uppermost wiring pattern 20. The Ni (Ni-P) plating layer and the A (Ni-P) plating layer are formed on the upper surface of the uppermost wiring pattern 20 exposed in the opening 24 by electroless plating.
A pad 26 made of a u-plated layer was formed, and a multilayer wiring board 28 was obtained. The uppermost wiring pattern 20 is a relative name in the vertical direction. If the upper wiring pattern 15 is a lower wiring pattern, the upper wiring pattern 20 is the upper wiring pattern.

Next, a characteristic manufacturing process of the present invention will be described with reference to FIG. FIG. 2A is a schematic enlarged sectional view showing a state immediately before forming the via hole 7 in FIG. 1B, and is formed above the lower wiring pattern 4 as shown in FIG. The so-called negative-type exposure and development are performed on the resin insulating layer 6 thus formed, and a via hole 7 is formed at a predetermined position. However, if the separated powder and the granular resin pieces 6a that have been melted out by the developer in the via hole 7 during the developing process, the development on the resin insulating layer 6 located at a deeper position is hindered. .

Then, by spraying a cleaning liquid made of, for example, an organic solvent into the via hole 7, the powder and granular resin pieces 6a are discharged as shown in FIG. 2C, and only the bottom resin portion 6b is discharged. Remains. By performing the washing between the two development steps, even in the case of the via hole 7 having a diameter of 100 μm or less, the resin piece 6a that has melted during the development step and accumulated at the bottom of the via hole 7 can be surely removed. Can be removed. Therefore, it is possible to prevent the resin residue at the bottom of the via hole 7 and the diameter of the via hole 7 from becoming excessive, so that the via holes 7 and the vias 12 that are relatively fine can be formed.

Next, the resin insulating layer 6 having the via holes 7 is dried. Specifically, at about 100 ° C, 10
Heat and hold for about a minute. Then, the resin insulating layer 6
The development action on the surface including the inside of the via hole 7 is stopped. By performing the drying after the washing, the swelling of the resin insulating layer 6 is eliminated, and the developing speed can be significantly reduced. Thereby, the diameter of the via hole 7 is easily controlled, and the accuracy of the manufactured wiring board 28 is stabilized.

When the via hole 7 having the dried surface is developed again, development in the depth direction is not hindered, and as shown in FIG. 6b is also removed, and a deep via hole 7 is formed while controlling the expansion of the diameter of the via hole 7. Pertaining 2
By performing the developing step and the washing and drying steps in between, the residual resin in the via hole 7 is eliminated, and the via hole 7 having a required shape and fine dimensions can be obtained. Finally, the steps shown in FIGS. 1C to 1E are applied to the resin insulating layer 6 including the via holes 7, as shown in FIG. A pattern 15 is formed.

In the developing step, as shown in FIG.
In a state where the substrate K including the core substrate 1, the lower wiring pattern 4, the resin insulating layer 6, and the like is held horizontally, the developing solution is continuously sprayed onto both upper and lower surfaces in a shower form from above and below. In this case, a liquid pool S of the developing solution is generated on the upper surface of the substrate K, and it is difficult for the liquid pressure to be applied to the resin insulating layer 6 on the upper surface, so that the via hole 7 is hardly formed. On the other hand, since a new developing solution is always sprayed on the lower surface of the substrate K,
Tend to be easily formed. In the case where two development steps are performed after the exposure as described above, the upper and lower surfaces of the substrate K are turned upside down after the first development step, and the second development step is performed. Variation in the shape of the via hole can be suppressed.

In this case, after the first development, the substrate K is taken out and the above-mentioned washing is performed to wash away the resin pieces in the via holes.
Thereafter, the drying and upside down are performed to perform the second development. In addition, 1
Compared to the method performed in one development step, in the case of performing the two development steps by inverting the upper and lower surfaces according to the present invention, the shower pressure of the developing solution is only about half of the conventional method. Further, it was confirmed that the aspect ratio (depth / inner diameter) of the via hole to be formed can be increased as compared with the conventional method.

Here, examples according to the present invention will be described together with comparative examples. The via hole 7 formed by the method shown in FIG. 2 and the via hole of the comparative example formed by conventional one-time development were formed by changing the exposure shielding dimension by a mask for forming a via hole by a negative type. For a plurality of vias, the variation (distribution) for each shielding dimension was measured, which was the same as their depth. The results are shown in the graph of FIG. From FIG. 4, it can be seen that each via hole 7 of the example can be formed deeper than the comparative example even with the same exposure shielding dimension, and the variation thereof remains within a small range. from this result,
The method of the present invention has been demonstrated to be able to form a via hole having a relatively accurate shape and size.

Further, the multilayer wiring board 28 of the embodiment manufactured by the method of the present invention in which development is performed twice with washing and drying interposed therebetween,
As in the conventional case, 160 wiring boards of the comparative example each having the same structure as the multilayer wiring board 28 obtained by only one development were prepared. Each of these wiring boards has a diameter of 100 μm.
Are formed in total. A probe (not shown) is brought into contact with the pad 26 of each wiring board 28, and a constant current is supplied from an external power source to each of the boards 100.
The circuit was passed through a three-dimensional circuit including zero vias 12 and 18, and the resistance of the circuit was measured to determine whether or not the circuit was conductive. Then, assuming that one of the 1000 vias 12 and 18 had a defective wiring board having a non-conducting portion, the failure rate for the entire circuit was calculated for each example. Further, after the above measurement, each wiring board 28 of the example and the comparative example was disassembled,
Average and deviation of diameters at the top of all vias 12, 18
(1Σ) was measured. Table 1 shows the results.

[0029]

[Table 1]

From Table 1, it is found that the wiring board of the embodiment has a defect rate of 5
% Or less, whereas the comparative example had a failure rate of 50% or more. Also, it was found that the diameters of the vias 12 and 18 were thicker on average in the example than in the comparative example, and there was less variation. These results also support the effect of the method of the present invention, and it has become clear that it can contribute to the improvement in productivity of the multilayer wiring board.

The present invention is not limited to the embodiments and examples described above. For example, FIG.
As shown in FIG. 1B, a lower wiring pattern 4 is formed on both surfaces of the core substrate 1 as in FIG. 1, a resin insulating layer 6 is formed thereon and exposed, and then the plurality of developing steps are performed. A via hole 7 is formed by performing a washing and drying process on the substrate. Next, as shown in FIG. 5C, the entire surface of the resin insulating layer 6 is subjected to electroless copper plating or the like to form a copper conductor layer 30 having a thickness of several tens of μm.
As shown in (D), an insulating layer 32 made of a photosensitive resin is formed on the upper surface of the copper body layer 30. Next, the resin insulating layer 32 is exposed and developed, and as shown in FIG.
A predetermined resin pattern 33 is used. Then, by dipping the resin pattern 33 and the conductor layer 30 in an etching solution, the upper wiring pattern 34 and the via 36 are formed at positions protected by the resin pattern 33 as shown in FIG. Is done. By the same method as described above, a multi-layer wiring board 38 similar to the wiring board 28 can be formed by forming a resin insulating layer, an uppermost wiring pattern, and the like (not shown).

The present invention also includes performing at least three development steps and a washing and drying step between them according to the thickness of the resin insulating layer and the like. Exposure and development are excellent in that the negative type, in which the unexposed portions are removed by development, is less in leaching of the resin in the exposed portions of the resin insulating layer and the amount of film loss is small, but a so-called positive type. Can also be used. Further, the core substrate 1 of the multilayer wiring boards 28 and 38 is made of a composite material of BT resin and glass fiber cloth.
In addition to (glass-BT resin material), composite materials such as glass-epoxy material, glass-PPE material, and paper-epoxy material, or resins such as epoxy, BT resin, polyimide, and PPE may be used.

Further, the core substrate 1 is not limited to the above-mentioned resin or the like.
It may be made of ceramic. When such a rigid ceramic core substrate 1 is used, the same number of resin insulating layers 6 and 16 and lower, upper and uppermost wiring patterns 4 and 1 are provided on both surfaces thereof.
The number of layers may be different from each other without forming the layers 5 and 20, or the resin insulating layer 6 and the like and the lower and upper wiring patterns 4 and 15 may be formed only on one surface of the core substrate 1. In the latter case, the through hole 2 and the like can be omitted. Furthermore, the core substrate 1 is not an essential element. For example, a resin multilayer wiring substrate may be manufactured by forming the lower wiring pattern 4 on the upper surface of an existing resin insulating layer and sequentially performing the above-described steps. . Alternatively, it is also possible to form a lower wiring pattern 4 on the upper surface of an existing ceramic layer or ceramic multilayer wiring board and sequentially perform the above-described steps to manufacture a composite multilayer wiring board containing ceramic and resin.

Although the pad 26 is used as a terminal for conduction with the outside of the multilayer wiring board 28, a solder bump, a lead, a pin, or the like may be used instead.
Although the wiring pattern 4 and the like were formed of copper, Ni and its alloys (Ni-P, Ni-B, Ni-Cu-P), Co and its alloys (Co-P, Co-B, Co-Ni- P), Sn and its alloys (Sn-Pb, Sn-Pb-Pd), Au, Ag, P
Any of d, Pt, Rh, Ru, and the like and alloys thereof can also be used.

[0035]

According to the manufacturing method of the present invention described above, since the via hole formed in the resin insulating layer is exposed to light and formed by a plurality of developing steps and a washing and drying step therebetween, an accurate shape is obtained. A relatively fine via hole having the following can be surely formed. Therefore, the via formed in the via hole becomes more accurate later, so that conduction between the upper and lower wiring patterns can be ensured, and a wiring board having a three-dimensional circuit as designed can be provided. Further, according to the fourth and fifth aspects of the present invention, it is possible to form a via hole having an accurate shape and dimensions and a via in accordance with the same even when the wiring pattern is provided on only one side of the wiring board, as well as on both sides. .

[Brief description of the drawings]

1A to 1H are partial cross-sectional views schematically showing a manufacturing process of a wiring board using the present invention.

2 (A) to 2 (D) are partial cross-sectional views showing steps of manufacturing a via hole according to the present invention, and FIG. 2 (E) is a partial cross-sectional view showing an obtained via.

FIG. 3 is a schematic view showing a developing step of the present invention.

FIG. 4 is a graph showing a relationship between an exposure shielding dimension and a via depth in Examples and Comparative Examples.

5A to 5F are partial cross-sectional views showing different manufacturing steps of a wiring board using the present invention.

FIGS. 6A and 6B are partial cross-sectional views showing a conventional manufacturing process, and FIGS. 6C and 6D are partial cross-sectional views showing obtained vias.

[Explanation of symbols]

 4 Lower wiring pattern 6, 16 Resin insulation layer 7, 17 Via hole 12, 18, 36 Via 15, 34 Upper wiring pattern 28, 38 … Wiring board

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-310858 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H05K 3/46

Claims (5)

(57) [Claims] 1. A multilayer wiring pattern comprising: a step of forming a resin insulating layer on a lower wiring pattern; and a step of exposing and developing the resin insulating layer to form a via hole in the resin insulating layer. A method of manufacturing a wiring board which is to be formed, comprising: a step of dividing the developing step into a plurality of steps, and washing and drying the resin insulating layer during the developing step. Production method. 2. After forming the via hole according to claim 1,
Forming an upper wiring pattern on the resin insulating layer and forming a via in the via hole. 3. The method according to claim 1, wherein the exposure and the development are performed by a negative type. 4. The plurality of development steps are performed while the wiring board is held substantially horizontally, and after the first or intermediate development in the plurality of development steps, the wiring board is held substantially horizontally. 4. The method for manufacturing a wiring board according to claim 1, wherein the next development is performed after the upper and lower surfaces are turned upside down. 5. The developing step according to claim 1, wherein the lower wiring pattern and the resin insulating layer are positioned on a lower surface side of the wiring substrate which is held substantially horizontally. A method for manufacturing a wiring board according to any one of the above.