JP3004329B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3004329B2 JP3004329B2 JP2224027A JP22402790A JP3004329B2 JP 3004329 B2 JP3004329 B2 JP 3004329B2 JP 2224027 A JP2224027 A JP 2224027A JP 22402790 A JP22402790 A JP 22402790A JP 3004329 B2 JP3004329 B2 JP 3004329B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- etching
- emission intensity
- hole
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔概要〕 多層配線工程において,2層目以降の配線を行う際に層
間絶縁膜にスルーホールを形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for forming through holes in an interlayer insulating film when performing wiring of a second layer or later in a multilayer wiring process.
スルーホール形成の際に側壁に付着する堆積物を減少
させて,多層配線の層間接続の信頼性を向上することを
目的とし, レジスト膜をマスクにした反応性イオンエッチング法
により,多層配線における下層配線上の層間絶縁膜にス
ルーホールを形成するに際し,下層配線の露出状態をプ
ラズマ発光強度でモニタしながら,最初は所定の高周波
電力を印加してエッチングし,エッチングの進行にとも
ない該発光強度が低下し始めて下層配線が完全に露出す
る以前に該高周波電力を低下させてエッチングするよう
に構成する。The purpose of this method is to reduce the deposits adhering to the sidewalls during the formation of through-holes and improve the reliability of the interlayer connection of the multilayer wiring. When a through hole is formed in the interlayer insulating film on the wiring, the exposed state of the lower wiring is monitored by plasma emission intensity while etching is first performed by applying a predetermined high frequency power, and as the etching progresses, the emission intensity decreases. The high-frequency power is reduced and etching is performed before the lower wiring starts to be completely reduced and the lower wiring is completely exposed.
本発明は半導体装置の製造方法に係り,特に多層配線
工程において,2層目以降の配線を行う際に層間絶縁膜に
スルーホールを形成する方法に関する。The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a through hole in an interlayer insulating film when performing wiring of a second layer or later in a multilayer wiring process.
半導体装置の微細化にともない,スルーホールも微細
化され,スルーホールのアスペクト比(深さ/開口径)
が大きくなり,配線層間のコンタクトの確実性が要求さ
れる。With the miniaturization of semiconductor devices, through-holes have also been miniaturized, and the aspect ratio of the through-holes (depth / opening diameter)
And the reliability of the contact between the wiring layers is required.
本発明はこの要求に対応した微細スルーホールの形成
に利用できる。The present invention can be used for forming a fine through hole that meets this requirement.
ウエハプロセスの配線工程において,多層配線の2層
目以降の配線を行う際,パターニングされたレジスト膜
をエッチングマスクとした反応性イオンエッチング(RI
E)を用いて,下地の層間絶縁膜にスルーホールを形成
して下層配線の表面を露出している。In the wiring process of the wafer process, when performing wiring of the second and subsequent layers of the multilayer wiring, reactive ion etching (RI) using the patterned resist film as an etching mask
Using E), a through hole is formed in the underlying interlayer insulating film to expose the surface of the lower wiring.
第4図は従来例を説明する断面図である。 FIG. 4 is a sectional view for explaining a conventional example.
図において,1は基板,2は下層配線,3は層間絶縁膜でり
ん珪酸ガラス(PSG)膜,4はレジスト膜,5はスルーホー
ル,6はRIEの際に付着した堆積物である。In the figure, 1 is a substrate, 2 is a lower wiring, 3 is an interlayer insulating film, a phosphosilicate glass (PSG) film, 4 is a resist film, 5 is a through hole, and 6 is a deposit attached during RIE.
RIEの際,スルーホール5の側壁に堆積物6が付着
し,微細なスルーホールの開口径を狭め,層間接続不良
の原因となっていた。At the time of RIE, the deposit 6 adheres to the side wall of the through-hole 5 and narrows the opening diameter of the fine through-hole, thereby causing poor interlayer connection.
そのため,後処理〔TMK(アルカリ性で,コリンの水
溶液)や硝酸等のウエット処理〕により除去していた。For this reason, they have been removed by post-treatment (wet treatment with TMK (an alkaline solution of choline) or nitric acid).
上記の後処理(ウエット処理)により堆積物を除去し
ようとするが,完全に除去することは困難である。Deposits are intended to be removed by the above-mentioned post-treatment (wet treatment), but it is difficult to remove them completely.
特に,下層配線材料が,下より順にTi/TiN/純Al,また
はTi/TiN/Al−Si−Cu合金のようにバリアメタル(ここ
ではTi/TiNがこれに相当し,Al配線と下地物質との間の
反応阻止用のメタル層)を用いた場合は,上記のウエッ
ト処理の際に電池効果によりエッチング速度が極度に速
くなることが知られており,下層配線は数秒で局部的に
穴が開いてしまう。In particular, the lower layer wiring material is a barrier metal such as Ti / TiN / pure Al or Ti / TiN / Al-Si-Cu alloy in order from the bottom (here, Ti / TiN corresponds to Al It is known that the etching rate becomes extremely high due to the battery effect during the above-mentioned wet treatment when the metal layer for preventing the reaction between the substrate and the lower wiring is formed within a few seconds. Will open.
配線材料にこのようなバリアメタル使用時には,スル
ーホールの側壁堆積物を減少させないと,下層配線に穴
を開けないで堆積物を除去することは極めて困難とな
る。When such a barrier metal is used as the wiring material, it is extremely difficult to remove the deposit without making a hole in the lower wiring unless the deposit on the side wall of the through hole is reduced.
本発明はスルーホール形成の際に側壁に付着する堆積
物を減少させて,多層配線の層間接続の信頼性を向上す
ることを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to reduce deposits adhering to a side wall when a through hole is formed and to improve reliability of interlayer connection of a multilayer wiring.
上記課題の解決は,レジスト膜をマスクにした反応性
イオンエッチング法により,多層配線における下層配線
上の層間絶縁膜にスルーホールを形成するに際し,下層
配線の露出状態をプラズマ発光強度でモニタしながら,
最初は所定の高周波電力を印加してエッチングし,エッ
チングの進行にともない該発光強度が低下し始めて下層
配線が完全に露出する以前に該高周波電力を低下させて
エッチングする半導体装置の製造方法により達成され
る。The above problem is solved by monitoring the exposed state of the lower wiring by plasma emission intensity when forming a through hole in the interlayer insulating film on the lower wiring in the multilayer wiring by the reactive ion etching method using the resist film as a mask. ,
At first, etching is performed by applying a predetermined high-frequency power, and the emission intensity starts to decrease with the progress of etching, and the high-frequency power is reduced before the lower wiring is completely exposed. Is done.
本発明者は堆積物の発生は,下層配線金属が露出した
後もなお高パワーのRIEを続けると,イオンにより下層
配線金属がスパッタされて,その変質物が側壁に付着す
るものと考えて,下記のような確認実験を行った。The present inventor believes that if the high-power RIE is continued even after the lower-layer wiring metal is exposed, the lower-layer wiring metal is sputtered by ions, and the altered substance adheres to the side wall. The following confirmation experiments were performed.
第1図は本発明の原理を説明する断面図である。 FIG. 1 is a sectional view for explaining the principle of the present invention.
図示のように下層配線金属が露出しない状態では堆積
物が付着しないことを確認した。As shown in the figure, it was confirmed that no deposits adhered when the lower wiring metal was not exposed.
さらにRIEを続けて下地の配線金属が露出すると,RIE
の高周波(RF)パワーが大きいほど,堆積物の付着する
量が多くなった。When RIE is continued and the underlying wiring metal is exposed, RIE
As the radio frequency (RF) power of the steel increased, the amount of sediment deposited increased.
従って,RFパワーを減らすとよいが,エッチングレー
トが減少し,著しくスループットを落としてしまうこと
になる。Therefore, although it is good to reduce the RF power, the etching rate is reduced and the throughput is remarkably reduced.
そこで,本発明は下層配線金属が露出しない間は高パ
ワーでエッチングし,露出してからは低パワーでソフト
にエッチングし,堆積物の発生を防止するようにしたも
のである。Therefore, the present invention is designed to perform high-power etching while the lower-layer wiring metal is not exposed, and to softly etch with low power after the lower-layer metal is exposed, thereby preventing generation of deposits.
ここで,パワーの切り換えは,RIE室内のプラズマ発光
強度をモニタし,RIEの進行にともないこの強度が減少し
始めた時に行えばよい。Here, the power may be switched by monitoring the plasma emission intensity in the RIE chamber and when the intensity starts to decrease as the RIE progresses.
第2図はプラズマ発光強度の時間経過にともなう変化
を示す図である。FIG. 2 is a diagram showing a change in plasma emission intensity with time.
図において,縦軸はプラズマ発光強度,横軸は経過時
間を示し,時刻Aでエッチングを開始し,時刻BとCの
間でパワーを切り換え,時刻Dでエッチングを終了す
る。In the figure, the vertical axis indicates the plasma emission intensity, and the horizontal axis indicates the elapsed time. Etching is started at time A, the power is switched between times B and C, and the etching is ended at time D.
第3図(a),(b)は本発明の一実施例を説明する
断面図である。FIGS. 3A and 3B are cross-sectional views illustrating an embodiment of the present invention.
図において,1は基板,2は下層配線でアルミニウム(A
l)配線,3は層間絶縁膜でPSG膜,4はレジスト膜,5はスル
ーホールである。In the figure, 1 is the substrate, 2 is the lower wiring, aluminum (A
l) Wiring, 3 is an interlayer insulating film, PSG film, 4 is a resist film, 5 is a through hole.
第3図(a)において,基板1上に下層配線として厚
さ5000ÅのAl配線2を形成し,その上を覆って基板上全
面に層間絶縁膜として厚さ5000ÅのPSG膜3を形成す
る。In FIG. 3 (a), a 5000 .ANG. Thick Al wiring 2 is formed on a substrate 1 as a lower wiring, and a 5000 .ANG. Thick PSG film 3 is formed over the entire surface of the substrate over the substrate.
つぎに,基板上全面に厚さ1μmのレジスト膜を被着
し,通常のリソグラフィ技術を用いてスルーホール形成
予定領域に開口径1.6μmの開口を形成する。Next, a resist film having a thickness of 1 μm is coated on the entire surface of the substrate, and an opening having a diameter of 1.6 μm is formed in a region where a through hole is to be formed by using a usual lithography technique.
第3図(b)において,レジスト膜4をエッチングマ
スクにして,RIEによりPSG膜3をエッチングして,スル
ーホール5を形成する。In FIG. 3B, the PSG film 3 is etched by RIE using the resist film 4 as an etching mask to form a through hole 5.
PSGのRIE条件は, Al配線が露出するまでの高パワーRIE: エッチングガスとしてCF4,またはCHF3を用い,これを
0.4Torrに減圧した雰囲気中で,周波数13.56MHzの電力
を基板当たり600W印加する。The RIE conditions for PSG are as follows: High power RIE until the Al wiring is exposed: CF 4 or CHF 3 is used as the etching gas.
In a reduced-pressure atmosphere of 0.4 Torr, a power of 13.56 MHz is applied at a power of 600 W per substrate.
最後の低パワーRIE: エッチングガスとしてCF4,またはCHF3を用い,これを
0.4Torrに減圧した雰囲気中で,周波数13.56MHzの電力
を基板当たり150W印加する。Last low power RIE: CF 4 or CHF 3 is used as etching gas
In an atmosphere reduced to 0.4 Torr, a power of 13.56 MHz is applied at 150 W per substrate.
この際のパワーの切り換えは第2図の説明に記載した
要領による。The switching of the power at this time is in accordance with the procedure described in the description of FIG.
つぎに,切り換え時期の判定に必要なプラズマ発光強
度測定の一例を第5図に示す。Next, FIG. 5 shows an example of the plasma emission intensity measurement required for determining the switching timing.
第5図はプラズマ発光強度測定例を示すブロック図で
ある。FIG. 5 is a block diagram showing an example of plasma emission intensity measurement.
図において,1はエッチング室で石英チャンバ,2,3は電
極,4はrf電源,5は出力側が2分枝された光ファイバ,6は
波長656nmの光を通すフィルタ,6Rは波長604nmの光を通
すフィルタ,7はフォトダイオード,8は増幅器,9はA/Dコ
ンバータである。In the figure, 1 is a quartz chamber, which is an etching chamber, 2 and 3 are electrodes, 4 is an rf power supply, 5 is an optical fiber whose output side is bifurcated, 6 is a filter that passes light of 656 nm wavelength, and 6R is light of 604 nm wavelength. 7 is a photodiode, 8 is an amplifier, and 9 is an A / D converter.
ここで,波長604nmの光はエッチングの進行にともな
う影響を受けにくい光で,これを基準としてプラズマ発
光強度は,波長656nmの光と波長604nmの基準光の比で表
される。Here, the light having a wavelength of 604 nm is light that is hardly affected by the progress of etching, and the plasma emission intensity is represented by the ratio of the light having a wavelength of 656 nm to the reference light having a wavelength of 604 nm.
ウエハ内の多数のスルーホールについて検鏡の結果,
スルーホール内の堆積物はほとんど見られなかった。As a result of microscopy for many through holes in the wafer,
Almost no deposits were found in the through holes.
その後,簡単なウエット処理により,堆積物は完全に
除去することができた。After that, the deposits could be completely removed by a simple wet treatment.
実施例では下層配線金属としてAlについて説明した
が,前記のようにバリアメタルの上にAlを含む金属を用
いた配線金属に対して本発明は一層効果的である。In the embodiment, Al was described as the lower wiring metal. However, the present invention is more effective for a wiring metal using a metal containing Al on the barrier metal as described above.
なお,本発明のように高パワーから低パワーに切り換
える2段エッチングは数々の公知例があり,例えば, (1) 特公昭55−033060, (2) 特公昭56−158874, (3) 特公昭60−142519, (4) 特公平02−003920 等がある。There are many known examples of two-step etching for switching from high power to low power as in the present invention. For example, (1) Japanese Patent Publication No. 55-033060, (2) Japanese Patent Publication No. 56-158874, and (3) Japanese Patent Publication No. 60-142519, (4) Japanese Patent Publication No. 02-003920.
以上の公知例は同じ2段エッチングでもそれぞれの特
徴を有しており,また,いずれも本発明と目的,構成が
異なっている。The above known examples have their respective characteristics even in the same two-stage etching, and all have different objects and configurations from the present invention.
以上説明したように本発明によれば,スルーホール形
成の際に側壁に付着する堆積物を減少させて,これの除
去処理を容易にし,多層配線の層間接続の信頼性を向上
することができた。As described above, according to the present invention, it is possible to reduce deposits adhering to side walls when forming through holes, to facilitate the removal of the deposits, and to improve the reliability of interlayer connection of multilayer wiring. Was.
第1図は本発明の原理を説明する断面図, 第2図はプラズマ発光強度の時間経過にともなう変化を
示す図, 第3図(a),(b)は本発明の一実施例を説明する断
面図, 第4図は従来例を説明する断面図, 第5図はプラズマ発光強度測定例を示すブロック図であ
る。 図において, 1は基板, 2は下層配線でAl配線, 3は層間絶縁膜でPSG膜, 4はレジスト膜, 5はスルーホール, 6はRIEの際に付着した堆積物 である。FIG. 1 is a cross-sectional view for explaining the principle of the present invention, FIG. 2 is a view showing a change in plasma emission intensity with time, and FIGS. 3 (a) and (b) are views for explaining an embodiment of the present invention. FIG. 4 is a sectional view for explaining a conventional example, and FIG. 5 is a block diagram showing an example of plasma emission intensity measurement. In the figure, 1 is a substrate, 2 is an Al wiring as a lower layer wiring, 3 is a PSG film as an interlayer insulating film, 4 is a resist film, 5 is a through hole, and 6 is a deposit attached during RIE.
フロントページの続き (72)発明者 太田 竜介 福島県会津若松市門田町工業団地4番地 株式会社富士通東北エレクトロニクス 内 (56)参考文献 特開 平2−210825(JP,A) 特開 昭58−175831(JP,A) 特開 昭56−158427(JP,A) 特開 昭62−272538(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/302 Continuation of front page (72) Inventor Ryusuke Ota 4 Kadotacho Industrial Park, Aizuwakamatsu-shi, Fukushima Prefecture Fujitsu Tohoku Electronics Co., Ltd. (JP, A) JP-A-56-158427 (JP, A) JP-A-62-272538 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/302
Claims (1)
ッチング法により,多層配線における下層配線上の層間
絶縁膜にスルーホールを形成するに際し, 下層配線の露出状態をプラズマ発光強度でモニタしなが
ら,最初は所定の高周波電力を印加してエッチングし,
エッチングの進行にともない該発光強度が低下し始めて
下層配線が完全に露出する以前に該高周波電力を低下さ
せてエッチングすることを特徴とする半導体装置の製造
方法。When a through hole is formed in an interlayer insulating film on a lower wiring in a multilayer wiring by a reactive ion etching method using a resist film as a mask, the exposed state of the lower wiring is monitored by plasma emission intensity. At first, etching is performed by applying a predetermined high frequency power.
A method of manufacturing a semiconductor device, characterized in that the high-frequency power is reduced and etching is performed before the lower-level wiring is completely exposed as the emission intensity starts to decrease with progress of etching.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2224027A JP3004329B2 (en) | 1990-08-23 | 1990-08-23 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2224027A JP3004329B2 (en) | 1990-08-23 | 1990-08-23 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04105318A JPH04105318A (en) | 1992-04-07 |
JP3004329B2 true JP3004329B2 (en) | 2000-01-31 |
Family
ID=16807443
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2224027A Expired - Lifetime JP3004329B2 (en) | 1990-08-23 | 1990-08-23 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3004329B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102004043233B4 (en) | 2003-09-10 | 2014-02-13 | Denso Corporation | A method of manufacturing a movable portion of a semiconductor device |
-
1990
- 1990-08-23 JP JP2224027A patent/JP3004329B2/en not_active Expired - Lifetime
Also Published As
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JPH04105318A (en) | 1992-04-07 |
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