JP3004329B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for forming through holes in an interlayer insulating film when performing wiring of a second layer or later in a multilayer wiring process.

The purpose of this method is to reduce the deposits adhering to the sidewalls during the formation of through-holes and improve the reliability of the interlayer connection of the multilayer wiring. When a through hole is formed in the interlayer insulating film on the wiring, the exposed state of the lower wiring is monitored by plasma emission intensity while etching is first performed by applying a predetermined high frequency power, and as the etching progresses, the emission intensity decreases. The high-frequency power is reduced and etching is performed before the lower wiring starts to be completely reduced and the lower wiring is completely exposed.

[Industrial applications]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a through hole in an interlayer insulating film when performing wiring of a second layer or later in a multilayer wiring process.

With the miniaturization of semiconductor devices, through-holes have also been miniaturized, and the aspect ratio of the through-holes (depth / opening diameter)
And the reliability of the contact between the wiring layers is required.

The present invention can be used for forming a fine through hole that meets this requirement.

[Conventional technology]

In the wiring process of the wafer process, when performing wiring of the second and subsequent layers of the multilayer wiring, reactive ion etching (RI) using the patterned resist film as an etching mask
Using E), a through hole is formed in the underlying interlayer insulating film to expose the surface of the lower wiring.

 FIG. 4 is a sectional view for explaining a conventional example.

In the figure, 1 is a substrate, 2 is a lower wiring, 3 is an interlayer insulating film, a phosphosilicate glass (PSG) film, 4 is a resist film, 5 is a through hole, and 6 is a deposit attached during RIE.

At the time of RIE, the deposit 6 adheres to the side wall of the through-hole 5 and narrows the opening diameter of the fine through-hole, thereby causing poor interlayer connection.

For this reason, they have been removed by post-treatment (wet treatment with TMK (an alkaline solution of choline) or nitric acid).

[Problems to be solved by the invention]

Deposits are intended to be removed by the above-mentioned post-treatment (wet treatment), but it is difficult to remove them completely.

In particular, the lower layer wiring material is a barrier metal such as Ti / TiN / pure Al or Ti / TiN / Al-Si-Cu alloy in order from the bottom (here, Ti / TiN corresponds to Al It is known that the etching rate becomes extremely high due to the battery effect during the above-mentioned wet treatment when the metal layer for preventing the reaction between the substrate and the lower wiring is formed within a few seconds. Will open.

When such a barrier metal is used as the wiring material, it is extremely difficult to remove the deposit without making a hole in the lower wiring unless the deposit on the side wall of the through hole is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce deposits adhering to a side wall when a through hole is formed and to improve reliability of interlayer connection of a multilayer wiring.

[Means for solving the problem]

The above problem is solved by monitoring the exposed state of the lower wiring by plasma emission intensity when forming a through hole in the interlayer insulating film on the lower wiring in the multilayer wiring by the reactive ion etching method using the resist film as a mask. ,
At first, etching is performed by applying a predetermined high-frequency power, and the emission intensity starts to decrease with the progress of etching, and the high-frequency power is reduced before the lower wiring is completely exposed. Is done.

[Action]

The present inventor believes that if the high-power RIE is continued even after the lower-layer wiring metal is exposed, the lower-layer wiring metal is sputtered by ions, and the altered substance adheres to the side wall. The following confirmation experiments were performed.

 FIG. 1 is a sectional view for explaining the principle of the present invention.

As shown in the figure, it was confirmed that no deposits adhered when the lower wiring metal was not exposed.

When RIE is continued and the underlying wiring metal is exposed, RIE
As the radio frequency (RF) power of the steel increased, the amount of sediment deposited increased.

Therefore, although it is good to reduce the RF power, the etching rate is reduced and the throughput is remarkably reduced.

Therefore, the present invention is designed to perform high-power etching while the lower-layer wiring metal is not exposed, and to softly etch with low power after the lower-layer metal is exposed, thereby preventing generation of deposits.

Here, the power may be switched by monitoring the plasma emission intensity in the RIE chamber and when the intensity starts to decrease as the RIE progresses.

FIG. 2 is a diagram showing a change in plasma emission intensity with time.

In the figure, the vertical axis indicates the plasma emission intensity, and the horizontal axis indicates the elapsed time. Etching is started at time A, the power is switched between times B and C, and the etching is ended at time D.

〔Example〕

FIGS. 3A and 3B are cross-sectional views illustrating an embodiment of the present invention.

In the figure, 1 is the substrate, 2 is the lower wiring, aluminum (A
l) Wiring, 3 is an interlayer insulating film, PSG film, 4 is a resist film, 5 is a through hole.

In FIG. 3 (a), a 5000 .ANG. Thick Al wiring 2 is formed on a substrate 1 as a lower wiring, and a 5000 .ANG. Thick PSG film 3 is formed over the entire surface of the substrate over the substrate.

Next, a resist film having a thickness of 1 μm is coated on the entire surface of the substrate, and an opening having a diameter of 1.6 μm is formed in a region where a through hole is to be formed by using a usual lithography technique.

In FIG. 3B, the PSG film 3 is etched by RIE using the resist film 4 as an etching mask to form a through hole 5.

The RIE conditions for PSG are as follows: High power RIE until the Al wiring is exposed: CF ₄ or CHF ₃ is used as the etching gas.
In a reduced-pressure atmosphere of 0.4 Torr, a power of 13.56 MHz is applied at a power of 600 W per substrate.

Last low power RIE: CF ₄ or CHF ₃ is used as etching gas
In an atmosphere reduced to 0.4 Torr, a power of 13.56 MHz is applied at 150 W per substrate.

The switching of the power at this time is in accordance with the procedure described in the description of FIG.

Next, FIG. 5 shows an example of the plasma emission intensity measurement required for determining the switching timing.

FIG. 5 is a block diagram showing an example of plasma emission intensity measurement.

In the figure, 1 is a quartz chamber, which is an etching chamber, 2 and 3 are electrodes, 4 is an rf power supply, 5 is an optical fiber whose output side is bifurcated, 6 is a filter that passes light of 656 nm wavelength, and 6R is light of 604 nm wavelength. 7 is a photodiode, 8 is an amplifier, and 9 is an A / D converter.

Here, the light having a wavelength of 604 nm is light that is hardly affected by the progress of etching, and the plasma emission intensity is represented by the ratio of the light having a wavelength of 656 nm to the reference light having a wavelength of 604 nm.

As a result of microscopy for many through holes in the wafer,
Almost no deposits were found in the through holes.

After that, the deposits could be completely removed by a simple wet treatment.

In the embodiment, Al was described as the lower wiring metal. However, the present invention is more effective for a wiring metal using a metal containing Al on the barrier metal as described above.

There are many known examples of two-step etching for switching from high power to low power as in the present invention. For example, (1) Japanese Patent Publication No. 55-033060, (2) Japanese Patent Publication No. 56-158874, and (3) Japanese Patent Publication No. 60-142519, (4) Japanese Patent Publication No. 02-003920.

The above known examples have their respective characteristics even in the same two-stage etching, and all have different objects and configurations from the present invention.

〔The invention's effect〕

As described above, according to the present invention, it is possible to reduce deposits adhering to side walls when forming through holes, to facilitate the removal of the deposits, and to improve the reliability of interlayer connection of multilayer wiring. Was.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the principle of the present invention, FIG. 2 is a view showing a change in plasma emission intensity with time, and FIGS. 3 (a) and (b) are views for explaining an embodiment of the present invention. FIG. 4 is a sectional view for explaining a conventional example, and FIG. 5 is a block diagram showing an example of plasma emission intensity measurement. In the figure, 1 is a substrate, 2 is an Al wiring as a lower layer wiring, 3 is a PSG film as an interlayer insulating film, 4 is a resist film, 5 is a through hole, and 6 is a deposit attached during RIE.

Continuation of front page (72) Inventor Ryusuke Ota 4 Kadotacho Industrial Park, Aizuwakamatsu-shi, Fukushima Prefecture Fujitsu Tohoku Electronics Co., Ltd. (JP, A) JP-A-56-158427 (JP, A) JP-A-62-272538 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/302

Claims (1)

(57) [Claims] When a through hole is formed in an interlayer insulating film on a lower wiring in a multilayer wiring by a reactive ion etching method using a resist film as a mask, the exposed state of the lower wiring is monitored by plasma emission intensity. At first, etching is performed by applying a predetermined high frequency power.
A method of manufacturing a semiconductor device, characterized in that the high-frequency power is reduced and etching is performed before the lower-level wiring is completely exposed as the emission intensity starts to decrease with progress of etching.