KR0181959B1 - Forming method of via hole in semiconductor device - Google Patents

Forming method of via hole in semiconductor device Download PDF

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KR0181959B1
KR0181959B1 KR1019910008734A KR910008734A KR0181959B1 KR 0181959 B1 KR0181959 B1 KR 0181959B1 KR 1019910008734 A KR1019910008734 A KR 1019910008734A KR 910008734 A KR910008734 A KR 910008734A KR 0181959 B1 KR0181959 B1 KR 0181959B1
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South Korea
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forming
capping metal
insulating film
via hole
wiring layer
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KR1019910008734A
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KR920022475A (en
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김호기
이태복
서진수
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김광호
삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure

Abstract

비아홀의 크기가 확대되지 않고 폴리머가 발생되지 않으면서 티타늄이 함유된 힐록 방지용 캡핑메탈을 제거할 수 있는 반도체 장치의 비아홀을 형성하기 위하여, 티타늄이 함유된 물질을 힐록 방지용 캡핑메탈(3)로 사용하는 반도체 장치의 비아홀 형성방법에 있어서, 반도체기판 위에 제1배선층(2)을 형성시키는 공정과, 상기 제1배선층에 힐록 방지용 캡핑메탈(3)을 형성시키는 공정과, 상기 제1배선층(2)과 그 위에 형성시킬 제2배선층간을 절연시키기 위해 절연막(4)을 형성시키는 공정과, 상기 절연막(4)상에 비아홀을 형성시킬 예정 부위에 포토레지스터 패턴(5)을 형성시키는 공정과, 상기 캡핑메탈층(3)이 드러나기 직전까지 상기 절연막(5)을 건식 식각하는 공정과, 고주파 건식 식각기로 플라즈마 상태에서 상기 캡핑메탈층(3)을 식각하는 공정으로 반도체 장치의 비아홀 형성방법에 관한 것이다.Titanium-containing materials are used as anti-lock capping metals (3) to form via-holes in semiconductor devices that can remove the anti-hilllock capping metal containing titanium without increasing the size of via holes and generating polymers. A method of forming a via hole in a semiconductor device, comprising: forming a first wiring layer (2) on a semiconductor substrate, forming a capping metal (3) for preventing heel lock in the first wiring layer, and forming the first wiring layer (2). Forming an insulating film 4 to insulate the second wiring layer to be formed thereon, and forming a photoresist pattern 5 at a predetermined site where a via hole is to be formed on the insulating film 4; Dry etching the insulating film 5 until the capping metal layer 3 is exposed, and etching the capping metal layer 3 in a plasma state using a high frequency dry etching machine. A method for forming a via hole in a conductor device.

Description

반도체 장치의 비아홀 형성 방법Via hole formation method of semiconductor device

제1a,b도는 종래의 비아홀 형성 공정 중 폴리머 형성을 보인 반도체 장치의 단면도.1A and 1B are cross-sectional views of a semiconductor device showing polymer formation during a conventional via hole forming process.

제2도는 이 발명의 비아홀 형성 과정을 보인 공정도이다.2 is a process chart showing a via hole forming process of the present invention.

이 발명은 반도체 장치에 관한 것으로, 특히 티타늄(Ti)을 포함하는 힐록(Hillock) 방지용 캡핑 메탈(Capping metal)을 사용하는 경우엔 폴리머(Polymer)가 발생되지 않는 반도체 장치의 비아홀(Via Hole) 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device. In particular, in the case of using a hillock preventing capping metal including titanium, a via hole is formed in a semiconductor device in which a polymer is not generated. It is about a method.

종래에는 다층 금속 공정에서 전극 배선을 위한 재료에는 보통 실리콘을 함유한 알루미늄 합금을 사용하고 있으며, 최근에는 실리콘 이외에 동이나 티타늄을 함유한 알루미늄 합금도 사용되고 있다. 그런데 반도체 기판 상에 알루미늄 박막을 형성하면 반도체 기판의 선팽창 계수와 알루미늄 박막의 선팽창 계수의 차이 때문에 알루미늄 박막의 표면 위에 2㎛ 정도의 높이를 갖는 언덕 모양의 힐록이 형성된다. 이 힐록의 발생은 접합 저항의 이상 증대를 야기시키며, 또한 접합 깊이를 얕아지게 하여 알루미늄 스파크에 한 접합 파괴를 유발시킨다. 상기와 같은 힐록이 형성되는 것을 방지하기 위해서 제1알루미늄 배선의 상측에 질화 티타늄 및 티타늄 실리사이드 등과 같은 고용점 금속의 엷은 막으로 된 힐록 방지용 캡핑 메탈을 삽입하는 방법이 채용되기 시작하였다.Conventionally, aluminum alloys containing silicon are usually used as materials for electrode wiring in multilayer metal processes, and recently, aluminum alloys containing copper or titanium are used in addition to silicon. However, when the aluminum thin film is formed on the semiconductor substrate, a hill-shaped hillock having a height of about 2 μm is formed on the surface of the aluminum thin film because of the difference between the linear expansion coefficient of the semiconductor substrate and the linear expansion coefficient of the aluminum thin film. The occurrence of this hillock causes an abnormal increase in the bonding resistance, and also causes the bonding depth to be shallow, which causes the bonding failure to the aluminum spark. In order to prevent the formation of such a hillock, a method of inserting a hillock preventing capping metal made of a thin film of a solid solution metal, such as titanium nitride and titanium silicide, has been adopted on the upper side of the first aluminum wiring.

이를 제1도를 참조하여 설명한다. 먼저 반도체 기판(1) 상에 제1알루미늄막을 적층시킨다음, 티타늄을 포함한 힐록 방지용 캡핑 메탈막을 스퍼터링법에 의하여 형성하고, 상기 캡핑 메탈막 및 제1 알루미늄막을 패터닝시켜 캡핑 메탈층(3) 및 제1 배선층(2)을 형성시킨다. 이어 화학 기상 증착법(CVD)으로 층간 절연막(4)을 형성시킨다음, 상기 층간 절연막(4) 및 캡핑 메탈층(3)을 통해 비아홀(7)을 형성시킨다. 이후의 공정은 제1도에 도시되지 않는 공정으로, 상기 층간 절연막(4)상의 전면에 걸쳐 제2 알루미늄막을 증착 시키고 패터닝시켜 비아홀(7)을 통해 제1 배선층(2)에 연결되는 제2 배선층을 상기 층간 절연막(4) 위에 형성시킴으로써 반도체 장치를 제조하였다.This will be described with reference to FIG. First, a first aluminum film is laminated on the semiconductor substrate 1, and then a capping metal film for preventing a heel lock including titanium is formed by a sputtering method, and the capping metal film and the first aluminum film are patterned to form a capping metal layer 3 and a first film. 1 The wiring layer 2 is formed. Subsequently, an interlayer insulating film 4 is formed by chemical vapor deposition (CVD), and a via hole 7 is formed through the interlayer insulating film 4 and the capping metal layer 3. The subsequent process is a process not shown in FIG. 1, in which a second aluminum film is deposited and patterned over the entire surface of the interlayer insulating film 4 and connected to the first wiring layer 2 through the via hole 7. Was formed on the interlayer insulating film 4 to manufacture a semiconductor device.

그런데 상기에서 언급한 제1도와 같은 반도체 제조 공정에서 티타늄이 함유된 물질을 배선의 힐록 방지용 캡핑 메탈로 사용하는 반도체 제품의 비아홀 형성 공정에 있어서, 상기 층간 절연막(4) 및 캡핑 메탈층(3)을 저주파 건식 식각기로 식각할 경우 제1b도에 나타낸 바와 같이 비아홀(7) 내의 측벽에 티타늄이 함유된 폴리머(6)가 발생되며, 이러한 현상은 저주파(400KHz) 발생기를 장치한 건식 식각기를 사용할 경우 더욱 현저해진다. 이같은 사실은 45th and 46th Schools on Thin Film Technology (1984 4월) SL-III-43쪽 이하 등에서 잘 알려진 사실이다.However, in the via hole forming process of a semiconductor product using the titanium-containing material as the anti-heel capping metal of the wiring in the semiconductor manufacturing process as described above, the interlayer insulating film 4 and the capping metal layer 3 Is a low-frequency dry etcher, as shown in FIG. 1b, a polymer (6) containing titanium is formed on the sidewalls of the via hole (7). This phenomenon occurs when a dry etcher equipped with a low-frequency (400 KHz) generator is used. Becomes more remarkable. This is well known in the 45th and 46th Schools on Thin Film Technology (April 1984) SL-III-43 and below.

이 폴리머(6)는 산소(O2)를 에칭용 가스로 사용한 플라즈마 애싱(ashing)이나 화학적 스트리핑(stripping)으로 제거되지 않으므로, 폴리머(6)의 두께 만큼 비아홀의 크기 감소 현상이 발생하게 되고, 비아홀 내부에 배선 메탈을 형성할때 폴리머(6)에 의한 블로킹 효과로 접촉저항이 증가하거나 비아 메탈의 스텝 커버리지(Step Coverage)가 나빠지는 등의 문제점이 있다. 또한 건식 식각기로 층간 절연막(4)을 식각한 후, 연이어 캡핑 메탈층(3)인 티타늄이 함유된 물질을 제거할 경우에 층간 절연막(4)을 식각하는 시간의 200% 이상 오버 에치를 실시해야하므로 오버 에치가 진행되는 동안 비아홀의 크기가 증가하게 되어 실제 제품 생산 공정으로는 적당하지 않다.Since the polymer 6 is not removed by plasma ashing or chemical stripping using oxygen (O 2 ) as an etching gas, the size of the via hole is reduced by the thickness of the polymer 6. When the wiring metal is formed in the via hole, there is a problem such that the contact resistance is increased or the step coverage of the via metal is deteriorated due to the blocking effect by the polymer 6. In addition, after the interlayer insulating film 4 is etched using a dry etcher, when the material containing titanium as the capping metal layer 3 is subsequently removed, over-etching of the interlayer insulating film 4 must be performed over 200% of the time. Therefore, the size of the via hole increases during the over etch, which is not suitable for the actual production process.

따라서 이 발명의 목적은 비아홀의 크기가 확대되지 않고 폴리머가 발생되지 않으면서 티타늄이 함유된 힐록 방지용 캡핑 메탈을 제거할 수 있는 반도체 장치의 비아홀 형성 방법을 제공하는데 있다.Accordingly, an object of the present invention is to provide a method for forming a via hole in a semiconductor device capable of removing the anti-hilllock capping metal containing titanium without increasing the size of the via hole and generating no polymer.

이러한 목적을 달성하기 위하여 이 발명은 티타늄이 함유된 물질을 힐록 방지용 캡핑 메탈로 사용하는 반도체 장치의 비아홀 형성 방법에 있어서, 반도체 기판 위에 제1 배선층을 형성시키는 공정과, 상기 제1 배선층에 힐록 방지용 캡핑 메탈을 형성시키는 공정과, 상기 제1 배선층과 그 위에 형성시킬 제2 배선층 간을 절연시키기 위해 절연막을 형성시키는 공정과, 상기 캡핑 메탈이 드러나기 직전까지 상기 절연막을 건식 식각하는 공정과, 고주파 건식 식각기로 플라즈마 상태에서 상기 캡핑 메탈을 식각하거나, 상기 캡핑 메탈을 H2O2상태에서 습식 식각하는 공정을 거쳐 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a via hole forming method of a semiconductor device using a titanium-containing material as an anti-lock capping metal, wherein the first wiring layer is formed on a semiconductor substrate, and the anti-hill lock is formed on the first wiring layer. Forming a capping metal; forming an insulating film to insulate between the first wiring layer and a second wiring layer to be formed thereon; and dry etching the insulating film until immediately before the capping metal is exposed; The capping metal may be etched in a plasma state using an etcher or wet etching the capping metal in a H 2 O 2 state.

이하, 발명의 한 실시예를 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

제2도 (a)-(c)는 이 발명의 비아홀 형성 공정을 보인 공정도이다. 먼저, 실리콘 기판(1)의 표면 위에 마그네트론 스퍼터링법에 의해 제1 배선층(2)이 될 알루미늄막인 제1막을 적층시키고, 상기 제1 배선층(2)에 힐록 방지용 캡핑 메탈층(3)을 차례로 형성시키며, 상기 제1 배선층(2)과 그 위에 형성시킬 제2 배선층 간을 절연시키기 위해 절연막(4)을 형성시키며, 비아홀을 형성시킬 예정 부위에 사진 식각법을 사용하여 레지스트 패턴(5)을 형성시킨다.(제2도의 (a) 참조) 상기 레지스터 패턴(5)을 마스크로 하여 상기 절연막(4)을 건식 식각기를 이용하여 일반적인 식각 조건으로 절연막(4)을 식각 완료한 후,(제2도의 (b) 참조), 고주파 발생기(13.56MHz)를 장착한 건식 식각기에서 CF4/He/O2가스 분위기, CF4/He 가스 분위기; CF4/04가스분위기 및 CF4가스 분위기 중 그 어느 하나의 가스 분위기로 형성된 플라즈마 상태에서 티타늄이 함유된 힐록 방지용 캡핑 메탈(3)을 식각한다.(제2도의 (c)참조) 이때 절연막의 에치 레이트(etch rate)와 포토 레지스트의 에치 레이트를 0.7-1 : 1-0.7이 되도록 구성된 조건에서 식각이 진행되도록 한다.2 (a)-(c) are process charts showing the via hole forming process of the present invention. First, a first film, which is an aluminum film to be the first wiring layer 2, is laminated on the surface of the silicon substrate 1 by the magnetron sputtering method, and the antilock capping metal layer 3 is sequentially placed on the first wiring layer 2. Forming an insulating film 4 to insulate between the first wiring layer 2 and the second wiring layer to be formed thereon, and using the photolithography method on the site where the via hole is to be formed. (Refer to (a) of FIG. 2) After the etching of the insulating film 4 is completed under general etching conditions using the dry etching machine using the insulating film 4 as a mask (see FIG. 2). (B) of FIG.), CF 4 / He / O 2 gas atmosphere, CF 4 / He gas atmosphere in a dry etcher equipped with a high frequency generator (13.56 MHz); (See the second-degree (c)), CF 4/0 4 gas atmosphere, and the CF 4 is etched to a gas atmosphere that any one of the hillock preventing capping metal (3) the titanium is contained in the plasma state is formed as a gas atmosphere. In this case the insulating film The etch rate of the photoresist and the etching rate of the photoresist are set to be 0.7-1: 1-0.7.

이 발명의 다른 실시예는 상기 실시예와는 캡핑 메탈층의 식각 방식이 다른 것으로, 절연막을 건식 식각기를 이용하여 일반적인 식각 조건으로 절연막(4)을 식각 완료할 때까지의 전 공정은 동일하나, 절연막 식각 후 캡핑 메탈층(3)을 H2O2를 사용하여 습식 식각을 실시한다.According to another embodiment of the present invention, the capping metal layer has a different etching method from the above embodiment, and the entire process until the insulating film 4 is etched under general etching conditions using the dry etching machine is the same. After etching the insulating film, the capping metal layer 3 is wet-etched using H 2 O 2 .

이와 같은 공정으로 형성되는 비아홀은 절연막 및 캡핑 메탈의 에치 시폴리머가 발생되지 않으므로 식각 공정의 최적화를 기할 수 있으며, 또한 씨디 스큐(CD Skew)가 0.1㎛ 이하인 정밀한 비아홀을 형성할 수 있으므로 신뢰성이 높은 고성능 집적 회로를 안정되게 제조할 수 있다.The via holes formed in this process can optimize the etching process because no etch polymer of the insulating film and the capping metal is generated, and can also form a precise via hole having a CD skew of 0.1 μm or less, thus providing high reliability. High performance integrated circuits can be manufactured stably.

Claims (4)

티타늄이 함유된 물질을 힐록 방지용 캡핑메탈(3)로 사용하는 반도체 장치의 비아홀 형성방법에 있어서, 반도체 기판 위에 제1 배선층(2)을 형성시키는 공정과, 상기 제1 배선층에 힐록 방지용 캡핑 메탈층(3)을 형성시키는 공정과, 상기 제1 배선층(2)과 그 위에 형성시킬 제2 배선층 간을 절연시키기 위해 절연막(4)을 형성시키는 공정과, 상기 절연막(4) 상에 비아홀을 형성시킬 예정 부위에 포토 레지스트 패턴(5)을 형성시키는 공정과, 상기 캡핑 메탈층(3)이 드러나기 직전까지 상기 절연막(5)을 건식 식각하는 공정과, 고주파 건식 식각기로 플라즈마 상태에서 상기 캡핑 메탈층(3)을 식각하는 공정으로 행하여지는 반도체 장치의 비아홀 형성 방법.In the method for forming a via hole of a semiconductor device using a titanium-containing material as the antilock capping metal (3), forming a first wiring layer (2) on a semiconductor substrate, and a antilock capping metal layer on the first wiring layer (3) forming, forming an insulating film (4) to insulate the first wiring layer (2) from the second wiring layer to be formed thereon, and forming a via hole on the insulating film (4) Forming a photoresist pattern 5 on a predetermined portion; dry etching the insulating film 5 until the capping metal layer 3 is exposed; and capping metal layer in a plasma state using a high frequency dry etching machine ( A method of forming a via hole in a semiconductor device, which is performed by the step of etching 3). 제1항에 있어서, 상기 티타늄이 함유된 캡핑 메탈층(3)의 식각은 CF4/He/O2가스 분위기, CF4/He 가스 분위기, CF4/O2가스 분위기 및 CF4가스 분위기중 그 어느 하나로 행하여지는 것을 특징으로 하는 반도체 장치의 비아홀 형성 방법.The method of claim 1, wherein the titanium-containing capping metal layer 3 is etched in a CF 4 / He / O 2 gas atmosphere, CF 4 / He gas atmosphere, CF 4 / O 2 gas atmosphere and CF 4 gas atmosphere The via hole forming method of a semiconductor device, characterized in that any one of the. 제1항에 있어서, 상기 티타늄이 함유된 캡핑 메탈층(3)의 식각은 절연막(4)의 에치 레이트와 포토 레지스트의 에치 레이트를 0.7-1 : 1-0.7이 되도록 하는 조건에서 식각을 진행하는 것을 특징으로 하는 반도체 장치의 비아홀 형성 방법.The method of claim 1, wherein the etching of the titanium-containing capping metal layer 3 is performed by etching under conditions such that the etch rate of the insulating film 4 and the etch rate of the photoresist are 0.7-1: 1-0.7. A via-hole forming method of a semiconductor device, characterized in that. 티타늄이 함유된 물질을 힐록 방지용 캡핑 메탈(3)로 사용하는 반도체 장치의 비아홀 형성 방법에 있어서, 반도체 기판 위에 제1 배선층(2)을 형성시키는 공정과, 상기 제1 배선층에 힐록 방지용 캡핑 메탈층(3)을 형성시키는 공정과, 상기 제1 배선층(2)과 그 위에 형성시킬 제2 배선층 간을 절연시키기 위해 절연막(4)을 형성시키는 공정과, 상기 절연막(4) 상에 비아홀을 형성시킬 예정 부위에 포토 레지스트 패턴(5)을 형성시키는 공정과, 상기 캡핑 메탈층(3)이 드러나기 직전까지 상기 절연막(5)을 건식 식각하는 공정과, 상기 캡핑 메탈을 H2O2상태에서 습식 식각하는 공정으로 행하여지는 반도체 장치의 비아홀 형성 방법.In the method for forming a via hole of a semiconductor device using a titanium-containing material as the anti-lock capping metal 3, a step of forming a first wiring layer 2 on a semiconductor substrate, and a anti-locking capping metal layer on the first wiring layer (3) forming, forming an insulating film (4) to insulate the first wiring layer (2) from the second wiring layer to be formed thereon, and forming a via hole on the insulating film (4) Forming a photoresist pattern 5 on a predetermined portion; dry etching the insulating film 5 until the capping metal layer 3 is exposed; and wet etching the capping metal in a H 2 O 2 state. The via-hole formation method of a semiconductor device performed by the process of carrying out.
KR1019910008734A 1991-05-28 1991-05-28 Forming method of via hole in semiconductor device KR0181959B1 (en)

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