JPH02275627A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a residual foreign film to be eliminated selectively by using a corrosive atmosphere by eliminating an organic film master pattern by the oxygen ashing method after etching a substance layer to be machined by the reactive ion etching method. CONSTITUTION:An oxidation silicon film 2 and a polycrystal silicon film 3 are laminated in sequence on a silicon substrate 1 and a mask pattern 4 of an organic photo resist is formed on it, thus eliminating one part of the polycrystal silicon film 3 up to the oxidation silicon film 2 by reactive ion etching. At this time, a protruding foreign object 5 is adhered to the polycrystal silicon pattern side wall but an organic substance constituent within the foreign object 5 is simultaneously ashed and eliminated when eliminating the photo resist 4 by the oxygen plasma ashing method, thus enabling the residual foreign object be porous. Then, the entire substrate is dipped into the mixed liquid of hydrofluoric acid, nitric acid, and acetic acid, thus eliminating only the protruding foreign object 5 selectively and obtaining a fine pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device using a reactive ion etching method for forming a fine pattern.

(Prior Art and its Problems) In recent years, efforts have been made to improve the characteristics and increase the integration of semiconductor devices. As a means of achieving high integration, an arbitrary pattern is formed on the etching layer, which is the workpiece layer, using a reduction projection exposure device and a photoresist, and this layer is selected by reactive ion etching. Microfabrication technology using etching is the mainstream.

For example, 4 Mbit DRAM, which is an example of a cutting-edge product,
(dynamic random access memory) is 0.7μ
A line width dimension of m (submicron) is adopted. In order to form this submicron pattern layer, the photoresist pattern serving as an etching mask has steeper pattern side surfaces in order to eliminate finished dimensional errors due to film burrs in the lateral direction of the mask pattern during etching. For etching, reactive ion etching is used in which gaseous ions are applied perpendicularly to the main surface of the etching layer. Etching progresses not only by chemical reaction between the layer to be etched and reactive ions, but also by sputtering by incident ions. This sputtering progresses not only on the sidewalls of the photoresist, which is the mask material, but also on the sidewalls of the layer to be etched. In conventional semiconductor devices, the side surfaces of the pattern of the photoresist mask were not steep, so the foreign matter to be sputtered adhering to this side surface was removed by etching, or even if it was not removed, it was removed from the side surface of the pattern, especially on the top surface (main surface). ) and was relatively unproblematic. However, in reactive ion etching when a steep pattern side surface is used, sputtering foreign matter adhering to the pattern side surface is not removed by etching, and therefore remains as a layer covering the side surface. This film of foreign matter to be sputtered is not removed even in the subsequent oxygen plasma ashing process of the photoresist, and remains as protruding foreign matter on the processed layer to be etched.

The remaining protruding foreign matter (foreign matter film to be sputtered) is not removed in the subsequent layer forming step for manufacturing a semiconductor device, but is incorporated into the formed layer. This problem will be explained in detail with reference to FIGS. 3A to 3C regarding etching of a polysilicon film used for a gate electrode of a semiconductor device. As shown in FIG. 3A, a silicon substrate 31
On top of this, there is a silicon thermal oxide film 32 with a thickness of 200 Å grown on this, a polycrystalline silicon film 33 with a thickness of 3000 Å grown on top of this by the low pressure CVD method, and this film 33 on top of this. A photoresist pattern 34 for selective etching is sequentially formed. CC is used as an etching gas using a parallel plate type reactive ion etching device.
J74 and He were each used at a flow rate of 1,00 cc/min, and the pressure in the etching chamber was set to 0.2 torr.
The polycrystalline silicon film 33 is etched for 50 seconds with the high frequency power applied to the electrode set to 0.5/cd. At this time, due to the sputtering that occurs simultaneously with etching, sputtered foreign matter 35 adheres to the sidewalls of the photoresist pattern 33 and the polysilicon pattern, as shown in FIG. 3B. However, the sputtering foreign matter 35 attached to the side wall of the polysilicon pattern is not removed and remains so as to protrude from the upper surface of the polycrystalline silicon film 33, as shown in FIG. 3C.

A similar problem also occurs in the case of a semiconductor device formed with an AΩ (including the case of Ag alloy, hereinafter the same) multilayer wiring J+i structure.

In other words, in order to form the second Ag wiring layer with high precision, it is necessary to planarize the interlayer insulating film, and the planarization technique is resist etching or SOG (SPI).
Although the non-on-grass method is known, there is a problem in that flattening is hindered when the above-mentioned foreign matter to be sputtered is present.

This problem will be explained in the case where the resist etching method is applied with reference to FIGS. 48 to 4E.

FIG. 4A shows the state immediately after the first layer wiring pattern 47 is formed. In this figure, 41 is a P-type silicon substrate, 42 is a field oxide film, 43 is a gate oxide film, 44 is a polysilicon gate electrode, 45a, 45b
4 indicates source and drain diffusion layers, and 46 indicates a first interlayer insulating film.

For the first layer wiring pattern 47, an Ap alloy film is deposited to a thickness of about 1 μm, a photoresist mask pattern is formed thereon, and then reactive ion etching is performed using CN2 gas. At this time, as in the case of the example shown in FIG. 3B, the foreign substance film 48 with a partially protruding part adheres to the steep sidewall of the first layer wiring pattern 47 due to the anisotropic etching action.

Since this foreign matter film 48 is formed from an aluminum compound, it is not removed when the photoresist is removed by oxygen ashing.
A portion remains on the side wall of the wiring pattern 41 in an upwardly protruding state. Subsequently, after performing a pure water treatment, a first interlayer insulating film 49 is applied as shown in FIG. 4, and a photoresist layer 50 is spin-coated thereon as shown in FIG. 4C. As shown in FIG. 4D, the first interlayer insulating film 49 is planarized by an etching method.

Next, as shown in FIG. 4E, a second interlayer insulating film 51 is coated to maintain the dielectric strength, and a communication hole is opened to connect to the wiring pattern 41 of the first layer 1.
Layer A11) A wiring pattern 52 is formed, and a predetermined semiconductor device is manufactured.

However, as shown in FIG. And/or narrow grooves 49b are formed, and even after the etching process, grooves remain formed on the surface as shown in FIG. 4D. Therefore, if the second interlayer insulating film 51 and the second wiring pattern 52 are formed in the same state, a disconnection portion 52a will occur in the second layer wiring pattern 52 as shown in FIG. 4E.
Problems such as a short circuit (not shown) occurring between the second layer wiring patterns occur.

As a method for removing this foreign matter film,
One proposal was made in 18973.

In this method, after a mask pattern is formed on the etching layer, ion etching is performed, and as a result, the foreign material film that is formed on the side wall of the mask pattern or the object to be etched is chemically etched using a wet method using an inorganic acid. In this method, the mask pattern is removed by etching and then by plasma ashing.

However, a drawback of this method is that the object to be etched is affected by this chemical etching, resulting in significant local etching, resulting in many product defects. This is thought to be because chemical etching is performed before resist stripping, so the trace amount of chlorine (derived from etching gas, etc.) present in the resist acts as a catalyst and promotes the etching of the object to be etched. .

(Problems to be Solved by the Invention) As described above, in semiconductor devices, high JJ! With the increase in the number of semiconductor devices, the formation of C1 fine patterns has become an essential condition, and for this reason, microfabrication using a photoresist mask with steep pattern sides and reactive ion etching has become mainstream. Protruding foreign matter on the sidewalls has been causing problems such as poor insulation and poor shape of semiconductor devices, resulting in performance deterioration.Therefore, there has been a desire to develop an effective method for removing these protruding foreign matter.

The present invention has been made in view of the above circumstances, and provides a method for manufacturing a semiconductor device that can achieve microfabrication in the submicron region with high precision using reactive ion etching and improve the reliability of the semiconductor device. The purpose is to

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention includes a step of forming a workpiece layer on a semiconductor substrate, and processing the workpiece layer on the workpiece layer. a step of forming an organic film mask pattern for
A method for manufacturing a semiconductor device, comprising the steps of processing the workpiece layer using a reactive ion etching method, and removing the organic film mask pattern using an oxygen ashing method containing at least oxygen molecules. In this method, after removing the organic film mask pattern, the workpiece is exposed to an etching medium that etches at least the workpiece layer and/or the underlying layer of the workpiece layer.

Note that the corrosive medium may be liquid or gaseous. There are no particular restrictions on the type of workpiece mentioned above (it can be applied to any type of workpiece, such as wiring layers made of silicon semiconductors, aluminum alloys, etc.).If the workpiece is aluminum or aluminum alloy, phosphoric acid is used as the corrosion medium. A solution consisting of a mixed solution mainly consisting of hydrofluoric acid, hydrofluoric acid, and alcohol is preferable.

(Function) After etching the corrugated material layer using a reactive ion etching method, the organic film mask pattern is removed using an oxygen ashing method containing oxygen molecules, thereby removing organic components in the foreign material film attached to the side wall of the workpiece. is also removed by ashes at the same time, so the residual foreign matter film becomes porous, and as a result, under conditions that will not have a negative effect on the workpiece and its underlying layer,
It becomes possible to easily and selectively remove the residual foreign matter film using an appropriate corrosive medium.

(Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1A to 1C.

A silicon oxide film (2) is deposited on a silicon substrate (1) to a thickness of 2
A polycrystalline silicon film (3) containing impurity phosphorous (I x 102] atoms/cii was formed on the entire surface of the silicon oxide film (2) to a thickness of 4000 A using a low pressure CVD method. ,accumulate. Next, a photoresist mask pattern (4) with 0.7μ lines and spaces is formed on the polycrystalline silicon film (3) using a 115 reduction projection exposure apparatus.Subsequently, cB,...
Gas 100 cc/m1n-He gas 100 cc/m
ln ・Pressure 0.2 torr ・Applied high frequency power 0.5
Reactive ion etching for 70 seconds under W/cd conditions,
As shown in FIG. 1A, a portion of the polycrystalline silicon film (3) is removed up to the silicon oxide film (2). Continuing, the first
As shown in Figure B, the entire substrate is exposed to an oxygen pressure of 1 tor.
Oxygen plasma ashing is performed for 30 minutes under the conditions of applied high-frequency power of 3 W/c-, and the photoresist mask is removed from the upper surface of the polycrystalline silicon film (3). After this, the entire semiconductor substrate was soaked in hydrofluoric acid, nitric acid, and acetic acid (weight ratio -5:20).
It is immersed in an etching solution consisting of a mixed solution of Nia 00) for 30 seconds. According to this mixture ratio, the etching rate of the polycrystalline silicon film (3), which is the workpiece, is as low as 100 A per minute, so the etching rate is as low as 100 A per minute. Only the protruding foreign matter (5) attached to the side wall of the silicon pattern could be selectively removed as shown in FIG. 1C.

The principle by which only the protruding foreign matter (5) attached to the side wall of the polycrystalline silicon pattern can be selectively removed is that the protruding foreign matter (5) attached during reactive ion etching is a photoresist processed material. It is thought to be a mixture of a crystalline silicon film and/or a silicon oxide film, which is the lower layer, and when the photoresist, which is the etching mask, is removed by oxygen ashing, the organic components in the sidewall foreign matter are also removed at the same time. Ashed and removed. As a result, the remaining side wall foreign matter becomes porous and has an increased surface area, so it is selectively etched in the subsequent etching with a mixed solution of hydrofluoric acid, nitric acid, and acetic acid (weight ratio -5.20Nia00). Understand it as a thing.

According to this example, it can be seen that even with a fine pattern of lines and spaces of 0.7 .mu.m, it is possible to perform good etching with foreign matter removed from the side walls. Furthermore, if the present invention is applied to microfabrication of a polycrystalline silicon film that is a gate electrode material of a MOS type transistor, it is possible to manufacture a semiconductor device having a submicron gate transistor.

Next, a second embodiment will be described with reference to FIGS. 2A to 2F.

This embodiment shows an example in which a multilayer wiring structure made of an AI-5i-Cu alloy is formed in a semiconductor device.

FIG. 2A shows the state immediately after the first layer wiring pattern 17 is formed. In this figure, reference numeral 11 is a silicon substrate, 12 is a field oxide film, 13 is a gate oxide film, 14 is a polysilicon gate electrode, 15a and 15b are source and drain diffusion layers, and 16 is a first interlayer insulating film. shows. This first layer wiring pattern 17 was formed as follows. First, AI-31-Cu(Si:
10%, Cu: 0.5%) alloy film is formed to a thickness of 0.8 μm, and a predetermined photoresist mask pattern is formed thereon, and then etching gas (Cfz: CC, Q) is formed.
, + :N2-20:20:1000cc/min), pressure (1, otorr), high frequency power (13,5(
The alloy film was selectively etched for 70 seconds under soching conditions of iMIIz: 3 W/c+T). Next, the photoresist mask pattern was ashed and removed by an oxygen plasma ashing method under the conditions of oxygen gas 50 cc/min, pressure 0.9 torr, high frequency power 13.5 MIIz: 0.4 W/c-, and the photoresist mask pattern was removed by ashing. As shown in the figure, the first
A foreign substance film 18 remained and protruded on the side wall of the wiring pattern 17 of each layer.

Then, as shown in FIG. 2B, the whole was immersed in a solution 19 of phosphoric acid:hydrofluoric acid:alcohol (100:1:100 volume ratio) for 1 minute, and then washed with pure water.

As a result, a normal wiring pattern 17 from which the foreign material film 18 was selectively removed could be obtained as shown in FIG. 2C.

According to the usual manufacturing process, as shown in FIG. 2D,
A second first interlayer insulating film 20 was deposited to a thickness of 1.2 μm by plasma CVD using silane gas and nitrous oxide gas (N20). In order to subsequently perform a resist etchback method, the photoresist 21 is removed from the insulating film 20.
It was applied to the entire surface. After flattening the surface of the insulating film 20 by performing an etching process in this state, the second interlayer insulating film 22 is deposited on the first layer as shown in FIG. 2E.
The first insulating film 20 is formed on the second insulating film 20, and then these insulating films 20 are
．． Openings were made at appropriate locations in 22, and a second layer of 1-alloy wiring pattern 23 was formed to obtain a semiconductor device as shown in FIG. 2F. The semiconductor device thus obtained is the second
No disconnections in the A47 alloy wiring patterns 23 or short circuits between the wiring patterns were observed.

A third embodiment will be described below.

A thermal oxide film with a thickness of 100 Å was formed on the surface of a (100) plane silicon substrate at a temperature of 900° C., and then an AΩ-5i-Cu film with a thickness of 10000 Å was formed on the thermal oxide film by sputtering. Next, the wiring pattern is line + lt, the line spacing is 0.8 μm, and the wiring length is 12 m, and a mask pattern is formed using a positive resist with a thickness of 1.5 μm.
, 17-5i-Cu film, and etching gas (BCΩ3:C12:CO:He-1000cc/
Min: 50cc/min + 50cc/min: 2000cc/min)
The A, Q-5i-Cu films were selectively etched for 100 seconds under the conditions of a pressure of 100 PaS and a high frequency power of 500 W to form a first layer wiring pattern. At this time, the side wall of the wiring pattern has the same tightness as shown in FIG. 2A.
, a foreign material film of I was attached.

Next, the photoresist mask was removed by oxygen plasma ashing treatment under the conditions of 02.100 cc/min, pressure of 130 Pa, high frequency power of 500 W, and time of 30 minutes.

Then, the whole was mixed with phosphoric acid:hydrofluoric acid:alcohol (100:
After being immersed in a solution with a volume ratio of 1:100 for 1 minute, it was washed with pure water.

Thereafter, by the same process as in Example 2, the wiring pattern of the second layer [] is changed to the same line +l as the wiring pattern of the first layer [''.
J, line spacing and line length, and the probability of occurrence of short circuits and disconnections was determined in 7111j. As a result, the yield was 99.4%
Met.

Comparative Example In the third example, all treatments were carried out in the same manner as in Example 3, except that the order of the oxygen plasma ashing treatment and the immersion treatment in a mixed solution of phosphoric acid: hydrofluoric acid: alcohol was reversed. , a multilayer wiring was formed. Next, when we measured the probability of occurrence of short circuits and disconnections in the second layer wiring pattern, the yield was 13.
%Met.

The etching for removing the protruding foreign matter (5) is as follows:
The liquid mixture is not limited to phosphoric acid, hydrofluoric acid, and alcohol. For example, hydrofluoric acid, nitric acid, acetic acid (5: 20 +
700 (weight ratio) or a 1% choline aqueous solution.

In the above embodiments, solution etching was used to remove the protruding foreign matter (5), but other etching methods may also be used. An example is given below.

1゜The entire semiconductor substrate is heated with nitrogen trifluoride gas (NF3:
100 cc/min) and chlorine (Cρ2: 150 cc/min)
, Hg- as a mercury light source under a pressure of 20 torr.
40 at a photoexcitation condition of 0.5 W/cd using a Xe lamp.
Optical etching that performs etching in seconds.

Similar effects can be obtained by using an etching device that uses excimer laser light instead of mercury light.

In addition, similar results can be obtained by using scattered light in place of the parallel light beams or parallel focused light beams used in general photoexcitation etching equipment (microfabrication).

2. The entire semiconductor substrate is heated in a plasma generation chamber with carbon tetrafluoride gas (CF4: 200 cc/min) and oxygen (0
2:50cc/min), pressure 1. Plasma etching was carried out for 40 seconds under the conditions of Otorr and high frequency power (0.1 W/c4: 13.56 MIIz).

Note that the same effect as described above can be obtained by using an etching apparatus in which the plasma generation chamber and the etching chamber are separated, using microwave power instead of the high frequency power.

[Effects of the Invention] As detailed above, according to the method of the present invention, it is possible to -H a fine pattern with a steep cross-sectional shape, and to manufacture a highly reliable and highly integrated semiconductor device at a high yield. becomes.

[Brief explanation of drawings]

3A to 3C are sectional views illustrating a conventional method in the order of steps, and FIGS. 4A to 4E are sectional views illustrating a different conventional method in the order of steps. It is sectional drawing explained in order. 1... Silicon substrate, 2... Silicon oxide film, 3.
... Polycrystalline silicon film, 4... Mask pattern, 5.
...Protruding foreign matter, 11...P-type silicon substrate, 12.
...Field oxide film, 13...Gate oxide film, 14
...Polysilicon gate electrodes, 15a, 15b...
Source and drain diffusion layer, 16... first interlayer insulating film, ] 7... second wiring pattern, 18... foreign matter film, 19... mixed solution of phosphoric acid, hydrofluoric acid, and alcohol ,
21... Photoresist, 22... Second layer interlayer insulating film, 23... Wiring pattern of second layer r1. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1A Figure 2A IB Fj 28゛゛゛゛ 1C 1:, 2C 2D To Figure 1 Iko A Figure 4B Figure '4C F2 Figure A Figure B Gu 4E r=

Claims (6)

[Claims] (1) A step of forming a workpiece layer on a semiconductor substrate, a step of forming an organic film mask pattern for processing this workpiece layer, and a step of forming a workpiece layer on the workpiece layer using reactive ions. a step of processing by an etching method, a step of removing the organic film mask pattern using an oxygen ashing method containing at least oxygen molecules, and after this removal step, at least the workpiece layer or the workpiece layer A method for manufacturing a semiconductor device, comprising: exposing the underlayer to a corrosive medium that etches the underlying layer. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the corrosive medium is a solution. (3) The method for manufacturing a semiconductor device according to claim 2, wherein the workpiece layer is aluminum or an aluminum alloy, and the solution is a solution containing phosphoric acid and hydrofluoric acid. (4) The method for manufacturing a semiconductor device according to claim 2, wherein the solution is gaseous. (5) The method for manufacturing a semiconductor device according to claim 4, wherein the gaseous solution is excited by light. (6) The method of manufacturing a semiconductor device according to claim 4, wherein the gaseous solution is excited by high frequency or microwave.