JP2968289B2 - 中央演算処理装置 - Google Patents

中央演算処理装置

Info

Publication number
JP2968289B2
JP2968289B2 JP1290667A JP29066789A JP2968289B2 JP 2968289 B2 JP2968289 B2 JP 2968289B2 JP 1290667 A JP1290667 A JP 1290667A JP 29066789 A JP29066789 A JP 29066789A JP 2968289 B2 JP2968289 B2 JP 2968289B2
Authority
JP
Japan
Prior art keywords
data
address
instruction
branch
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1290667A
Other languages
English (en)
Japanese (ja)
Other versions
JPH03150634A (ja
Inventor
慎一 山浦
隆 安井
圭一 吉岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP1290667A priority Critical patent/JP2968289B2/ja
Priority to DE4035405A priority patent/DE4035405A1/de
Publication of JPH03150634A publication Critical patent/JPH03150634A/ja
Priority to US08/177,794 priority patent/US5511173A/en
Application granted granted Critical
Publication of JP2968289B2 publication Critical patent/JP2968289B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/223—Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Executing Machine-Instructions (AREA)
JP1290667A 1989-11-08 1989-11-08 中央演算処理装置 Expired - Fee Related JP2968289B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP1290667A JP2968289B2 (ja) 1989-11-08 1989-11-08 中央演算処理装置
DE4035405A DE4035405A1 (de) 1989-11-08 1990-11-07 Programmierbare logik-anordnung und datenverarbeitungseinrichtung mit einer solchen logik-anordnung
US08/177,794 US5511173A (en) 1989-11-08 1994-01-05 Programmable logic array and data processing unit using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1290667A JP2968289B2 (ja) 1989-11-08 1989-11-08 中央演算処理装置

Publications (2)

Publication Number Publication Date
JPH03150634A JPH03150634A (ja) 1991-06-27
JP2968289B2 true JP2968289B2 (ja) 1999-10-25

Family

ID=17758937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1290667A Expired - Fee Related JP2968289B2 (ja) 1989-11-08 1989-11-08 中央演算処理装置

Country Status (3)

Country Link
US (1) US5511173A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JP2968289B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE4035405A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

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US5737631A (en) * 1995-04-05 1998-04-07 Xilinx Inc Reprogrammable instruction set accelerator
US5805871A (en) * 1995-07-21 1998-09-08 Ricoh Company Ltd. System and method for phase-synchronous, flexible-frequency clocking and messaging
US5794062A (en) * 1995-04-17 1998-08-11 Ricoh Company Ltd. System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US6266756B1 (en) * 1995-07-17 2001-07-24 Ricoh Company, Ltd. Central processing unit compatible with bank register CPU
US5943242A (en) 1995-11-17 1999-08-24 Pact Gmbh Dynamically reconfigurable data processing system
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US5854918A (en) * 1996-01-24 1998-12-29 Ricoh Company Ltd. Apparatus and method for self-timed algorithmic execution
DE19651075A1 (de) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
DE19654593A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Umkonfigurierungs-Verfahren für programmierbare Bausteine zur Laufzeit
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
US6338106B1 (en) * 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
EP1329816B1 (de) 1996-12-27 2011-06-22 Richter, Thomas Verfahren zum selbständigen dynamischen Umladen von Datenflussprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o.dgl.)
DE19654846A1 (de) * 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
DE19704044A1 (de) * 1997-02-04 1998-08-13 Pact Inf Tech Gmbh Verfahren zur automatischen Adressgenerierung von Bausteinen innerhalb Clustern aus einer Vielzahl dieser Bausteine
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704728A1 (de) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
DE19704742A1 (de) * 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internes Bussystem für DFPs, sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen, zur Bewältigung großer Datenmengen mit hohem Vernetzungsaufwand
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) * 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
US5987559A (en) * 1998-02-02 1999-11-16 Texas Instruments Incorporated Data processor with protected non-maskable interrupt
DE19807872A1 (de) 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Verfahren zur Verwaltung von Konfigurationsdaten in Datenflußprozessoren sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstruktur (FPGAs, DPGAs, o. dgl.
US7782844B1 (en) * 1999-01-05 2010-08-24 GlobalFoundries, Inc. Method and apparatus for pattern matching on single and multiple pattern structures
DE10081643D2 (de) 1999-06-10 2002-05-29 Pact Inf Tech Gmbh Sequenz-Partitionierung auf Zellstrukturen
EP1342158B1 (de) 2000-06-13 2010-08-04 Richter, Thomas Pipeline ct-protokolle und -kommunikation
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
ATE437476T1 (de) 2000-10-06 2009-08-15 Pact Xpp Technologies Ag Zellenanordnung mit segmentierter zwischenzellstruktur
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US6990555B2 (en) * 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
WO2005045692A2 (en) 2003-08-28 2005-05-19 Pact Xpp Technologies Ag Data processing device and method
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
EP2224330B1 (de) 2001-06-20 2012-05-09 Krass, Maren Verfahren und gerät zum partitionieren von grossen rechnerprogrammen
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) * 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
JP4044756B2 (ja) * 2001-12-11 2008-02-06 松下電器産業株式会社 プログラム変換装置、プログラム変換方法、及び当該プログラム変換装置を実現するプログラム
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
JP2003190367A (ja) * 2001-12-21 2003-07-08 Konami Co Ltd 虚像、実映像重畳表示装置及び映像表示制御方法、ならびに映像表示制御用プログラム
DE10392560D2 (de) 2002-01-19 2005-05-12 Pact Xpp Technologies Ag Reconfigurierbarer Prozessor
EP1514193B1 (de) 2002-02-18 2008-07-23 PACT XPP Technologies AG Bussysteme und rekonfigurationsverfahren
JP4146654B2 (ja) * 2002-02-28 2008-09-10 株式会社リコー 画像処理回路、複合画像処理回路、および、画像形成装置
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
WO2004021176A2 (de) 2002-08-07 2004-03-11 Pact Xpp Technologies Ag Verfahren und vorrichtung zur datenverarbeitung
JP3976089B2 (ja) * 2002-08-09 2007-09-12 株式会社リコー 半導体集積回路装置及びその製造方法
JP4388895B2 (ja) 2002-09-06 2009-12-24 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト リコンフィギュアラブルなシーケンサ構造
US7464310B2 (en) * 2002-09-30 2008-12-09 Broadcom Corporation Programmable state machine of an integrated circuit
JP4296051B2 (ja) * 2003-07-23 2009-07-15 株式会社リコー 半導体集積回路装置
US8595688B1 (en) * 2003-09-08 2013-11-26 Synopsys, Inc. Generation of instruction set from architecture description
KR100632943B1 (ko) * 2004-05-29 2006-10-12 삼성전자주식회사 저전력 및 고속 프로그램 가능한 로직 어레이
KR100578142B1 (ko) 2004-12-09 2006-05-10 삼성전자주식회사 프로그래머블 로직 어레이
WO2007062327A2 (en) * 2005-11-18 2007-05-31 Ideal Industries, Inc. Releasable wire connector
JP2009524134A (ja) 2006-01-18 2009-06-25 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト ハードウェア定義方法
US7541832B1 (en) * 2007-04-30 2009-06-02 Arizona Board Of Regents For And On Behalf Of Arizona State University Low power, race free programmable logic arrays

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US4947369A (en) * 1982-12-23 1990-08-07 International Business Machines Corporation Microword generation mechanism utilizing a separate branch decision programmable logic array
US4713750A (en) * 1983-03-31 1987-12-15 Fairchild Camera & Instrument Corporation Microprocessor with compact mapped programmable logic array
JPS60145488A (ja) * 1984-01-06 1985-07-31 Hitachi Ltd 給液システム制御装置
US4839890A (en) * 1986-10-31 1989-06-13 Ncr Corporation Data bit synchronizer
US5123096A (en) * 1987-08-03 1992-06-16 Masahito Matuo Data processor with addressing mode decoding function

Also Published As

Publication number Publication date
DE4035405C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-01-14
DE4035405A1 (de) 1991-05-16
JPH03150634A (ja) 1991-06-27
US5511173A (en) 1996-04-23

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