JP2964895B2 - Field effect transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor having an extension structure in which a diffusion layer extends shallowly to a channel side, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A field-effect transistor having a structure in which a high-concentration impurity region is extended from a source / drain to a channel region in contact with a substrate surface and shallower than the source / drain, that is, an extension structure. By Taua et al., 1992 IEDM Technical Digest, page 901 (Y. Taur, et. Al., 1992 IEDM).
Tech. Dig. p. 901). FIG. 30 shows the structure. This is because the thinning of the diffusion layer, which is effective for suppressing the short channel effect that causes the deterioration of MOSFET characteristics, is realized in the extension region 103 into which high-concentration boron is introduced, the parasitic resistance of the diffusion layer is reduced, and the contact formation is reduced. In addition, the depth of the diffusion layer necessary for the silicidation process is realized in the normal p ⁺ diffusion layer 102 located outside the extension region 103 (in the direction opposite to the channel).

A similar structure for an SOI MOSFET is described in Shahidi et al., 1993 VLSI Symposium on Technology, page 27 (GG Shahidi, et. Al., 1993).
VLSI Symp. onTech. p. 27). The structure is shown in FIG. As in the case of Tauer et al., A thin extension region 113 extends from the n ⁺ diffusion layer 112 to the channel side. In this example, a p-type impurity region 120 is provided below the extension region 113.

[0004] Although it is not an extension structure,
In order to obtain a shallow junction, Goto et al. In 1994 extended abstract of 1 formed a FET whose source and drain were formed by epitaxially growing a silicon-germanium mixed crystal doped with boron at a high concentration.
994 International Conference on Solid State Devices and Materials, 99
9 pages (K. Goto, et. Al., Ext. Ab)
s. 1994 SSDM, p. 999). FIG. 32 shows the structure. In the drawing, reference numeral 132 denotes an epitaxial silicon germanium layer.

A method of using germanium as a source in order to suppress the substrate floating effect of an SOIMOSFET is disclosed in, for example, Japanese Patent Application No. 3-106665 by Matsushita (Japanese Patent Application Laid-Open No. 4-313242). FIG. 33 shows the structure. Here, the LDD region 143 and the channel region 144 are made of silicon, while the source region 142 is made of germanium.

[0006]

However, if the extension portion is made thinner in order to suppress the short channel effect, the parasitic resistance in the extension portion increases.
Increasing the impurity concentration in the extension portion can reduce the parasitic resistance. However, when the extension portion is formed by ion implantation, increasing the impurity concentration increases the spread of impurities to the substrate method at the time of ion implantation or heat treatment for activating the implanted ions. Layering and resistance reduction can both be achieved.

In addition, the heat treatment performed after the formation of the extension and accompanying the formation of the source / drain diffusion layers causes impurities in the extension portion to spread to the substrate side, thereby increasing the thickness of the extension portion.

An object of the present invention is to provide an extension structure in which a diffusion layer is extended shallowly to a channel side in order to suppress a short channel effect. And a method for manufacturing the same.

[0009]

The present invention SUMMARY OF] includes, from the source-drain diffusion layer to the channel side, in contact with the substrate surface, and the shallower region than the source-drain, source
Extended diffusion layer containing impurities of the same conductivity type as the drain
In the field effect transistor having the extended structure described above, the source / drain extension, which is an extended diffusion layer , is formed of germanium or a mixed crystal of silicon and germanium.

Further, according to the present invention, in the above-described method for manufacturing a field effect transistor, a source / drain is formed by epitaxially growing a germanium layer containing impurities or a mixed crystal of silicon and germanium containing impurities.
It is characterized by forming a drain extension, after epitaxially growing a germanium layer or a mixed crystal layer of silicon and germanium on the substrate surface, and introducing impurities into the epitaxial layer.
It is characterized in that a drain extension is formed.

In the method of manufacturing a field effect transistor according to the present invention, a spacer is provided in contact with a side surface of the gate electrode.
After that, source / drain regions are formed,
The source and drain diffusion layers to the channel side
Toward the source / drain region
Epitaxy of silicon containing impurities in shallow regions
To form an epitaxial silicon layer.
Epitaxial silicon layer is the same as source / drain
In the region where the diffusion layer containing the conductive type impurity is extended.
It is characterized by forming an extension area .

In the method of manufacturing a field-effect transistor according to the present invention, the CVD oxide film is formed in contact with the side surface of the gate electrode.
After providing a spacer, the source / drain region
After that, the spacer was removed by RIE, and provided in a region on the channel side in contact with the source / drain diffusion layers.
Through the opening for the substrate coating including the side wall provided on the side surface of the gate electrode, in contact with the substrate surface by ion implantation, thermal diffusion, deposition / growth of semiconductor containing impurities, or plasma doping, and from the source / drain An extension structure in which a diffusion layer containing an impurity of the same conductivity type as that of the source / drain is extended in a shallow region .

In the method of manufacturing a field effect transistor according to the present invention, a spacer is formed in contact with a side surface of a gate electrode, and then a source / drain diffusion layer is formed outside these spacers. A resist pattern is provided on the upper part of the part away from the gate, the spacer is selectively etched using this resist as a mask, and the spacer is removed. Contact source and drain
The same conductivity type as the source / drain in the region shallower than the in
Extension to extend the diffusion layer containing impurities
It is characterized by forming a structure .

[0014]

According to the present invention, a diffusion layer is formed on a normal silicon substrate, and a germanium layer or a mixed crystal layer of silicon and germanium is selectively used only in an extension portion.

[0015] Germanium or silicon-germanium mixed crystals containing high-concentration impurities can be epitaxially grown at a low temperature of 500 ° C to 600 ° C where impurity diffusion does not occur on the silicon substrate. this is,
See, for example, Gotou et al., 1994 Extended Abstract of 1994 International Conference on Solid State Devices and Materials, p. 999 (K. Goto et.a.
l. , Ext. Abs. 1994 SSDM, p. 99
9). In the present invention, by forming the extension portion by epitaxial growth of germanium or silicon-germanium mixed crystal,
A high-concentration extension region is formed while suppressing impurity diffusion into the silicon substrate. Thus, even if the concentration of the extension portion is increased, the spread of the impurity in the silicon substrate does not increase, and the problem of the conventional extension structure can be solved. Further, since the source / drain diffusion layer has a normal structure formed on the silicon substrate outside the extension region, conventional techniques can be used for silicidation of the diffusion layer and formation of contact with the diffusion layer.

This is an effect brought about by selectively using germanium or a silicon-germanium mixed crystal only in the extension portion.

This structure can be formed by epitaxially growing germanium or a mixed crystal of germanium and silicon on a silicon substrate, ion-implanting impurities into the epitaxial layer, and performing heat treatment. Germanium can be recrystallized by a heat treatment of 300 to 700 degrees, and is lower than the temperature of 800 to 900 degrees required for silicon,
Even if the diffusion layer is silicided in advance, the influence on the silicidation is small. Therefore, the structure of the present invention can be formed at a lower temperature than the case where a diffusion layer is formed on a silicon substrate, so that impurities in the silicon substrate due to heat treatment for recrystallization after ion implantation can be obtained. Diffusion can be suppressed, and a shallow junction can be obtained.

Further, according to the present invention, the source / drain diffusion layer is formed in advance at a position away from the gate electrode, and thereafter, an extension region is provided in a region located between the source / drain diffusion layer and the gate electrode. . Thereby, it is possible to prevent the heat treatment for forming the gate / drain diffusion layers from expanding the impurity distribution in the extension region.

In the present invention, the extension region is formed by epitaxial growth of silicon into which impurities are introduced. Thereby, a steep impurity profile can be formed, and a shallow extension region with a high concentration can be formed.

The present invention is also effective for eliminating the floating effect of the SOIMOSFET on the substrate. SOIMOSFET
In, the carriers generated by impact ionization do not flow into the substrate, so that the minority carrier concentration in the SOI layer increases, the potential fluctuates, and the characteristics change. The generated carriers disappear by diffusion to the source or recombination at the source junction as shown in FIG. 27. However, by using germanium having a narrower band gap than silicon or a mixed crystal of germanium and silicon for the source electrode, the carrier diffusion is prevented. Lowering the potential barrier and increasing diffusion. Further, by using germanium or a mixed crystal of germanium and silicon having a band gap smaller than that of silicon in a region adjacent to the source junction, the concentration product of carriers can be increased and recombination can be increased (FIG. 28). When the junction is changed steeply as shown in FIG. 29, the carrier concentration increases due to discontinuity of the band at the junction, but when the mixed crystal ratio is changed smoothly,
As shown in FIG. 29, a region where holes are accumulated can be removed. These effects can prevent the accumulation of holes and reduce the substrate floating effect.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1 to 6 are schematic structural views showing the manufacturing steps of the first embodiment of the present invention. 2 × 10 ¹⁷ cm ⁻² ions of phosphorus are implanted into the silicon substrate 1 at 30 keV, and 85
A heat treatment is performed at 0 degrees for 10 minutes to activate the ion-implanted phosphorus. The surface of the silicon substrate 1 is thermally oxidized to 70 Å (hereinafter, Å is referred to as “A”).
Of the gate oxide film 2 is formed. Polysilicon 3 is deposited at 2000 A by the CVD method, and boron is implanted into the polysilicon 3 at 2 × 10 ¹⁵ cm ^{−2 at 15} keV, and 800
Heat treatment is performed for 10 minutes. Next, 1 on polysilicon 3
A first CVD oxide film 4 of 000 A is deposited. The polysilicon 3 and the first CVD oxide film 4 are patterned to a width of 0.2 μm by photolithography and RIE to form a gate electrode (FIG. 1). Next, 1500 A of a second CVD oxide film 5 is deposited by the LPCVD method, and this is etched back by RIE to form a side wall on the gate electrode. Boron 20 ke using the gate electrode and its side wall as a mask
After ion implantation at 3 × 10 ¹⁵ cm ^{−2 with} V, heat treatment is performed at 800 ° C. for 10 minutes to activate boron and form a source / drain diffusion layer 6 (FIG. 2).

A third CVD oxide film 7 is deposited to a thickness of 3000 A by the LPCVD method, and covers the gate electrode, the side wall, and the source / drain diffusion layer 6. Next, a pattern of the photoresist 8 is provided at a position where the diffusion layer exists by photolithography (FIG. 3). At this time, the end of the resist is located at the same position as the end of the source / drain diffusion layer 6 or outside thereof. Next, the second CVD oxide film 5 and the third CVD oxide film 7 are selectively etched with respect to the polysilicon 3 and removed by RIE. At this time, since the photoresist 8 and the polysilicon 3 serve as a mask for etching, the surface of the silicon substrate 1 is exposed only in the intermediate portion between the diffusion layer and the gate electrode. Next, after removing the photoresist 8, an HTO oxide film 9 of 150A is deposited by the HTO method, and etched back by RIE to form a side wall (FIG. 4). Next, the silicon substrate 1 is etched by 300 A by RIE (FIG. 5), and Ge doped with boron is selectively epitaxially grown on the etched region by CVD using GeH ₄ and B ₂ H ₆ , and the extension is performed. Area 10
Is formed (FIG. 6). Here, a mixed crystal of Si and Ge may be used instead of Ge. In the case of an n-channel FET, the extension region is doped with arsenic, phosphorus, antimony or the like instead of boron.

FIG. 7 shows an example in which the silicon substrate 1 is isotropically etched after providing the side wall of the HTO oxide film 9 in the first embodiment. The isotropic etching is performed by a gas phase reaction using chlorine or CF ₄ gas, a wet etching using a mixture of hydrofluoric acid, nitric acid, and acetic acid. Further, wet etching using an alkaline aqueous solution such as sodium hydroxide or hydrazine may be used.

In this case, the extension area 10
It goes around to the lower part of the gate electrode (FIG. 8).

FIG. 9 shows an example in which an LDD region 11 is provided in the first embodiment. Here, the LDD region 11 is
After patterning the gate electrode, boron is applied at 15 keV for 2
It is provided by ion implantation of × 10 ¹⁷ cm ⁻² .

FIG. 10 shows an example in which epitaxial silicon 12 is used for the extension region 10 in the first embodiment.

FIGS. 11 to 13 show that the second CVD oxide film 5 and the third CVD
After the oxide film 7 is selectively removed by etching with respect to the polysilicon 3 (FIG. 11), 1000 A of boron glass 13 is deposited by a CVD method (FIG. 12).
Perform a 5 second lamp anneal to extend region 1
0 is formed (FIG. 13). Further, the extension region 10 may be formed by ion implantation, plasma doping, or the like.

FIG. 14 shows that, in the first embodiment, germanium not doped with impurities is grown in place of germanium doped with impurities, and then boron is ion-implanted at 5 × 10 ¹³ cm ^-3 at 15 keV. 5 at 700 degrees
This is an example of heat treatment. Alternatively, use boron glass as CV
Deposited by D method or spin coating method.
Perform a partial heat treatment.

FIGS. 15 to 18 are schematic structural views showing a second embodiment of the present invention. Boron is applied to the surface of the silicon substrate 21 at 4 × 10 ¹⁷ cm ⁻² , 20 keV and 1 × 10
Ion implantation is performed at ¹⁸ cm ^-2 and 180 keV. 800 degrees 1
After the heat treatment for 0 minutes, the surface of the silicon
A thermal oxidation is performed to form a gate oxide film 22. 2000 A of polysilicon 23 is deposited by the CVD method, and phosphorus is thermally diffused therein. The polysilicon 23 is patterned to a width of 0.3 μm by photolithography and RIE to form a gate electrode. 3 × 10 ¹⁷ c phosphorus at 30 keV
m- ² ion implantation, heat treatment at 800 degrees for 5 minutes, LD
A D region 25 is formed. HT of 150A by HTO method
An O-oxide film 24 is deposited and etched back by RIE to form side walls (FIG. 15). At the time of this etch back, a region other than the related device, that is, a device isolation region,
The p-channel FET and the like are protected by a photoresist. Next, the silicon substrate 21 is vapor-
A etch. At this time, as in the first embodiment, R
Anisotropic etching by IE or other isotropic etching may be used (FIG. 16).

Subsequently, in the etched region, for example, Si ₄ Cl ₂ H ₂ , PH ₅ is used by a CVD method.
Phosphorus-doped Si is selectively grown epitaxially at 400 A to form extension regions 26 (FIG. 17).

Next, the CVD oxide film 27 is formed by the CVD method.
Is deposited at 1000 A and etched back by RIE to form a side wall on the gate electrode. Next, arsenic is ion-implanted at 5 × 10 ¹⁷ cm ^{−2 at} 70 keV, and 10% at 850 ° C.
A diffusion heat treatment is performed to form a diffusion layer 28 (FIG. 18).

FIGS. 19 to 22 are schematic structural views showing a third embodiment of the present invention. 40 on silicon substrate 41
Boron is implanted into a SOI substrate having a 1200A silicon layer 43 with a buried oxide film 42 of 00A at 3 × 10 ¹⁷ cm ⁻² at 30 keV and a heat treatment at 850 ° C. for 10 minutes to perform ion implantation. Activate element. The surface of the silicon layer 43 is thermally oxidized to form a gate oxide film 44 of 100A. 2000 A of polysilicon 45 is deposited by the CVD method, and a high concentration of phosphorus is diffused in the polysilicon. Next, a thickness of 1500 A is formed on the polysilicon 45.
A first CVD oxide film 46 is deposited. Polysilicon 45 and first CV by photolithography and RIE
The D oxide film 46 is patterned to a width of 0.2 μm to form a gate electrode. Next, the second CV is formed by LPCVD.
A 1000 Å D oxide film 47 is deposited, and this is etched back by RIE to form a sidewall on the gate electrode. Arsenic is 3 × 10 at 70 keV using the gate electrode and its side wall as a mask.
After ion implantation at ¹⁵ cm ⁻² , heat treatment is performed at 800 ° C. for 10 minutes to activate arsenic and form a source / drain diffusion layer 48.

A third CVD oxide film 49 is deposited at 3000 A by LPCVD to cover the gate electrode, the side walls, and the source / drain diffusion layers. Next, a pattern of the photoresist 50 is provided at a position where the diffusion layer exists by photolithography. At this time, the edge of the resist is
It is separated by 0.5 μm outward from the end of the drain diffusion layer 48 (FIG. 19). Next, the second CVD oxide film 4 is formed by RIE.
The seventh and third CVD oxide films 49 are selectively etched with respect to the polysilicon 45 and removed. At this time, the photoresist 50 and the polysilicon 45 serve as a mask for etching. Next, after removing the photoresist 7,
An HTO oxide film 51 of 150 A is deposited by the HTO method,
Etchback is performed by RIE to form side walls. Next, the silicon layer 43 is isotropically etched with chlorine gas at 600 A (FIG. 20).

In the etched region, a mixed crystal of silicon and germanium is epitaxially grown at 400 A, without doping impurities, while the proportion of germanium is gradually increased with growth to form a mixed crystal region 52. Next, growth is performed at 200 A while doping germanium with a high concentration of arsenic to form an extension region 53. A resist pattern 54 is provided so as to cover a portion of the extension region 53 that does not overlap with the diffusion layer 48 of the gate electrode. Then, 1 × 10 ¹⁵ cm ⁻² ions of phosphorus are implanted at 20 keV (FIG. 21), and a heat treatment is performed at 700 ° C. for 10 minutes to form a connection portion 55 with the diffusion layer into which the high concentration impurity is introduced (FIG. 21). 22). Further, the mixed crystal region 52 may be replaced with germanium. Further, the ratio of the mixed crystal may be sharply changed.

The introduction of impurities into germanium is as follows:
After the epitaxial growth, ion implantation, solid phase diffusion, plasma doping, or the like may be used.

In the above embodiment, the diffusion layer may be silicided before or after the extension portion is formed.

FIG. 23 is a schematic structural diagram showing a fourth embodiment in which the present invention is applied to an SOIMOSFET. In an SOI substrate having a 4000A thick buried oxide film 62 on a silicon substrate 61 and a 1000A thick SOI layer 69, a 100A thick gate oxide film 6
A gate electrode of n-type polysilicon 68 is formed on both sides of the gate electrode 7. 1 × 10 ¹⁸ boron is formed under the SOI layer 69.
A p-type region 66 with cm ⁻³ introduced is provided. Above the p-type region, the concentration of boron is 2 × 10 ¹⁷ cm ⁻³ . An n ⁺ -type diffusion layer 63 is provided at a position away from the gate electrode. Extension region 6 made of n ⁺ type germanium / silicon mixed crystal having a thickness of 500 A between diffusion layer 63 and the gate.
4 is provided. The mixed crystal ratio is 1: 1. From the end of the extension region 64, an inclined junction region 65 having a width of 500A in which the mixed crystal ratio of silicon and germanium is continuously changed from 1: 0 to 1: 1 is provided on the channel side. Boron is introduced into the inclined junction region at 2 × 10 ¹⁷ cm ⁻³ .

FIGS. 24 to 26 are schematic structural views showing a fifth embodiment of the present invention. Boron is ion-implanted into the surface of the silicon substrate 71 at 4 × 10 ¹⁷ cm ⁻² at 20 keV. After the heat treatment at 850 ° C. for 10 minutes, the silicon substrate 7
1 is thermally oxidized by 70 A to form a gate oxide film 72. 2000 A of polysilicon 73 is deposited by the CVD method, and phosphorus is thermally diffused therein. Next, by the CVD method,
A 3000 A CVD oxide film 74 is deposited, etched back by RIE, and a sidewall is formed on the gate electrode. Next, arsenic is ion-implanted at 5 × 10 ¹⁷ cm ^{−2 at} 70 keV and heat-treated at 850 ° C. for 10 minutes to form a diffusion layer 75 (FIG. 24). Next, the oxide film 74 is removed by RIE, and HT
An O-oxide film 76 is deposited at 100 A and etched back by RIE to form side walls.
OA, RIE or removal by vapor phase etching of chlorine or the like is performed, and n-type germanium is epitaxially grown at 200 A to form an extension region 77 (FIG. 2).
5).

For silicidation or contact formation, the germanium layer 77 on the diffusion layer 75 may be removed.

The extension region 77 may be formed by ion implantation, solid phase diffusion, plasma doping or the like without using epitaxial growth. in this case,
The HTO oxide film 76 is not required.

Before depositing oxide film 74, nitride film 76 may be deposited at 100A (FIG. 26), and oxide film 74 may be removed by wet etching. In this case, the HTO oxide film 76 is not formed.

[0043]

According to the present invention, by forming the extension region by epitaxial growth of germanium or silicon-germanium mixed crystal, it is possible to form the extension region with high concentration while suppressing impurity diffusion into the silicon substrate. Thus, even if the impurity concentration is increased to reduce the resistance of the extension portion, the spread of the impurity in the silicon substrate does not increase.
Further, since the source / drain diffusion layer has a normal structure formed on the silicon substrate outside the extension region, conventional techniques can be used for silicidation of the diffusion layer and formation of contact with the diffusion layer.

Further, the present invention is formed by epitaxially growing germanium or a mixed crystal of germanium and silicon on a silicon substrate, ion-implanting impurities into the epitaxial layer, and performing heat treatment. Germanium can be recrystallized by heat treatment at 300-700 ° C.
Than 900 degrees Celsius, and can be formed at a lower temperature than the case where a diffusion layer is formed on a silicon substrate, so that it can be formed into a silicon substrate due to heat treatment for recrystallization after ion implantation. Can be suppressed, and a shallow junction can be obtained.

In the present invention, the source / drain diffusion layer is formed in advance at a position away from the gate electrode, and thereafter, an extension region is provided in a region located between the source / drain diffusion layer and the gate electrode. Thereby, it is possible to prevent the heat treatment for forming the source / drain diffusion layers from expanding the impurity distribution in the extension region.

According to the present invention, the extension region is formed by epitaxial growth of silicon into which impurities are introduced. Thereby, a steep impurity profile can be formed, and a shallow extension region with a high concentration can be formed.

When the silicon substrate is isotropically etched, the extension region extends to below the gate electrode. Therefore, the extension region extends between the channel formed under the gate electrode and the extension region. It is possible to eliminate the parasitic resistance caused by the offset region, which is formed when the impurity diffusion into the semiconductor substrate is extremely small.

The present invention is also effective for eliminating the floating effect of the SOIMOSFET on the substrate.

[Brief description of the drawings]

FIG. 1 is a schematic structural view showing a first embodiment of the present invention.

FIG. 2 is a schematic structural view showing a first embodiment of the present invention.

FIG. 3 is a schematic structural view showing a first embodiment of the present invention.

FIG. 4 is a schematic structural view showing a first embodiment of the present invention.

FIG. 5 is a schematic structural view showing a first embodiment of the present invention.

FIG. 6 is a schematic structural view showing a first embodiment of the present invention.

FIG. 7 is a schematic structural view showing a first embodiment of the present invention.

FIG. 8 is a schematic structural view showing a first embodiment of the present invention.

FIG. 9 is a schematic structural view showing a first embodiment of the present invention.

FIG. 10 is a schematic structural view showing a first embodiment of the present invention.

FIG. 11 is a schematic structural view showing a first embodiment of the present invention.

FIG. 12 is a schematic structural view showing a first embodiment of the present invention.

FIG. 13 is a schematic structural view showing a first embodiment of the present invention.

FIG. 14 is a schematic structural view showing a first embodiment of the present invention.

FIG. 15 is a schematic structural view showing a second embodiment of the present invention.

FIG. 16 is a schematic structural view showing a second embodiment of the present invention.

FIG. 17 is a schematic structural view showing a second embodiment of the present invention.

FIG. 18 is a schematic structural view showing a second embodiment of the present invention.

FIG. 19 is a schematic structural view showing a third embodiment of the present invention.

FIG. 20 is a schematic structural view showing a third embodiment of the present invention.

FIG. 21 is a schematic structural view showing a third embodiment of the present invention.

FIG. 22 is a schematic structural view showing a third embodiment of the present invention.

FIG. 23 is a schematic structural view showing a fourth embodiment of the present invention.

FIG. 24 is a schematic structural view showing a fifth embodiment of the present invention.

FIG. 25 is a schematic structural view showing a fifth embodiment of the present invention.

FIG. 26 is a schematic structural view showing a fifth embodiment of the present invention.

FIG. 27 is a diagram illustrating an effect when the present invention is applied to an SOIMOSFET.

FIG. 28 is a diagram illustrating an effect when the present invention is applied to an SOIMOSFET.

FIG. 29 is a diagram illustrating an effect when the present invention is applied to an SOIMOSFET.

FIG. 30 is a schematic structural view showing a conventional example.

FIG. 31 is a schematic structural view showing a conventional example.

FIG. 32 is a schematic structural view showing a conventional example.

FIG. 33 is a schematic structural view showing a conventional example.

[Explanation of symbols]

1,21,41,61,71,101,111,131
Silicon substrate 2, 22, 44, 67, 72, 107, 117 Gate oxide film 3, 23, 45, 68, 73, 106, 116, 13
4,147 polysilicon 4,5,7,27,46,47,49,74,105,
115 CVD oxide film 6 Source / drain diffusion layer 8,50 Photoresist 9,24,51,76 HTO oxide film 10,26,53,64,77,103,113 Extension region 11,25,143 LDD region 12 Epitaxial silicon 13 Boron glass 28, 48, 63, 75 Diffusion layer 42, 62, 118, 141 Buried oxide film 43 Silicon layer 52 Mixed crystal region 54 Resist pattern 55 Connection with diffusion layer 65 Inclined junction region 66 P-type region 69, 119 SOI layer 102 p ⁺ diffusion layer 104, 114 titanium silicide 112 n ⁺ diffusion layer 120 p-type impurity region 132 epitaxial silicon germanium layer 133, 146 oxide film 142 source region 144 channel region 145 drain region

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/78 H01L 21/336 H01L 29/786

Claims (10)

(57) [Claims] 1. A diffusion layer containing an impurity of the same conductivity type as that of a source / drain is extended from a source / drain diffusion layer to a channel side in a region in contact with a substrate surface and shallower than the source / drain. Field-effect transistor having an extended extension structure, wherein the source / drain extensions, which are extended diffusion layers, are formed of germanium or a mixed crystal of silicon and germanium. Transistor. 2. A method for manufacturing a field-effect transistor according to claim 1, wherein the source / drain extension is formed by epitaxially growing a germanium layer containing impurities or a mixed crystal of silicon and germanium containing impurities. A method for manufacturing a field-effect transistor. 3. A method for manufacturing a field-effect transistor according to claim 1, wherein a germanium layer or a mixed crystal layer of silicon and germanium is epitaxially grown on a substrate surface, and then a source is introduced by introducing impurities into the epitaxial layer. -A method for manufacturing a field effect transistor, comprising forming a drain extension. 4. A method according to claim 1, further comprising: forming a source / drain region after providing a spacer in contact with a side surface of the gate electrode; removing the spacer from the source / drain diffusion layer toward the channel side; An epitaxial silicon layer is formed by epitaxially growing silicon containing impurities in a region shallower than the drain region, and the epitaxial silicon layer is a region in which a diffusion layer containing impurities of the same conductivity type as the source and drain is extended. A method for manufacturing a field-effect transistor, comprising forming an extension region. 5. A channel-side region in contact with a source / drain diffusion layer after a spacer made of a CVD oxide film is provided in contact with a side surface of a gate electrode, a source / drain region is formed, and then the spacer is removed by RIE. Provided in
Ion implantation, thermal diffusion, epitaxy through openings in the substrate coating, including sidewalls on the sides of the gate electrode
Silicon or germanium containing impurities from silicon growth
From silicon or a mixed crystal of silicon and germanium
Formation of a semiconductor or plasma doping,
Manufacturing a field effect transistor characterized by forming an extension structure in which a diffusion layer containing an impurity of the same conductivity type as the source / drain is extended in a region in contact with the substrate surface and shallower than the source / drain. Method. 6. After forming spacers in contact with the side surfaces of the gate electrode, a source / drain diffusion layer is formed outside these, and a resist pattern is provided at least on a portion of the diffusion layer remote from the channel, Using the resist as a mask, the spacer is selectively etched to remove the spacer, and then a side wall is provided on the side of the gate. A method for manufacturing a field-effect transistor, comprising: forming an extension structure in a shallow region where a diffusion layer containing an impurity of the same conductivity type as a source / drain is extended. 7. After forming a source / drain region, a semiconductor is formed in an opening for a substrate coating including an insulating film side wall provided on a side surface of a gate electrode provided in a region on a channel side in contact with a source / drain diffusion layer. Etching the substrate, followed by silicon containing impurities of the same conductivity type as the diffusion layer
Or germanium or a mixture of silicon and germanium
Selective epitaxial semiconductor of either
A method for manufacturing a field effect transistor, comprising forming a source / drain extension in which a diffusion layer is extended at a position in contact with a surface and shallower than a source / drain region by growing . 8. After the source / drain regions are formed, the semiconductor is formed in an opening for a substrate coating including an insulating film side wall provided on a side surface of the gate electrode provided in a channel side region in contact with the source / drain diffusion layer. The substrate is etched so that the region to be etched reaches the lower portion of the interface between the side wall and the gate electrode, or reaches the gate electrode side from the interface, and then contains impurities of the same conductivity type as the diffusion layer.
Silicon or germanium or silicon and germanium
Selective epitaxy for semiconductors consisting of
It grows in contact with the surface and the source
A method for manufacturing a field effect transistor, comprising: forming a source / drain extension in which a diffusion layer is extended at a position shallower than a drain region. 9. On the semiconductor surface on both sides of the gate electrode,
After etching the semiconductor substrate, silicon containing impurities is epitaxially grown, spacers are provided on the epitaxial silicon layer on both sides of the gate electrode, and source / drain regions deeper than the epitaxial silicon layer are formed.
An extension region in which a diffusion layer containing an impurity of the same conductivity type as the source / drain is formed by extending the epitaxial silicon layer formed at a certain distance from the gate electrode using the gate electrode and the spacer as a mask. A method for manufacturing a field-effect transistor. 10. On the semiconductor surface on both sides of the gate electrode, the surface of the substrate is etched, and silicon containing impurities is epitaxially grown in a recess formed by the etching, and then a spacer is formed on the epitaxial silicon layer on both sides of the gate electrode. The source / drain region deeper than the epitaxial silicon layer is formed at a certain distance from the gate electrode using the gate electrode and the spacer as a mask, and the epitaxial silicon layer has the same conductivity type as the source / drain. A method for manufacturing a field-effect transistor, comprising forming an extension region, which is a region in which a diffusion layer containing an impurity is extended.