WO2024053401A1 - Light detection apparatus, digital device, and method for producing light detection apparatus - Google Patents

Light detection apparatus, digital device, and method for producing light detection apparatus Download PDF

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Publication number
WO2024053401A1
WO2024053401A1 PCT/JP2023/030367 JP2023030367W WO2024053401A1 WO 2024053401 A1 WO2024053401 A1 WO 2024053401A1 JP 2023030367 W JP2023030367 W JP 2023030367W WO 2024053401 A1 WO2024053401 A1 WO 2024053401A1
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type
layer
epitaxial growth
photoelectric conversion
trench
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PCT/JP2023/030367
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French (fr)
Japanese (ja)
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慎一 吉田
尚人 北條
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2024053401A1 publication Critical patent/WO2024053401A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors

Definitions

  • the present disclosure relates to a photodetection device, an electronic device, and a method of manufacturing the photodetection device.
  • a photodetection device has been proposed that has a trench portion between photoelectric conversion portions and a P-type semiconductor layer formed by epitaxial growth is disposed within the trench portion (see, for example, Patent Document 1).
  • the P-type semiconductor layer functions as a hole pinning layer to suppress the generation of dark current on the sidewall surface of the trench portion.
  • An object of the present disclosure is to provide a photodetection device, an electronic device, and a method for manufacturing a photodetection device that can improve the saturation charge amount Qs of a photoelectric conversion unit.
  • a photodetecting device of the present disclosure includes: (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed; (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate; (c) the photoelectric conversion section includes a semiconductor layer covering a side wall surface of the trench section; and an element isolation section having a functional layer disposed in a space inside the trench section covered with the semiconductor layer; It has an N-type semiconductor region in the contacting region, (d) the semiconductor layer has a P-type impurity concentration of 1e16/cm 3 or less, and (e) the functional layer has holes on the functional layer side of the semiconductor layer.
  • the gist is that it is a layer that induces
  • Another photodetection device of the present disclosure includes (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed, (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate, and a trench section disposed within the trench section. and (c) the photoelectric conversion section has an N-type semiconductor region in a region in contact with the P-type solid-phase diffusion layer. (d) The P-type solid phase diffusion layer has an N-type impurity concentration of 1e16/cm 3 or less.
  • Another photodetection device of the present disclosure includes (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed, (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate, and a trench section disposed within the trench section. , an element isolation section having an N-type epitaxial growth layer covering a side wall surface of the trench portion, and a P-type epitaxial growth layer disposed in a space inside the trench portion covered with the N-type epitaxial growth layer and in contact with the N-type epitaxial growth layer.
  • the N-type epitaxial growth layer has a P-type impurity concentration of 1e16/cm 3 or less, and (d) The P-type epitaxial growth layer has an N-type impurity concentration of 1e16/cm 3 or less. do.
  • An electronic device of the present disclosure includes (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed, (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate, and a trench section disposed within the trench section. (c) a photoelectric conversion section is provided in a region in contact with the semiconductor layer; It has an N-type semiconductor region, (d) the semiconductor layer has a P-type impurity concentration of 1e16/cm 3 or less, and (e) the functional layer is a layer that induces holes on the functional layer side of the semiconductor layer.
  • the gist is to provide a photodetecting device that is.
  • Another electronic device of the present disclosure includes (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed, (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate, and a trench section disposed within the trench section. (c) the photoelectric conversion section has an N-type semiconductor region in a region in contact with the P-type solid-phase diffusion layer; , (d) The P-type solid phase diffusion layer is provided with a photodetector having an N-type impurity concentration of 1e16/cm 3 or less.
  • Another electronic device of the present disclosure includes (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed, (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate, and a trench section disposed within the trench section; an element isolation section having an N-type epitaxial growth layer covering a side wall surface of the trench portion, and a P-type epitaxial growth layer disposed in a space inside the trench portion covered with the N-type epitaxial growth layer and in contact with the N-type epitaxial growth layer; (c) The N-type epitaxial growth layer has a P-type impurity concentration of 1e16/cm 3 or less, and (d) The P-type epitaxial growth layer includes a photodetector having an N-type impurity concentration of 1e16/cm 3 or less.
  • the gist is that.
  • a method for manufacturing a photodetection device includes (a) forming a trench portion in a semiconductor substrate; and (b) forming an epitaxial growth layer with an impurity concentration of 1e16/cm 3 or less on the side wall surface of the trench portion by epitaxial growth. and (c) a step of doping the epitaxial growth layer with a P-type impurity from within the trench portion by solid-phase diffusion.
  • Another method of manufacturing a photodetecting device includes (a) forming a trench in a semiconductor substrate, and (b) epitaxial growth while adding N-type impurities to form a P-type on the side wall surface of the trench.
  • N is formed on the center side in the trench width direction of the N-type epitaxial growth layer.
  • the method includes the step of forming a P-type epitaxial growth layer having a type impurity concentration of 1e16/cm 3 or less.
  • FIG. 1 is a diagram showing the overall configuration of a solid-state imaging device according to a first embodiment.
  • 2 is a diagram illustrating a cross-sectional configuration of the solid-state imaging device taken along line AA in FIG. 1.
  • FIG. 3 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region B in FIG. 2 is enlarged.
  • 4 is a diagram showing the distribution of N-type impurity concentration at the position of line CC in FIG. 3.
  • FIG. FIG. 2 is a diagram showing a cross-sectional configuration of a solid-state imaging device when the semiconductor layer is of P type. It is a figure showing the manufacturing method of a solid-state imaging device. It is a figure showing the manufacturing method of a solid-state imaging device.
  • FIG. 3 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a second embodiment.
  • 9 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region D in FIG. 8 is enlarged.
  • FIG. FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification.
  • 11 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region E in FIG. 10 is enlarged.
  • FIG. FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a third embodiment.
  • 13 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region F in FIG. 12 is enlarged.
  • FIG. 3 is a diagram showing potential distribution.
  • FIG. 2 is a diagram showing a cross-sectional configuration of a solid-state imaging device having a P-type semiconductor region.
  • FIG. 3 is a diagram showing potential distribution.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method
  • FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification.
  • FIG. 20 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region G in FIG. 19 is enlarged.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification.
  • 24 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region H in FIG. 23 is enlarged.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification. 28 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region I in FIG. 27 is enlarged.
  • FIG. FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a fourth embodiment.
  • 32 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region J in FIG. 31 is enlarged.
  • FIG. FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram showing the overall configuration of an electronic device according to a fifth embodiment.
  • FIGS. 1 to 35 An example of a photodetection device, an electronic device, and a method of manufacturing the photodetection device according to an embodiment of the present disclosure will be described below with reference to FIGS. 1 to 35. Embodiments of the present disclosure will be described in the following order. Note that the present disclosure is not limited to the following examples. Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.
  • First embodiment Solid-state imaging device 1-1 Overall configuration of solid-state imaging device 1-2 Configuration of main parts 1-3 Manufacturing method of solid-state imaging device 1-4 Modification example 2.
  • Second embodiment Solid-state imaging device 2-1 Configuration of main parts 2-2 Modification example 3.
  • Third embodiment Solid-state imaging device 3-1 Configuration of main parts 3-2 Manufacturing method of solid-state imaging device 3-3 Modification example 4.
  • Fourth embodiment Solid-state imaging device 4-1 Configuration of main parts 4-2 Manufacturing method of solid-state imaging device 4-3 Modification example 5.
  • Fifth embodiment Application example to electronic equipment
  • FIG. 1 is a diagram showing the overall configuration of a solid-state imaging device 1 according to the first embodiment.
  • the solid-state imaging device 1 in FIG. 1 is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor.
  • CMOS Complementary Metal Oxide Semiconductor
  • the solid-state imaging device 1 (1002) captures image light (incident light) from a subject through a lens group 1001, and calculates the amount of incident light formed on the imaging surface in pixel units.
  • the solid-state imaging device 1 includes a pixel region 2, a vertical drive circuit 3, a column signal processing circuit 4, a horizontal drive circuit 5, an output circuit 6, and a control circuit 7. .
  • the pixel area 2 has a plurality of pixels 8 arranged in a two-dimensional array.
  • the pixel 8 includes the photoelectric conversion section 21 shown in FIG. 2 and a plurality of pixel transistors. Examples of the plurality of pixel transistors include four MOS transistors including a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor.
  • the vertical drive circuit 3 is configured by, for example, a shift register, selects a desired pixel drive wiring 9, supplies pulses for driving the pixels 8 to the selected pixel drive wiring 9, and drives each pixel 8 in rows.
  • the vertical drive circuit 3 sequentially selectively scans each pixel 8 in the pixel region 2 in the vertical direction row by row, and generates a pixel signal based on the signal charge generated in the photoelectric conversion section 21 of each pixel 8 according to the amount of light received. , are supplied to the column signal processing circuit 4 through the vertical signal line 10.
  • the column signal processing circuit 4 is arranged, for example, for each column of pixels 8, and performs signal processing such as noise removal on the signals output from the pixels 8 of one row for each pixel column.
  • the column signal processing circuit 4 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog Digital) conversion to remove fixed pattern noise specific to pixels.
  • the horizontal drive circuit 5 is configured by, for example, a shift register, and sequentially outputs horizontal scanning pulses to the column signal processing circuits 4 to select each of the column signal processing circuits 4 in turn, and selects each of the column signal processing circuits 4 from each of the column signal processing circuits 4 in turn.
  • the pixel signal subjected to signal processing is output to the horizontal signal line 11.
  • the output circuit 6 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 4 through the horizontal signal line 11, and outputs the processed pixel signals.
  • signal processing for example, buffering, black level adjustment, column variation correction, various digital signal processing, etc. can be used.
  • the control circuit 7 generates clock signals and control signals that serve as operating standards for the vertical drive circuit 3, column signal processing circuit 4, horizontal drive circuit 5, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. generate. Then, the control circuit 7 outputs the generated clock signal and control signal to the vertical drive circuit 3, column signal processing circuit 4, horizontal drive circuit 5, and the like.
  • FIG. 2 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 taken along line AA in FIG.
  • FIG. 3 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 when region B in FIG. 2 is enlarged.
  • the solid-state imaging device 1 includes a semiconductor substrate 12, a fixed charge film 13 (“functional layer” in a broad sense), an insulating film 14, a light shielding film 15, and a planarization film 16 stacked in this order.
  • a light-receiving layer 17 is disposed.
  • a color filter layer 18 and a microlens array 19 are arranged in this order.
  • a wiring layer 20 is arranged on the surface of the light-receiving layer 17 on the semiconductor substrate 12 side (hereinafter also referred to as "surface S2").
  • the semiconductor substrate 12 is made of silicon (Si), for example.
  • a photoelectric conversion section 21 is formed in each region of each pixel 8 on the semiconductor substrate 12 . That is, a plurality of photoelectric conversion units 21 are arranged in a two-dimensional array on the semiconductor substrate 12.
  • the photoelectric conversion unit 21 includes a P-type semiconductor region 22 containing a P-type impurity, and a P-type semiconductor region 22 containing a P-type impurity on the light incident surface (hereinafter also referred to as "back surface S3") side and the front surface S2 side of the semiconductor substrate 12, respectively.
  • a P-type semiconductor region 24 is formed.
  • an N-type semiconductor region 23 that is continuous in the thickness direction of the semiconductor substrate 12 is in contact with the semiconductor layer 27 surrounding the photoelectric conversion section 21. is formed. That is, the photoelectric conversion section 21 has an N-type semiconductor region 23 in a region in contact with the semiconductor layer 27 .
  • the semiconductor layer 27 is a layer that covers the side wall surface S4 of the trench section 25 formed between the photoelectric conversion sections 21.
  • boron (B) can be used as the P-type impurity.
  • the N-type impurity for example, phosphorus (P) or arsenic (As) can be used.
  • the photoelectric conversion section 21 constitutes a photodiode by a PN junction between a junction surface between the P-type semiconductor region 22 and the N-type semiconductor region 23 and a junction surface between the P-type semiconductor region 24 and the N-type semiconductor region 23. Then, photoelectric conversion is performed to generate charges according to the amount of received light. Further, the photoelectric conversion unit 21 accumulates charges generated by photoelectric conversion in the N-type semiconductor region 23 .
  • the N-type impurity concentration is higher on the trench portion 25 side than on the central portion side of the photoelectric conversion section 21, and the N-type impurity concentration is higher on the trench portion 25 (semiconductor The N-type impurity concentration has a peak at the interface between the layer 27) and the N-type semiconductor region 23.
  • the N-type impurity concentration near the interface can be increased, and the amount of charge that can be accumulated in the photoelectric conversion section 21 (ie, the saturated charge amount Qs) can be increased.
  • the higher the N-type impurity concentration the darker the color. Further, in FIG.
  • FIG. 4 is a diagram showing the distribution of N-type impurity concentration at the position of line CC in FIG. Further, the N-type semiconductor region 23 has a constant N-type impurity concentration in the thickness direction of the semiconductor substrate 12. Therefore, the peak of the N-type impurity concentration at the interface between the trench portion 25 (semiconductor layer 27) and the N-type semiconductor region 23 is continuous in the thickness direction of the semiconductor substrate 12.
  • the amount of charge that can be stored on the back surface S3 side of the semiconductor substrate 12 and the amount of charge that can be stored on the front surface S2 side can be increased, and the saturated charge amount Qs can be further increased.
  • the impurity concentration distribution of the N-type semiconductor region 23 and the semiconductor layer 27 shown in FIG. 4 can be obtained by, for example, analyzing with Nano-SIMS (Secondary Ion Mass Spectrometry).
  • a trench portion 25 is formed in the semiconductor substrate 12 between adjacent photoelectric conversion portions 21 .
  • the trench portion 25 is formed along the side surface of the photoelectric conversion portion 21 from the front surface S2 to the back surface S3 of the semiconductor substrate 12. That is, the trench portions 25 are formed in a grid pattern on the semiconductor substrate 12 so as to surround each of the photoelectric conversion portions 21 .
  • the trench portion 25 forms an element isolation portion 26 together with the semiconductor layer 27, the fixed charge film 13, and the insulating film 14.
  • a semiconductor layer 27 is arranged to cover the side wall surface S4 of the trench portion 25. The semiconductor layer 27 is formed to surround each of the photoelectric conversion parts 21 when viewed from the thickness direction of the semiconductor substrate 12.
  • the semiconductor layer 27 for example, a non-doped semiconductor layer formed at a different timing from the semiconductor substrate 12, such as a non-doped epitaxial growth layer, can be used.
  • the epitaxial growth layer is a semiconductor layer formed by epitaxially growing a semiconductor crystal.
  • the P-type impurity concentration of the semiconductor layer 27 is 1e16/cm 3 or less (low value).
  • the semiconductor layer 27 can suppress the diffusion of P-type impurities from the semiconductor layer 27 into the photoelectric conversion section 21, as shown in FIG. Erosion of the N-type semiconductor region 23 can be suppressed. Therefore, a decrease in the saturation charge amount Qs of the photoelectric conversion section 21 can be suppressed. That is, the saturation charge amount Qs of the photoelectric conversion section 21 can be improved.
  • the N-type of the semiconductor layer 27 is The impurity concentration was 1e16/cm 3 or less.
  • a semiconductor layer for example, an epitaxially grown layer
  • an impurity concentration of 1e16/cm 3 or less is formed as the semiconductor layer 27. Therefore, almost all of the N-type impurities in the semiconductor layer 27 are diffused from the N-type semiconductor region 23.
  • the N-type impurity concentration (1e16/cm 3 or less) of the semiconductor layer 27 is achieved by adjusting the thickness of the N-type semiconductor region 23 and the semiconductor layer 27, etc.
  • the layer thickness (film thickness) of the semiconductor layer 27 for example, 10 nm or more can be adopted.
  • the hole inducing layer 27a can be formed by the fixed charge film 13 on the inner side surface S5 side of the semiconductor layer 27, as described later.
  • the material of the semiconductor layer 27 for example, the same material as the semiconductor substrate 12 (for example, silicon (Si)) can be used.
  • the inner side surface S5 of the semiconductor layer 27 is covered with the fixed charge film 13. That is, the fixed charge film 13 is arranged in a space inside the trench portion 25 covered with the semiconductor layer 27, along the inner side surface S5 of the semiconductor layer 27.
  • a material for the fixed charge film 13 for example, a material that can be deposited on the semiconductor layer 27 to generate negative fixed charges and realize pinning can be used.
  • a high refractive index material film or a high dielectric constant film having a negative fixed charge can be used.
  • oxides or nitrides Al 2 O 3 , HfO 2 , Ta 2 O 5 , etc.
  • a hole inducing layer 27a (also referred to as a "hole inducing layer 27a") is formed, and pinning of the sidewalls of the trench portion 25 is realized.
  • the fixed charge film 13 is a layer that induces holes on the fixed charge film 13 side (the inner side surface S5 side) of the semiconductor layer 27.
  • an insulating film 14 is embedded in a groove-shaped space inside the trench portion 25 covered with the semiconductor layer 27 and the fixed charge film 13.
  • the material of the insulating film 14 for example, silicon oxide (SiO 2 ) or silicon nitride (SiN) can be used.
  • the insulating film 14 prevents the occurrence of electrical color mixing between adjacent photoelectric conversion units 21 due to crosstalk in which charges photoelectrically converted in one photoelectric conversion unit 21 move to the other photoelectric conversion unit 21. suppressed.
  • the fixed charge film 13 covers the bottom surface of the trench portion 25 and the back surface S3 of the semiconductor substrate 12 together with the semiconductor layer 27. Further, the insulating film 14 not only fills the trench portion 25 but also covers the light incident surface (hereinafter also referred to as "back surface S7") of the fixed charge film 13.
  • the light shielding film 15 is disposed on the light incident surface (hereinafter also referred to as "back surface S8") side of the insulating film 14, and is formed so as to open the light incident surface of each of the photoelectric conversion sections 21.
  • the planarization film 16 is disposed on the back surface S8 side of the insulating film 14, and continuously covers the back surface S8 and the light shielding film 15 so that the back surface S1 side of the light-receiving layer 17 becomes a flat surface.
  • the material of the insulating film 14 for example, silicon oxide (SiO 2 ) or silicon nitride (SiN) can be used.
  • the color filter layer 18 is formed on the back surface S1 side of the planarizing film 16, and includes a plurality of color filters 28 arranged corresponding to the photoelectric conversion sections 21. That is, one color filter 28 is formed for one photoelectric conversion section 21.
  • the plurality of color filters 28 include a plurality of types of color filters that transmit light of a predetermined wavelength included in the light condensed by the microlens 29. As a result, each of the color filters 28 transmits light of a predetermined wavelength corresponding to the color filter 28, and the transmitted light is incident on the photoelectric conversion unit 21.
  • the microlens array 19 is formed on the back surface S9 side (light receiving surface side) of the color filter layer 18, and has a plurality of microlenses 29 arranged corresponding to the photoelectric conversion sections 21. That is, one microlens 29 is formed for one photoelectric conversion section 21. Thereby, each of the microlenses 29 collects image light (incident light) from the subject, and causes the collected incident light to enter the corresponding photoelectric conversion unit 21 via the color filter 28.
  • the wiring layer 20 is arranged on the surface S2 side of the semiconductor substrate 12.
  • the wiring layer 20 includes an interlayer insulating film and wiring (not shown) stacked in multiple layers with the interlayer insulating film interposed therebetween.
  • the wiring layer 20 drives the pixel transistor of each pixel 8 via multiple layers of wiring.
  • the solid-state imaging device 1 having the above configuration, light is irradiated from the back surface S3 side of the semiconductor substrate 12, the irradiated light is transmitted through the microlens 29 and the color filter 28, and the transmitted light is photoelectrically converted by the photoelectric conversion unit 21.
  • the signal charge is generated by conversion.
  • the generated signal charge is then output as a pixel signal from the vertical signal line 10 of FIG. 1 formed by the wiring of the wiring layer 20.
  • the hole inducing layer 27a is formed on the fixed charge film 13 side of the semiconductor layer 27 by the fixed charge film 13, and pinning of the side wall of the trench portion 25 is realized. This pinning suppresses dark current generated on the sidewalls of the trench portion 25.
  • FIG. 5 illustrates a case where the width of the N-type semiconductor region 23 is reduced from W 1 to W 2 due to erosion by P-type impurities. Therefore, there was a possibility that the saturation charge amount Qs of the photoelectric conversion section 21 would decrease.
  • the higher the P-type impurity concentration the darker the color.
  • a curve indicating the P-type impurity concentration is shown by a broken line superimposed on the P+-type semiconductor layer 27.
  • the pixels 8 are made smaller.
  • the pixel 8 is miniaturized in the solid-state imaging device 1 shown in FIG. 23 also occurs, which may make it difficult to secure the necessary saturation charge amount Qs.
  • the semiconductor layer 27 is configured to have a P-type impurity concentration of 1e16/cm 3 or less. Therefore, diffusion of P-type impurities from the semiconductor layer 27 into the photoelectric conversion section 21 can be suppressed, and erosion of the N-type semiconductor region 23 within the photoelectric conversion section 21 can be suppressed.
  • FIG. 3 illustrates a case where the width of the N-type semiconductor region 23 is maintained at W 1 without being corroded by P-type impurities. Therefore, it is possible to suppress a decrease in the amount of charge that can be accumulated in the photoelectric conversion section 21 (the amount of saturated charge Qs).
  • the saturation charge amount Qs of the photoelectric conversion section 21 can be improved. Furthermore, even when the pixels 8 are miniaturized, the N-type semiconductor region 23 does not decrease due to the diffusion of P-type impurities, so the necessary saturation charge amount Qs can be secured, and the solid-state imaging device 1 can have a large number of pixels. can be realized relatively easily.
  • a method for manufacturing the solid-state imaging device 1 according to the first embodiment will be described.
  • a mask 30 having an opening at a position where the trench portion 25 is to be formed is formed on the surface S2 of the semiconductor substrate 12.
  • anisotropic dry etching is performed through the mask 30 to form the trench portion 25.
  • the processing damage during the formation of the trench portion 25 can be recovered using the heat treatment performed in the later process. white spots and dark current can be suppressed.
  • the N-type semiconductor region 23 of the photoelectric conversion section 21 is formed on the side wall surface S4 of the trench section 25 using a conformal doping technique, as shown in FIG. 6B.
  • the N-type semiconductor region 23 can be formed by a process of introducing N-type impurities from the inside of the trench portion 25.
  • a method for doping with N-type impurities for example, solid phase diffusion, plasma doping, and ion implantation can be used. Note that in FIG. 6B, only the portions of the N-type semiconductor region 23 shown in dark colors in FIG. 3 (only the portions where the N-type impurity concentration is high) are expressed with dots. Further, similar expressions were used in FIGS. 6C to 6H.
  • a semiconductor crystal for example, silicon (Si)
  • Si silicon
  • the trench portion 25 is grown so as to cover the side wall surface S4 and the bottom surface of the trench portion 25.
  • a semiconductor layer 27 is formed inside.
  • an epitaxially grown layer having an impurity concentration of 1e16/cm 3 or less is formed.
  • silicon oxide (SiO) 31 and doped polysilicon 32 are embedded in this order into the space inside the trench portion 25 covered with the semiconductor layer 27. Subsequently, as shown in FIG.
  • a wiring layer 20 is formed on the surface S2 side of the semiconductor substrate 12. Subsequently, after bonding the sensor substrate including the semiconductor substrate 12 and the wiring layer 20 and the logic substrate (not shown), the semiconductor substrate 12 is bonded to the back surface S3 side as shown in FIG. 6F using CMP technology. Polish it to make it thinner. Subsequently, as shown in FIG. 6G, silicon oxide 31 and doped polysilicon 32 are removed from within trench portion 25. Subsequently, as shown in FIG. 6H, the fixed charge film 13 and the insulating film 14 are formed in this order within the trench portion 25. Subsequently, as shown in FIG.
  • a light shielding film 15, a planarization film 16, a color filter layer 18, and a microlens array 19 are formed in this order on the back surface S8 of the insulating film 14. In this way, the solid-state imaging device 1 according to the first embodiment is manufactured.
  • the semiconductor layer 37 is formed in a process (FEOL process) before joining the sensor substrate and the logic board or thinning the semiconductor substrate 12.
  • FEOL process a process
  • it may be formed after the FEOL process.
  • silicon oxide (SiO) 31 and doped polysilicon 32 are placed in the space inside the trench portion 25 in this order. Embed.
  • a wiring layer 20 is formed on the surface S2 side of the semiconductor substrate 12.
  • the back surface of the semiconductor substrate 12 is polished using CMP (Chemical Mechanical Polishing) technology, as shown in FIG. 7C. Polish from the S3 side to make it thinner.
  • CMP Chemical Mechanical Polishing
  • silicon oxide (SiO) 31 and doped polysilicon 32 are removed from inside the trench portion 25.
  • a semiconductor crystal for example, silicon (Si)
  • Si silicon
  • FIG. 6G a semiconductor crystal (for example, silicon (Si)) is epitaxially grown on the side wall surface S4 of the trench portion 25, and the trench portion 25 is grown so as to cover the side wall surface S4 and the bottom surface of the trench portion 25.
  • a semiconductor layer 27 is formed inside.
  • the fixed charge film 13 and the insulating film 14 are formed in this order within the trench portion 25.
  • a light shielding film 15, a planarization film 16, a color filter layer 18, and a microlens array 19 are formed in this order on the back surface S8 of the insulating film 14.
  • FIG. 8 is a diagram showing a cross-sectional configuration of a solid-state imaging device 1 according to the second embodiment.
  • FIG. 9 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 when region D in FIG. 8 is enlarged.
  • parts corresponding to those in FIGS. 2 and 3 are denoted by the same reference numerals, and redundant explanation will be omitted.
  • the conductor portions 34 to which voltage is applied are embedded in this order.
  • An inner side surface S5 of the semiconductor layer 27 is covered with an insulating film 33.
  • the conductor section 34 and the photoelectric conversion section 21 are insulated by the insulating film 33.
  • silicon oxide (SiO) or a high dielectric constant insulating film can be used, for example.
  • a conductor portion 34 is embedded in a groove-shaped space inside the trench portion 25 covered with the semiconductor layer 27 and the insulating film 33.
  • the conductor portion 34 is arranged along the inner side surface S5 of the semiconductor layer 27 with the insulating film 33 interposed therebetween.
  • the material of the conductor portion 34 for example, polysilicon doped with boron (B) or a metal material can be used.
  • a negative bias voltage is applied to the conductor portion 34.
  • holes are induced by the conductor part 34 on the conductor part 34 side (inner side surface S5 side) of the semiconductor layer 27, and the high hole concentration state (hole inducing layer 27a ) is formed, and pinning of the side wall of the trench portion 25 is realized. By this pinning, dark current generated on the sidewalls of the trench portion 25 can be suppressed.
  • Examples of methods for applying a negative bias voltage to the conductor portion 34 include a method of supplying power from the logic board (not shown) side and a method of applying it from the back surface S3 side of the semiconductor substrate 12.
  • the second embodiment shows an example in which the conductor portion 34 is embedded in the space inside the trench portion 25
  • other configurations may also be adopted.
  • the side wall surface S4 of the trench portion 25 is formed so that the conductor portion 34 has a groove-shaped space inside the trench portion 25, the side wall portion of which is formed by the conductor portion 34.
  • polysilicon has the property of absorbing light. Therefore, for example, when the conductor portion 34 shown in FIGS. 8 and 9 is formed of polysilicon, that is, when the polysilicon is embedded in the space inside the trench portion 25 (filled configuration), the quantum There was a possibility that the efficiency QE would decrease.
  • the conductor portion 35 is formed so as to have a groove-shaped space inside the trench portion 25. Therefore, for example, when the conductor portion 34 is formed of polysilicon, the amount of polysilicon can be reduced by the space inside the trench portion 25, and light absorption by the polysilicon can be suppressed. As a result, a decrease in quantum efficiency QE can be suppressed.
  • FIG. 12 is a diagram showing a cross-sectional configuration of a solid-state imaging device 1 according to the third embodiment.
  • FIG. 13 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 when region F in FIG. 12 is enlarged.
  • parts corresponding to those in FIGS. 8 and 9 are designated by the same reference numerals, and redundant explanation will be omitted.
  • the third embodiment differs from the second embodiment in that, as shown in FIGS. 12 and 13, a P-type solid phase diffusion layer 38 is used instead of the semiconductor layer 27 shown in FIG. .
  • the P-type solid phase diffusion layer 38 is a layer that is disposed within the trench portion 25 and covers the side wall surface S4 of the trench portion 25.
  • a semiconductor layer obtained by introducing a P-type impurity (for example, boron (B)) into a non-doped epitaxial growth layer by solid-phase diffusion can be employed.
  • the N-type impurity concentration of the P-type solid phase diffusion layer 38 is 1e16/cm 3 or less (a low value).
  • FIG. 13 a curve showing the N-type impurity concentration overlapping the N-type semiconductor region 23 and the P-type solid phase diffusion layer 38 is shown by a broken line, and a curve showing the P-type impurity concentration is shown by a dashed line.
  • FIG. 14 is a diagram showing the potential distribution. Moreover, in FIG.
  • N-type and P-type impurity concentration distributions shown in FIG. 13 can be obtained by performing analysis using Nano-SIMS, for example.
  • the photoelectric conversion section 21 has an N-type semiconductor region 23 in a region in contact with the P-type solid phase diffusion layer 38 .
  • the N-type semiconductor region 23 for example, a semiconductor region obtained by ion-implanting N-type impurities from the surface S2 side of the semiconductor substrate 12 is used. Thereby, as shown in FIG. 13, the N-type impurity concentration of the N-type semiconductor region 23 is constant at each depth from the surface S2.
  • FIG. 12 illustrates a case where the fixed charge film 13 shown in FIG. 8 is omitted.
  • first element isolation section 26a a portion of the element isolation section 26 on the back surface S3 side
  • second element isolation section 26b a portion on the front surface S2 side
  • the width of the second element isolation part 26b is formed wider than the width of the first element isolation part 26a.
  • an insulating material 39 is embedded inside the second element isolation section 26b.
  • a P-type impurity is ion-implanted into the N-type semiconductor region 23 from the side wall surface S4 of the trench portion 25.
  • the P-type semiconductor region 55 is used, N-type impurities are mixed into the P-type semiconductor region 55, and a potential gradient due to the PN junction between the P-type semiconductor region 55 and the N-type semiconductor region 23 is created as shown in FIG. becomes more gradual. Therefore, the saturation charge amount Qs of the photoelectric conversion section 21 may decrease.
  • FIG. 15 instead of the P-type solid phase diffusion layer 38, a P-type impurity is ion-implanted into the N-type semiconductor region 23 from the side wall surface S4 of the trench portion 25.
  • FIG. 16 is a diagram showing the potential distribution. Further, in FIG. 16, a curve showing the potential distribution is shown by a broken line overlapping the N-type semiconductor region 23 and the P-type semiconductor region 55.
  • the P-type solid phase diffusion layer 38 has an N-type impurity concentration of 1e16/cm 3 or less. Therefore, it is possible to prevent N-type impurities from being mixed into the P-type solid-phase diffusion layer 38, to steepen the potential gradient due to the PN junction between the P-type solid-phase diffusion layer 38 and the N-type semiconductor region 23, and to make the photoelectric conversion section
  • the saturation charge amount Qs of 21 can be improved. Furthermore, even when the pixels 8 are miniaturized, the necessary saturation charge amount Qs can be ensured, and the solid-state imaging device 1 can be made to have a large number of pixels with relative ease.
  • a method for manufacturing the solid-state imaging device 1 according to the third embodiment will be described.
  • N-type impurities for example, phosphorus (P), arsenic (As)
  • P phosphorus
  • As arsenic
  • an N-type semiconductor region 23 is formed.
  • the N-type semiconductor region 23 has a constant N-type impurity concentration at each depth from the surface S2.
  • a mask 40 having an opening at a position where the trench portion 25 is to be formed is formed on the surface S2 of the semiconductor substrate 12.
  • the mask 40 is constructed by laminating a silicon nitride (SiN) film 41 and a silicon oxide (SiO) film 42. Subsequently, anisotropic dry etching is performed through the mask 40 to form the trench portion 25.
  • SiN silicon nitride
  • SiO silicon oxide
  • a semiconductor crystal (silicon (Si)) is epitaxially grown on the side wall surface S4 of the trench portion 25, and a semiconductor crystal (silicon (Si)) is grown in the trench portion 25 so as to cover the side wall surface S4 and the bottom surface of the trench portion 25.
  • a semiconductor layer 43 is formed.
  • the semiconductor layer 43 is formed by covering the surface S2 side of the trench portion 25 with the silicon nitride film 41, and is performed only at the position where the first element isolation portion 26a (see FIG. 12) is to be formed.
  • As the semiconductor layer 43 a non-doped epitaxial growth layer with an impurity concentration of 1e16/cm 3 or less is formed.
  • a P-type impurity for example, boron (B)
  • B boron
  • silicon oxide (SiO) 44 and doped polysilicon 45 are embedded in this order into the space inside the trench portion 25 covered with the P-type solid phase diffusion layer 38.
  • the silicon oxide 44 is buried so as to cover the side surfaces of the P-type solid phase diffusion layer 38.
  • the doped polysilicon 45 is buried until the doped polysilicon 45 covers the entire surface S10 of the mask 40.
  • an etch-back is performed to remove the doped polysilicon 45 from the surface S10 of the mask 40 and the position in the trench portion 25 where the insulating material 39 (see FIG. 12) is buried.
  • FIG. 17E an etch-back is performed to remove the doped polysilicon 45 from the surface S10 of the mask 40 and the position in the trench portion 25 where the insulating material 39 (see FIG. 12) is buried.
  • an insulating material 46 is embedded in the surface S2 side of the trench portion 25.
  • the insulating material 46 is embedded until the insulating material 46 covers the entire surface S10 of the mask 40.
  • the insulating material 46 is polished from the surface S11 side using the CMP technique to form the insulating material 39.
  • the element isolation portion 26 shown in FIG. 12 is formed.
  • an insulating film 14, a light shielding film 15, a planarizing film 16, a color filter layer 18, and a microlens array 19 are formed. In this way, the solid-state imaging device 1 shown in FIG. 12 is manufactured.
  • the configuration of the second element isolation part 26b when formed by this manufacturing method is slightly different from the configuration of the second element isolation part 26b when formed by the above-mentioned formation method. It becomes the composition.
  • N-type impurity ions are implanted into the P-type semiconductor substrate 12 to form the N-type semiconductor region 23.
  • etching is performed from the surface S2 side of the semiconductor substrate 12 through a mask (not shown) to form the trench portion 25.
  • a mask not shown
  • a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25, etc., so as to continuously cover the entire side wall surface S4 and the bottom surface of the trench portion 25, as well as the surface S2 of the semiconductor substrate 12.
  • a semiconductor layer 43 is formed within the trench portion 25 and on the surface S2 of the semiconductor substrate 12.
  • a non-doped epitaxial growth layer with an impurity concentration of 1e16/cm 3 or less is formed.
  • a P-type impurity for example, boron (B)
  • B solid-phase diffusion method
  • the semiconductor layer 43 is changed to the P-type solid phase diffusion layer 38. This can prevent N-type impurities from being mixed into the P-type solid-phase diffusion layer 38, and the concentration of N-type impurities in the P-type solid-phase diffusion layer 38 can be set to 1e16/cm 3 or less.
  • silicon oxide (SiO) 44 and doped polysilicon 45 are embedded in this order into the space inside the trench portion 25 covered with the P-type solid phase diffusion layer 38.
  • the silicon oxide 44 is buried so as to cover the side surfaces of the P-type solid phase diffusion layer 38.
  • the doped polysilicon 45 is buried until the doped polysilicon 45 covers the entire surface S12 of the silicon oxide 44.
  • the surface S2 of the semiconductor substrate 12 is exposed by polishing or the like from the surface S2 side of the semiconductor substrate 12 using CMP technology or etchback. Subsequently, as shown in FIG.
  • a mask 47 having an opening at a position where the second element isolation portion 26b (see FIG. 12) is to be formed is formed on the surface S2 of the semiconductor substrate 12.
  • the mask 47 is constructed by laminating a silicon nitride (SiN) film 48 and a silicon oxide (SiO) film 49.
  • SiN silicon nitride
  • SiO silicon oxide
  • FIG. 18G etching is performed through the mask 47 to form a portion of the trench portion 25 where the second element isolation portion 26b (see FIG. 12) is to be formed (hereinafter also referred to as “trench portion 50”). form).
  • an insulating material 46 is embedded in the trench portion 50.
  • the insulating material 46 is embedded until the insulating material 46 covers the entire surface S10 of the mask 47. Subsequently, as shown in FIG. 18I, the insulating material 46 is polished from the surface S11 side using the CMP technique to form the insulating material 39 shown in FIG. 12. Through such a procedure, the element isolation portion 26 shown in FIG. 12 is formed. Subsequently, as shown in FIG. 12, an insulating film 14, a light shielding film 15, a planarizing film 16, a color filter layer 18, and a microlens array 19 are formed. In this way, the solid-state imaging device 1 shown in FIG. 12 is manufactured.
  • N-type semiconductor region 23 is provided as the N-type region of the photoelectric conversion section 21, but other configurations may also be adopted.
  • FIGS. 19 and 20 as part of the N-type semiconductor region 23, an N-type semiconductor with a relatively high N-type impurity concentration is added to a region of the photoelectric conversion section 21 that is in contact with the trench section 25.
  • a structure having a region hereinafter also referred to as "N+ type semiconductor region 51" may be used.
  • a PN junction is formed between the P-type solid phase diffusion layer 38 and the N+ type semiconductor region 51 (a region with a relatively high N-type impurity concentration), so that the potential gradient can be made steeper, and the photoelectric conversion section 21
  • the saturation charge amount Qs can be increased.
  • the curve showing the N-type impurity concentration overlapping the N-type semiconductor region 23 and the P-type solid phase diffusion layer 38 is shown by a broken line, and the curve showing the P-type impurity concentration is shown by a dashed line.
  • a method for forming the element isolation portion 26 when adopting such a configuration will be described.
  • a manufacturing method similar to the manufacturing method shown in FIGS. 17A to 17G first, similar to the process shown in FIG. 17A, an N-type impurity is ion-implanted into the P-type semiconductor substrate 12, A semiconductor region 23 is formed. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through the mask 40 to form the trench portion 25. Subsequently, as shown in FIG. 21, N type impurity ions are implanted from within the trench portion 25 to form an N+ type semiconductor region 51 on the side wall surface S4 and the bottom surface of the trench portion 25. Subsequently, similarly to the step shown in FIG.
  • a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25, and a semiconductor layer 43 is formed in the trench portion 25 so as to cover the side wall surface S4 and the bottom surface of the trench portion 25. form.
  • the element isolation portion 26 shown in FIG. 19 is formed.
  • an N-type impurity is added to the P-type semiconductor substrate 12 in the same manner as the step shown in FIG. 18A. is ion-implanted to form an N-type semiconductor region 23. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through a mask (not shown) to form the trench portion 25. Subsequently, as shown in FIG. 22A, N type impurity ions are implanted from within the trench portion 25 to form an N + type semiconductor region 51 on the entire sidewall surface S4 and the bottom surface of the trench portion 25. Subsequently, similarly to the step shown in FIG.
  • a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25 to continuously cover the entire side wall surface S4 and the bottom surface of the trench portion 25, as well as the surface S2 of the semiconductor substrate 12.
  • the semiconductor layer 43 is formed in the trench portion 25 and on the surface S2 of the semiconductor substrate 12 so as to do so.
  • the element isolation portion 26 shown in FIG. 22B is formed. Note that, as shown in FIG. 22B, the configuration of the second element isolation part 26b when formed by this formation method is the same as the configuration of the second element isolation part 26b when formed by the above-mentioned formation method (the second element isolation part 26b in FIG. 19). The configuration is slightly different from the configuration of the element isolation section 26b.
  • the P-type solid phase diffusion layer 38 is provided as the P-type layer of the element isolation section 26, but other configurations may also be adopted.
  • a P-type epitaxial growth layer 52 formed by epitaxial growth while adding P-type impurities may be used instead of the P-type solid phase diffusion layer 38.
  • the P-type impurity is added to the N-type semiconductor region 23 when forming this layer. may be ion-implanted.
  • the P-type impurity is not mixed into the N-type semiconductor region 23 as shown in FIG. 24 when the P-type epitaxial growth layer 52 is formed. Therefore, since a PN junction is formed between the N-type semiconductor region 23 with a low P-type impurity concentration and the P-type epitaxial growth layer 52, the potential gradient can be made steeper, and the saturated charge amount Qs of the photoelectric conversion section 21 can be increased. be able to.
  • the curve showing the N-type impurity concentration overlapping the N-type semiconductor region 23 and the P-type solid phase diffusion layer 38 is shown by a broken line, and the curve showing the P-type impurity concentration is shown by a dashed line.
  • a method for forming the element isolation portion 26 when adopting such a configuration will be described.
  • a manufacturing method similar to the manufacturing method shown in FIGS. 17A to 17G first, similar to the process shown in FIG. 17A, an N-type impurity is ion-implanted into the P-type semiconductor substrate 12, A semiconductor region 23 is formed. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through the mask 40 to form the trench portion 25. Subsequently, as shown in FIG. 25, a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25 while adding a P-type impurity, and the trench portion is grown so as to cover the side wall surface S4 and the bottom surface of the trench portion 25. A P-type epitaxial growth layer 52 is formed within 25. Thereafter, by omitting the step shown in FIG. 17C and passing through the steps shown in FIGS. 17D to 17G, the element isolation portion 26 shown in FIG. 23 is formed.
  • an N-type impurity is added to the P-type semiconductor substrate 12 in the same manner as the step shown in FIG. 18A. is ion-implanted to form an N-type semiconductor region 23.
  • etching is performed from the surface S2 side of the semiconductor substrate 12 through a mask (not shown) to form the trench portion 25.
  • a semiconductor crystal is epitaxially grown while adding P-type impurities to the sidewall surface S4 of the trench portion 25, etc., so that the entire sidewall surface S4 and bottom surface of the trench portion 25, as well as the semiconductor substrate 12 are grown.
  • a P-type epitaxial growth layer 52 is formed in the trench portion 25 and on the surface S2 of the semiconductor substrate 12 so as to continuously cover the surface S2. Thereafter, by omitting the step shown in FIG. 18C and passing through the steps shown in FIGS. 18D to 18I, the element isolation portion 26 shown in FIG. 26B is formed. Note that, as shown in FIG. 26B, the configuration of the second element isolation part 26b when formed by this formation method is different from the configuration of the second element isolation part 26b when formed by the above-mentioned formation method (the second element isolation part 26b in FIG. 23). The configuration is slightly different from the configuration of the element isolation section 26b.
  • the N+ type semiconductor region 51 shown in FIG. 19 and the P type semiconductor region 51 shown in FIG. A structure including an epitaxial growth layer 52 may also be used. Thereby, the saturated charge amount Qs of the photoelectric conversion section 21 can be increased.
  • a curve showing the N-type impurity concentration overlapping the N-type semiconductor region 23 and the P-type solid phase diffusion layer 38 is shown by a broken line, and a curve showing the P-type impurity concentration is shown by a dashed line.
  • a method of forming the element isolation portion 26 when such a configuration is adopted will be described. When adopting a manufacturing method similar to the manufacturing method shown in FIGS.
  • a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25 while adding a P-type impurity, and the trench portion is grown so as to cover the side wall surface S4 and the bottom surface of the trench portion 25.
  • a P-type epitaxial growth layer 52 is formed within 25.
  • an N-type impurity is added to the P-type semiconductor substrate 12 in the same manner as the step shown in FIG. 18A. is ion-implanted to form an N-type semiconductor region 23. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through a mask (not shown) to form the trench portion 25. Subsequently, similarly to the step shown in FIG. 22A, N type impurity ions are implanted from within the trench portion 25 to form an N + type semiconductor region 51 on the entire sidewall surface S4 and the bottom surface of the trench portion 25. Subsequently, as shown in FIG.
  • a semiconductor crystal is epitaxially grown while adding P-type impurities to the sidewall surface S4 of the trench portion 25, etc., so that the entire sidewall surface S4 and bottom surface of the trench portion 25 and the semiconductor substrate 12 are grown.
  • a P-type epitaxial growth layer 52 is formed in the trench portion 25 and on the surface S2 of the semiconductor substrate 12 so as to continuously cover the surface S2. Thereafter, by omitting the step shown in FIG. 18C and passing through the steps shown in FIGS. 18D to 18I, the element isolation portion 26 shown in FIG. 30B is formed. Note that, as shown in FIG.
  • the configuration of the second element isolation part 26b when formed by this formation method is different from the configuration of the second element isolation part 26b when formed by the above-mentioned formation method (the second element isolation part 26b in FIG. 27).
  • the configuration is slightly different from the configuration of the element isolation section 26b.
  • FIG. 31 is a diagram showing a cross-sectional configuration of a solid-state imaging device 1 according to the fourth embodiment.
  • FIG. 32 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 when region J in FIG. 31 is enlarged.
  • parts corresponding to those in FIGS. 12 and 13 are denoted by the same reference numerals, and redundant explanation will be omitted.
  • an N-type epitaxial growth layer 53 and a P-type epitaxial growth layer 54 are used in place of the P-type solid phase diffusion layer 38 shown in FIG.
  • This embodiment is different from the third embodiment.
  • the N-type epitaxial growth layer 53 and the P-type epitaxial growth layer 54 are laminated in this order on the side wall surface S4 of the trench portion 25.
  • the N-type epitaxial growth layer 53 is a layer disposed within the trench portion 25 and covering the side wall surface S4 of the trench portion 25.
  • an epitaxial growth layer formed by epitaxial growth while adding N-type impurities can be used.
  • the P-type impurity concentration of the N-type epitaxial growth layer 53 is 1e16/cm 3 or less.
  • the N-type epitaxial growth layer 53 can steepen the potential gradient due to the PN junction between the N-type epitaxial growth layer 53 and the P-type epitaxial growth layer 54. Therefore, the saturation charge amount Qs of the photoelectric conversion section 21 can be improved.
  • the curve showing the N-type impurity concentration overlapping the N-type semiconductor region 23, the N-type epitaxial growth layer 53, and the P-type epitaxial growth layer 54 is shown by a broken line, and the curve showing the P-type impurity concentration is shown by a dashed line. ing.
  • the P-type epitaxial growth layer 54 is a layer that is disposed in the space inside the trench portion 25 covered with the N-type epitaxial growth layer 53 and is in contact with the N-type epitaxial growth layer 53 .
  • the P-type epitaxial growth layer 54 is stacked on the surface of the N-type epitaxial growth layer 53 on the center side in the width direction of the trench portion 25, forming a PN junction with the N-type epitaxial growth layer 53.
  • the P-type epitaxial growth layer 54 for example, an epitaxial growth layer formed by epitaxial growth while adding P-type impurities can be employed. By using such an epitaxial growth layer, as shown in FIG.
  • the N-type impurity concentration of the P-type epitaxial growth layer 54 is 1e16/cm 3 or less.
  • the P-type epitaxial growth layer 54 can have a steeper potential gradient due to the PN junction. Therefore, a decrease in the saturation charge amount Qs of the photoelectric conversion section 21 can be further suppressed.
  • FIG. 12 illustrates a case where the fixed charge film 13 shown in FIG. 8 is omitted.
  • a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25 while adding an N-type impurity, and the trench portion is grown so as to cover the side wall surface S4 and the bottom surface of the trench portion 25.
  • An N-type epitaxial growth layer 53 is formed within 25.
  • a semiconductor crystal is epitaxially grown on the surface of the N-type epitaxial growth layer 53 on the center side in the width direction of the trench portion 25 (hereinafter also referred to as "center side surface S13") while adding P-type impurities.
  • a P-type epitaxial growth layer 54 is formed in the trench portion 25 so as to cover the central side surface S13 of the N-type epitaxial growth layer 53.
  • the element isolation portion 26 shown in FIG. 31 is formed.
  • an insulating film 14, a light shielding film 15, a planarizing film 16, a color filter layer 18, and a microlens array 19 are formed. As a result, the solid-state imaging device 1 shown in FIG. 31 is manufactured.
  • an N-type impurity is added to the P-type semiconductor substrate 12. is ion-implanted to form an N-type semiconductor region 23. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through a mask (not shown) to form the trench portion 25. Subsequently, as shown in FIG. 34A, a semiconductor crystal is epitaxially grown while adding an N-type impurity to the side wall surface S4 of the trench portion 25, etc., so that the entire side wall surface S4 and bottom surface of the trench portion 25, as well as the semiconductor substrate 12 are grown.
  • An N-type epitaxial growth layer 53 is formed in the trench portion 25 and on the surface S2 of the semiconductor substrate 12 so as to continuously cover the surface S2. Subsequently, as shown in FIG. 34B, a semiconductor crystal is epitaxially grown while adding P-type impurities to the center side surface in the width direction of the trench portion 25 (center side surface S13) of the N-type epitaxial growth layer 53, and the N-type epitaxial growth is performed. A P-type epitaxial growth layer 54 is formed in the trench portion 25 or the like so as to continuously cover the entire center side surface S13 of the layer 53. Thereafter, the step shown in FIG. 18C is omitted and the steps shown in FIGS. 18D to 18I are performed to form the element isolation portion 26 shown in FIG.
  • the configuration of the second element isolation part 26b when formed by this manufacturing method is different from the configuration of the second element isolation part 26b when formed by the above manufacturing method (the second element isolation part 26b in FIG. 31).
  • the configuration is slightly different from that of the element isolation section 26b (configuration of the element isolation section 26b).
  • an insulating film 14, a light shielding film 15, a planarizing film 16, a color filter layer 18, and a microlens array 19 are formed.
  • the solid-state imaging device 1 shown in FIG. 31 is manufactured.
  • the present technology can also be applied to photodetection devices in general, including a ranging sensor that measures distance, also called a ToF (Time of Flight) sensor.
  • a ranging sensor that measures distance
  • ToF Time of Flight
  • a distance measurement sensor emits illumination light toward an object, detects the reflected light that is reflected back from the object's surface, and measures the flight from the time the illumination light is emitted until the reflected light is received. This is a sensor that calculates the distance to an object based on time.
  • the structure of the pixel 8 described above can be adopted.
  • FIG. 35 is a diagram illustrating an example of a schematic configuration of an imaging device (video camera, digital still camera, etc.) as an electronic device to which the present technology is applied.
  • the imaging device 1000 includes a lens group 1001, a solid-state imaging device 1002 (solid-state imaging device 1 according to the first embodiment), a DSP (Digital Signal Processor) circuit 1003, and a frame memory 1004. , a monitor 1005, and a memory 1006.
  • DSP circuit 1003, frame memory 1004, monitor 1005, and memory 1006 are interconnected via bus line 1007.
  • a lens group 1001 guides incident light (image light) from a subject to a solid-state imaging device 1002, and forms an image on a light entrance surface (pixel region) of the solid-state imaging device 1002.
  • the solid-state imaging device 1002 is composed of the CMOS image sensor of the first embodiment described above.
  • the solid-state imaging device 1002 converts the amount of incident light imaged on the light entrance surface by the lens group 1001 into an electric signal for each pixel, and supplies the electric signal to the DSP circuit 1003 as a pixel signal.
  • the DSP circuit 1003 performs predetermined image processing on pixel signals supplied from the solid-state imaging device 1002.
  • the DSP circuit 1003 supplies the image signal after image processing to the frame memory 1004 in units of frames, and causes the frame memory 1004 to temporarily store the image signal.
  • the monitor 1005 is composed of a panel display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel.
  • the monitor 1005 displays an image (moving image) of the subject based on pixel signals for each frame temporarily stored in the frame memory 1004.
  • the memory 1006 consists of a DVD, flash memory, etc.
  • the memory 1006 reads out and records pixel signals in frame units temporarily stored in the frame memory 1004.
  • the electronic device to which the solid-state imaging device 1 can be applied is not limited to the imaging device 1000, but can also be applied to other electronic devices.
  • the solid-state imaging device 1 according to the first embodiment is used as the solid-state imaging device 1002
  • other configurations may also be adopted.
  • a configuration using other photodetecting devices to which the present technology is applied such as the solid-state imaging device 1 according to the second to fourth embodiments and the solid-state imaging device 1 according to a modification of the second to fourth embodiments. You can also use it as
  • the present disclosure may have the following configuration.
  • a trench portion formed between the photoelectric conversion parts of the semiconductor substrate, a semiconductor layer disposed within the trench portion and covering a side wall surface of the trench portion, and an interior of the trench portion covered with the semiconductor layer.
  • an element isolation section having a functional layer arranged in a space of The photoelectric conversion section has an N-type semiconductor region in a region in contact with the semiconductor layer,
  • the semiconductor layer has a P-type impurity concentration of 1e16/cm 3 or less
  • the functional layer is a layer that induces holes on the functional layer side of the semiconductor layer.
  • the photodetecting device is a layer that induces holes on the functional layer side of the semiconductor layer.
  • the photodetection device according to (1), wherein the N-type semiconductor region has an N-type impurity concentration peak at an interface between the semiconductor layer and the N-type semiconductor region.
  • the functional layer is a fixed charge film that is disposed along a surface of the semiconductor layer that is far from the side wall surface of the trench portion and has a negative fixed charge.
  • the functional layer is a conductor portion disposed along a surface of the semiconductor layer that is far from the side wall surface of the trench portion, and to which a negative bias voltage is applied. (1) or (2) above. ).
  • the photodetecting device according to (4) wherein the conductor portion covers the side wall surface of the trench portion such that the trench portion has a groove-shaped space inside the trench portion, the side wall being formed by the conductor portion. .
  • the semiconductor layer is a semiconductor layer formed at a different timing from that of the semiconductor substrate.
  • the semiconductor layer is an epitaxially grown layer.
  • the photoelectric conversion section has an N-type semiconductor region in a region in contact with the P-type solid phase diffusion layer,
  • the P-type solid phase diffusion layer has an N-type impurity concentration of 1e16/cm 3 or less.
  • a semiconductor substrate on which a plurality of photoelectric conversion parts are formed A trench portion formed between the photoelectric conversion parts of the semiconductor substrate, an N-type epitaxial growth layer disposed within the trench portion and covering a side wall surface of the trench portion, and the N-type epitaxial growth layer covered with the N-type epitaxial growth layer.
  • an element isolation part having a P-type epitaxial growth layer disposed in a space inside the trench part and in contact with the N-type epitaxial growth layer;
  • the N-type epitaxial growth layer has a P-type impurity concentration of 1e16/cm 3 or less,
  • the P-type epitaxial growth layer has an N-type impurity concentration of 1e16/cm 3 or less.
  • a semiconductor substrate on which a plurality of photoelectric conversion sections are formed a trench section formed between the photoelectric conversion sections of the semiconductor substrate; a semiconductor layer disposed within the trench section and covering a side wall surface of the trench section; and an element isolation section having a functional layer disposed in a space inside the trench section covered with the semiconductor layer, and the photoelectric conversion section has an N-type semiconductor region in a region in contact with the semiconductor layer.
  • the semiconductor layer has a P-type impurity concentration of 1e16/cm 3 or less
  • the functional layer includes a photodetection device that is a layer that induces holes on the functional layer side of the semiconductor layer.
  • the photoelectric conversion section includes an element isolation section having a solid phase diffusion layer, the photoelectric conversion section has an N type semiconductor region in a region in contact with the P type solid phase diffusion layer, and the P type solid phase diffusion layer has an N type semiconductor region.
  • An electronic device comprising: a photodetector having a type impurity concentration of 1e16/cm 3 or less, and the P-type epitaxial growth layer has an N-type impurity concentration of 1e16/cm 3 or less.
  • (13) a step of forming a trench portion in a semiconductor substrate; forming an epitaxial growth layer with an impurity concentration of 1e16/cm 3 or less on the sidewall surface of the trench portion by epitaxial growth;
  • a method for manufacturing a photodetector comprising the step of doping a P-type impurity from within the trench portion into the epitaxial growth layer by solid-phase diffusion.
  • (14) a step of forming a trench portion in a semiconductor substrate; forming an N-type epitaxial growth layer with a P-type impurity concentration of 1e16/cm 3 or less on the side wall surface of the trench portion by epitaxial growth while adding N-type impurities; forming a P-type epitaxial growth layer with an N-type impurity concentration of 1e16/cm 3 or less on a surface of the N-type epitaxial growth layer on the center side in the trench width direction by epitaxial growth while adding P-type impurities; A method for manufacturing a photodetection device.
  • SYMBOLS 1 Solid-state imaging device, 2... Pixel area, 3... Vertical drive circuit, 4... Column signal processing circuit, 5... Horizontal drive circuit, 6... Output circuit, 7... Control circuit, 8... Pixel, 9... Pixel drive wiring, 10... Vertical signal line, 11... Horizontal signal line, 12... Semiconductor substrate, 13... Fixed charge film, 14... Insulating film, 15... Light shielding film, 16... Flattening film, 17... Light receiving layer, 18... Color filter layer, 19... Microlens array, 20... Wiring layer, 21... Photoelectric conversion section, 22... P-type semiconductor region, 23... N-type semiconductor region, 24... P-type semiconductor region, 25... Trench section, 26... Element separation section, 27 ...
  • P type epitaxial growth layer 55... P-type semiconductor region, 1000... imaging device, 1001... lens group, 1002... solid-state imaging device, 1003... DSP circuit, 1004... frame memory, 1005... monitor, 1006... memory, 1007... bus line

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Abstract

Provided is a light detection apparatus capable of improving the saturation charge amount Qs of a photoelectric conversion unit. Specifically, the light detection apparatus is configured to comprise: a semiconductor substrate on which a plurality of photoelectric conversion units are formed; and an element separation part which has a trench part formed between photoelectric conversion units on the semiconductor substrate, a semiconductor layer disposed in the trench part and covering side walls of the trench part, and a functional layer disposed in a space in the trench part covered by the semiconductor layer. The photoelectric conversion units are configured to have an N-type semiconductor region in a region contacting the semiconductor layer. The semiconductor layer has a P-type impurity concentration of not more than 1e16/cm3. The functional layer induces holes in the functional layer side of the semiconductor layer.

Description

光検出装置、電子機器及び光検出装置の製造方法Photodetection device, electronic equipment, and method for manufacturing photodetection device
　本開示は、光検出装置、電子機器及び光検出装置の製造方法に関する。 The present disclosure relates to a photodetection device, an electronic device, and a method of manufacturing the photodetection device.
　従来、光電変換部間にトレンチ部を有し、トレンチ部内にエピタキシャル成長によるＰ型の半導体層が配置された光検出装置が提案されている（例えば、特許文献１参照）。特許文献１に記載の光検出装置では、Ｐ型の半導体層をホールピニング層として機能させ、トレンチ部の側壁面における暗電流の発生を抑制するようになっている。 Conventionally, a photodetection device has been proposed that has a trench portion between photoelectric conversion portions and a P-type semiconductor layer formed by epitaxial growth is disposed within the trench portion (see, for example, Patent Document 1). In the photodetection device described in Patent Document 1, the P-type semiconductor layer functions as a hole pinning layer to suppress the generation of dark current on the sidewall surface of the trench portion.
特開２０１２－３８９８１号公報JP2012-38981A
　このような光検出装置では、光電変換部に蓄積できる電荷量（以下、「飽和電荷量Ｑs」とも呼ぶ）のさらなる向上が求められている。 In such a photodetection device, there is a demand for further improvement in the amount of charge that can be accumulated in the photoelectric conversion section (hereinafter also referred to as "saturation charge amount Qs").
　本開示は、光電変換部の飽和電荷量Ｑsを向上可能な光検出装置、電子機器及び光検出装置の製造方法を提供することを目的とする。 An object of the present disclosure is to provide a photodetection device, an electronic device, and a method for manufacturing a photodetection device that can improve the saturation charge amount Qs of a photoelectric conversion unit.
　本開示の光検出装置は、（ａ）複数の光電変換部が形成された半導体基板と、（ｂ）半導体基板のうちの光電変換部間に形成されたトレンチ部、トレンチ部内に配置され、トレンチ部の側壁面を被覆する半導体層、及び半導体層で被覆されたトレンチ部の内部の空間に配置された機能層を有する素子分離部と、を備え、（ｃ）光電変換部は、半導体層と接する領域にＮ型半導体領域を有しており、（ｄ）半導体層は、Ｐ型の不純物濃度が１ｅ１６/ｃｍ3以下であり、（ｅ）機能層は、半導体層の機能層側にホールを誘起させる層であることを要旨とする。 A photodetecting device of the present disclosure includes: (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed; (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate; (c) the photoelectric conversion section includes a semiconductor layer covering a side wall surface of the trench section; and an element isolation section having a functional layer disposed in a space inside the trench section covered with the semiconductor layer; It has an N-type semiconductor region in the contacting region, (d) the semiconductor layer has a P-type impurity concentration of 1e16/cm 3 or less, and (e) the functional layer has holes on the functional layer side of the semiconductor layer. The gist is that it is a layer that induces
　本開示の他の光検出装置は、（ａ）複数の光電変換部が形成された半導体基板と、（ｂ）半導体基板のうちの光電変換部間に形成されたトレンチ部、及びトレンチ部内に配置され、トレンチ部の側壁面を被覆するＰ型固相拡散層を有する素子分離部と、を備え、（ｃ）光電変換部は、Ｐ型固相拡散層と接する領域にＮ型半導体領域を有しており、（ｄ）Ｐ型固相拡散層は、Ｎ型の不純物濃度が１ｅ１６/ｃｍ3以下であることを要旨とする。 Another photodetection device of the present disclosure includes (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed, (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate, and a trench section disposed within the trench section. and (c) the photoelectric conversion section has an N-type semiconductor region in a region in contact with the P-type solid-phase diffusion layer. (d) The P-type solid phase diffusion layer has an N-type impurity concentration of 1e16/cm 3 or less.
　本開示の他の光検出装置は、（ａ）複数の光電変換部が形成された半導体基板と、（ｂ）半導体基板のうちの光電変換部間に形成されたトレンチ部、トレンチ部内に配置され、トレンチ部の側壁面を被覆するＮ型エピタキシャル成長層、及びＮ型エピタキシャル成長層で被覆されたトレンチ部の内部の空間に配置され、Ｎ型エピタキシャル成長層と接するＰ型エピタキシャル成長層を有する素子分離部を備え、（ｃ）Ｎ型エピタキシャル成長層は、Ｐ型の不純物濃度が１ｅ１６/ｃｍ3以下であり、（ｄ）Ｐ型エピタキシャル成長層は、Ｎ型の不純物濃度が１ｅ１６/ｃｍ3以下であることを要旨とする。 Another photodetection device of the present disclosure includes (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed, (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate, and a trench section disposed within the trench section. , an element isolation section having an N-type epitaxial growth layer covering a side wall surface of the trench portion, and a P-type epitaxial growth layer disposed in a space inside the trench portion covered with the N-type epitaxial growth layer and in contact with the N-type epitaxial growth layer. , (c) The N-type epitaxial growth layer has a P-type impurity concentration of 1e16/cm 3 or less, and (d) The P-type epitaxial growth layer has an N-type impurity concentration of 1e16/cm 3 or less. do.
　本開示の電子機器は、（ａ）複数の光電変換部が形成された半導体基板、（ｂ）並びに半導体基板のうちの光電変換部間に形成されたトレンチ部、トレンチ部内に配置され、トレンチ部の側壁面を被覆する半導体層、及び半導体層で被覆されたトレンチ部の内部の空間に配置された機能層を有する素子分離部を備え、（ｃ）光電変換部は、半導体層と接する領域にＮ型半導体領域を有しており、（ｄ）半導体層は、Ｐ型の不純物濃度が１ｅ１６/ｃｍ3以下であり、（ｅ）機能層は、半導体層の機能層側にホールを誘起させる層である光検出装置を備えることを要旨とする。 An electronic device of the present disclosure includes (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed, (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate, and a trench section disposed within the trench section. (c) a photoelectric conversion section is provided in a region in contact with the semiconductor layer; It has an N-type semiconductor region, (d) the semiconductor layer has a P-type impurity concentration of 1e16/cm 3 or less, and (e) the functional layer is a layer that induces holes on the functional layer side of the semiconductor layer. The gist is to provide a photodetecting device that is.
　本開示の他の電子機器は、（ａ）複数の光電変換部が形成された半導体基板、（ｂ）並びに半導体基板のうちの光電変換部間に形成されたトレンチ部、及びトレンチ部内に配置され、トレンチ部の側壁面を被覆するＰ型固相拡散層を有する素子分離部を備え、（ｃ）光電変換部は、Ｐ型固相拡散層と接する領域にＮ型半導体領域を有しており、（ｄ）Ｐ型固相拡散層は、Ｎ型の不純物濃度が１ｅ１６/ｃｍ3以下である光検出装置を備えることを要旨とする。 Another electronic device of the present disclosure includes (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed, (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate, and a trench section disposed within the trench section. (c) the photoelectric conversion section has an N-type semiconductor region in a region in contact with the P-type solid-phase diffusion layer; , (d) The P-type solid phase diffusion layer is provided with a photodetector having an N-type impurity concentration of 1e16/cm 3 or less.
　本開示の他の電子機器は、（ａ）複数の光電変換部が形成された半導体基板、（ｂ）並びに半導体基板のうちの光電変換部間に形成されたトレンチ部、トレンチ部内に配置され、トレンチ部の側壁面を被覆するＮ型エピタキシャル成長層、及びＮ型エピタキシャル成長層で被覆されたトレンチ部の内部の空間に配置され、Ｎ型エピタキシャル成長層と接するＰ型エピタキシャル成長層を有する素子分離部を備え、（ｃ）Ｎ型エピタキシャル成長層は、Ｐ型の不純物濃度が１ｅ１６/ｃｍ3以下であり、（ｄ）Ｐ型エピタキシャル成長層は、Ｎ型の不純物濃度が１ｅ１６/ｃｍ3以下である光検出装置を備えることを要旨とする。 Another electronic device of the present disclosure includes (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed, (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate, and a trench section disposed within the trench section; an element isolation section having an N-type epitaxial growth layer covering a side wall surface of the trench portion, and a P-type epitaxial growth layer disposed in a space inside the trench portion covered with the N-type epitaxial growth layer and in contact with the N-type epitaxial growth layer; (c) The N-type epitaxial growth layer has a P-type impurity concentration of 1e16/cm 3 or less, and (d) The P-type epitaxial growth layer includes a photodetector having an N-type impurity concentration of 1e16/cm 3 or less. The gist is that.
　本開示の光検出装置の製造方法は、（ａ）半導体基板にトレンチ部を形成する工程と、（ｂ）エピタキシャル成長によって、トレンチ部の側壁面に不純物濃度が１ｅ１６/ｃｍ3以下のエピタキシャル成長層を形成する工程と、（ｃ）固相拡散によって、トレンチ部内からエピタキシャル成長層にＰ型の不純物をドープする工程と、を含むことを要旨とする。 A method for manufacturing a photodetection device according to the present disclosure includes (a) forming a trench portion in a semiconductor substrate; and (b) forming an epitaxial growth layer with an impurity concentration of 1e16/cm 3 or less on the side wall surface of the trench portion by epitaxial growth. and (c) a step of doping the epitaxial growth layer with a P-type impurity from within the trench portion by solid-phase diffusion.
　本開示の他の光検出装置の製造方法は、（ａ）半導体基板にトレンチ部を形成する工程と、（ｂ）Ｎ型の不純物を添加しながらのエピタキシャル成長によって、トレンチ部の側壁面にＰ型の不純物濃度が１ｅ１６/ｃｍ3以下のＮ型エピタキシャル成長層を形成する工程と、（ｃ）Ｐ型の不純物を添加しながらのエピタキシャル成長によって、Ｎ型エピタキシャル成長層のトレンチ部幅方向中心側の面にＮ型の不純物濃度が１ｅ１６/ｃｍ3以下のＰ型エピタキシャル成長層を形成する工程と、を含むことを要旨とする。 Another method of manufacturing a photodetecting device according to the present disclosure includes (a) forming a trench in a semiconductor substrate, and (b) epitaxial growth while adding N-type impurities to form a P-type on the side wall surface of the trench. By forming an N-type epitaxial growth layer with an impurity concentration of 1e16/cm 3 or less, and (c) epitaxial growth while adding P-type impurities, N is formed on the center side in the trench width direction of the N-type epitaxial growth layer. The method includes the step of forming a P-type epitaxial growth layer having a type impurity concentration of 1e16/cm 3 or less.
第１の実施形態に係る固体撮像装置の全体構成を示す図である。1 is a diagram showing the overall configuration of a solid-state imaging device according to a first embodiment. 図１のＡ－Ａ線で破断した場合の、固体撮像装置の断面構成を示す図である。2 is a diagram illustrating a cross-sectional configuration of the solid-state imaging device taken along line AA in FIG. 1. FIG. 図２の領域Ｂを拡大した場合の、固体撮像装置の断面構成を示す図である。FIG. 3 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region B in FIG. 2 is enlarged. 図３のＣ－Ｃ線の位置における、Ｎ型の不純物濃度の分布を示す図である。4 is a diagram showing the distribution of N-type impurity concentration at the position of line CC in FIG. 3. FIG. 半導体層がＰ型である場合の、固体撮像装置の断面構成を示す図である。FIG. 2 is a diagram showing a cross-sectional configuration of a solid-state imaging device when the semiconductor layer is of P type. 固体撮像装置の製造方法を示す図である。It is a figure showing the manufacturing method of a solid-state imaging device. 固体撮像装置の製造方法を示す図である。It is a figure showing the manufacturing method of a solid-state imaging device. 固体撮像装置の製造方法を示す図である。It is a figure showing the manufacturing method of a solid-state imaging device. 固体撮像装置の製造方法を示す図である。It is a figure showing the manufacturing method of a solid-state imaging device. 固体撮像装置の製造方法を示す図である。It is a figure showing the manufacturing method of a solid-state imaging device. 固体撮像装置の製造方法を示す図である。It is a figure showing the manufacturing method of a solid-state imaging device. 固体撮像装置の製造方法を示す図である。It is a figure showing the manufacturing method of a solid-state imaging device. 固体撮像装置の製造方法を示す図である。It is a figure showing the manufacturing method of a solid-state imaging device. 変形例に係る固体撮像装置の製造方法を示す図である。It is a figure showing the manufacturing method of the solid-state imaging device concerning a modification. 変形例に係る固体撮像装置の製造方法を示す図である。It is a figure showing the manufacturing method of the solid-state imaging device concerning a modification. 変形例に係る固体撮像装置の製造方法を示す図である。It is a figure showing the manufacturing method of the solid-state imaging device concerning a modification. 変形例に係る固体撮像装置の製造方法を示す図である。It is a figure showing the manufacturing method of the solid-state imaging device concerning a modification. 第２の実施形態に係る固体撮像装置の断面構成を示す図である。FIG. 3 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a second embodiment. 図８の領域Ｄを拡大した場合の、固体撮像装置の断面構成を示す図である。9 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region D in FIG. 8 is enlarged. FIG. 変形例に係る固体撮像装置の断面構成を示す図である。FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification. 図１０の領域Ｅを拡大した場合の、固体撮像装置の断面構成を示す図である。11 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region E in FIG. 10 is enlarged. FIG. 第３の実施形態に係る固体撮像装置の断面構成を示す図である。FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a third embodiment. 図１２の領域Ｆを拡大した場合の、固体撮像装置の断面構成を示す図である。13 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region F in FIG. 12 is enlarged. FIG. ポテンシャル分布を示す図である。FIG. 3 is a diagram showing potential distribution. Ｐ型半導体領域を有する場合の、固体撮像装置の断面構成を示す図である。FIG. 2 is a diagram showing a cross-sectional configuration of a solid-state imaging device having a P-type semiconductor region. ポテンシャル分布を示す図である。FIG. 3 is a diagram showing potential distribution. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 変形例に係る固体撮像装置の断面構成を示す図である。FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification. 図１９の領域Ｇを拡大した場合の、固体撮像装置の断面構成を示す図である。FIG. 20 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region G in FIG. 19 is enlarged. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 変形例に係る固体撮像装置の断面構成を示す図である。FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification. 図２３の領域Ｈを拡大した場合の、固体撮像装置の断面構成を示す図である。24 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region H in FIG. 23 is enlarged. FIG. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 変形例に係る固体撮像装置の断面構成を示す図である。FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification. 図２７の領域Ｉを拡大した場合の、固体撮像装置の断面構成を示す図である。28 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region I in FIG. 27 is enlarged. FIG. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 第４の実施形態に係る固体撮像装置の断面構成を示す図である。FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a fourth embodiment. 図３１の領域Ｊを拡大した場合の、固体撮像装置の断面構成を示す図である。32 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region J in FIG. 31 is enlarged. FIG. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 素子分離部の形成方法を示す図である。FIG. 3 is a diagram illustrating a method of forming an element isolation section. 第５の実施形態に係る電子機器の全体構成を示す図である。FIG. 3 is a diagram showing the overall configuration of an electronic device according to a fifth embodiment.
　以下に、本開示の実施形態に係る光検出装置、電子機器及び光検出装置の製造方法の一例を、図１～図３５を参照しながら説明する。本開示の実施形態は以下の順序で説明する。なお、本開示は以下の例に限定されるものではない。また、本明細書に記載された効果は例示であって限定されるものではなく、また他の効果があってもよい。 An example of a photodetection device, an electronic device, and a method of manufacturing the photodetection device according to an embodiment of the present disclosure will be described below with reference to FIGS. 1 to 35. Embodiments of the present disclosure will be described in the following order. Note that the present disclosure is not limited to the following examples. Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.
１．第１の実施形態：固体撮像装置
　１－１　固体撮像装置の全体の構成
　１－２　要部の構成
　１－３　固体撮像装置の製造方法
　１－４　変形例
２．第２の実施形態：固体撮像装置
　２－１　要部の構成
　２－２　変形例
３．第３の実施形態：固体撮像装置
　３－１　要部の構成
　３－２　固体撮像装置の製造方法
　３－３　変形例
４．第４の実施形態：固体撮像装置
　４－１　要部の構成
　４－２　固体撮像装置の製造方法
　４－３　変形例
５．第５の実施形態：電子機器への応用例 1. First embodiment: Solid-state imaging device 1-1 Overall configuration of solid-state imaging device 1-2 Configuration of main parts 1-3 Manufacturing method of solid-state imaging device 1-4 Modification example 2. Second embodiment: Solid-state imaging device 2-1 Configuration of main parts 2-2 Modification example 3. Third embodiment: Solid-state imaging device 3-1 Configuration of main parts 3-2 Manufacturing method of solid-state imaging device 3-3 Modification example 4. Fourth embodiment: Solid-state imaging device 4-1 Configuration of main parts 4-2 Manufacturing method of solid-state imaging device 4-3 Modification example 5. Fifth embodiment: Application example to electronic equipment
〈１．第１の実施形態：固体撮像装置〉
［１－１　固体撮像装置の全体の構成］
　本開示の第１の実施形態に係る固体撮像装置１（広義には「光検出装置」）について説明する。図１は、第１の実施形態に係る固体撮像装置１の全体構成を示す図である。
　図１の固体撮像装置１は、裏面照射型のＣＭＯＳ（Complementary Metal Oxide Semiconductor）イメージセンサである。図３５に示すように、固体撮像装置１（１００２）はレンズ群１００１を介して、被写体からの像光（入射光）を取り込み、撮像面上に結像された入射光の光量を画素単位で電気信号に変換して画素信号として出力する。
　図１に示すように、固体撮像装置１は、画素領域２と、垂直駆動回路３と、カラム信号処理回路４と、水平駆動回路５と、出力回路６と、制御回路７とを備えている。 <1. First embodiment: solid-state imaging device>
[1-1 Overall configuration of solid-state imaging device]
A solid-state imaging device 1 (“photodetection device” in a broad sense) according to a first embodiment of the present disclosure will be described. FIG. 1 is a diagram showing the overall configuration of a solid-state imaging device 1 according to the first embodiment.
The solid-state imaging device 1 in FIG. 1 is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor. As shown in FIG. 35, the solid-state imaging device 1 (1002) captures image light (incident light) from a subject through a lens group 1001, and calculates the amount of incident light formed on the imaging surface in pixel units. It is converted into an electrical signal and output as a pixel signal.
As shown in FIG. 1, the solid-state imaging device 1 includes a pixel region 2, a vertical drive circuit 3, a column signal processing circuit 4, a horizontal drive circuit 5, an output circuit 6, and a control circuit 7. .
　画素領域２は、二次元アレイ状に配置された複数の画素８を有している。画素８は、図２に示した光電変換部２１と、複数の画素トランジスタとを有している。複数の画素トランジスタとしては、例えば、転送トランジスタ、リセットトランジスタ、増幅トランジスタ、及び選択トランジスタによって構成される４つのＭＯＳトランジスタが挙げられる。
　垂直駆動回路３は、例えば、シフトレジスタによって構成され、所望の画素駆動配線９を選択し、選択した画素駆動配線９に画素８を駆動するためのパルスを供給し、各画素８を行単位で駆動する。即ち、垂直駆動回路３は、画素領域２の各画素８を行単位で順次垂直方向に選択走査し、各画素８の光電変換部２１において受光量に応じて生成した信号電荷に基づく画素信号を、垂直信号線１０を通してカラム信号処理回路４に供給する。 The pixel area 2 has a plurality of pixels 8 arranged in a two-dimensional array. The pixel 8 includes the photoelectric conversion section 21 shown in FIG. 2 and a plurality of pixel transistors. Examples of the plurality of pixel transistors include four MOS transistors including a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor.
The vertical drive circuit 3 is configured by, for example, a shift register, selects a desired pixel drive wiring 9, supplies pulses for driving the pixels 8 to the selected pixel drive wiring 9, and drives each pixel 8 in rows. drive That is, the vertical drive circuit 3 sequentially selectively scans each pixel 8 in the pixel region 2 in the vertical direction row by row, and generates a pixel signal based on the signal charge generated in the photoelectric conversion section 21 of each pixel 8 according to the amount of light received. , are supplied to the column signal processing circuit 4 through the vertical signal line 10.
　カラム信号処理回路４は、例えば、画素８の列毎に配置されており、１行分の画素８から出力される信号に対して画素列毎にノイズ除去等の信号処理を行う。例えばカラム信号処理回路４は画素固有の固定パターンノイズを除去するためのＣＤＳ(Correlated Double Sampling：相関二重サンプリング)及びＡＤ(Analog Digital)変換等の信号処理を行う。
　水平駆動回路５は、例えば、シフトレジスタによって構成され、水平走査パルスをカラム信号処理回路４に順次出力して、カラム信号処理回路４の各々を順番に選択し、カラム信号処理回路４の各々から信号処理が行われた画素信号を水平信号線１１に出力させる。 The column signal processing circuit 4 is arranged, for example, for each column of pixels 8, and performs signal processing such as noise removal on the signals output from the pixels 8 of one row for each pixel column. For example, the column signal processing circuit 4 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog Digital) conversion to remove fixed pattern noise specific to pixels.
The horizontal drive circuit 5 is configured by, for example, a shift register, and sequentially outputs horizontal scanning pulses to the column signal processing circuits 4 to select each of the column signal processing circuits 4 in turn, and selects each of the column signal processing circuits 4 from each of the column signal processing circuits 4 in turn. The pixel signal subjected to signal processing is output to the horizontal signal line 11.
　出力回路６は、カラム信号処理回路４の各々から水平信号線１１を通して、順次に供給される画素信号に対し信号処理を行って出力する。信号処理としては、例えば、バファリング、黒レベル調整、列ばらつき補正、各種デジタル信号処理等を用いることができる。
　制御回路７は、垂直同期信号、水平同期信号、及びマスタクロック信号に基づいて、垂直駆動回路３、カラム信号処理回路４、及び水平駆動回路５等の動作の基準となるクロック信号や制御信号を生成する。そして、制御回路７は、生成したクロック信号や制御信号を、垂直駆動回路３、カラム信号処理回路４、及び水平駆動回路５等に出力する。 The output circuit 6 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 4 through the horizontal signal line 11, and outputs the processed pixel signals. As signal processing, for example, buffering, black level adjustment, column variation correction, various digital signal processing, etc. can be used.
The control circuit 7 generates clock signals and control signals that serve as operating standards for the vertical drive circuit 3, column signal processing circuit 4, horizontal drive circuit 5, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. generate. Then, the control circuit 7 outputs the generated clock signal and control signal to the vertical drive circuit 3, column signal processing circuit 4, horizontal drive circuit 5, and the like.
［１－２　要部の構成］
　次に、固体撮像装置１の詳細構造について説明する。図２は、図１のＡ－Ａ線で破断した場合の、固体撮像装置１の断面構成を示す図である。また、図３は、図２の領域Ｂを拡大した場合の、固体撮像装置１の断面構成を示す図である。
　図２及び図３に示すように、固体撮像装置１は、半導体基板１２、固定電荷膜１３（広義には「機能層」）、絶縁膜１４、遮光膜１５及び平坦化膜１６がこの順に積層されてなる受光層１７が配置されている。また、受光層１７の平坦化膜１６側の面（以下、「裏面Ｓ１」とも呼ぶ）には、カラーフィルタ層１８、及びマイクロレンズアレイ１９がこの順に配置されている。さらに、受光層１７の半導体基板１２側の面（以下、「表面Ｓ２」とも呼ぶ）には、配線層２０が配置されている。 [1-2 Main part configuration]
Next, the detailed structure of the solid-state imaging device 1 will be explained. FIG. 2 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 taken along line AA in FIG. Further, FIG. 3 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 when region B in FIG. 2 is enlarged.
As shown in FIGS. 2 and 3, the solid-state imaging device 1 includes a semiconductor substrate 12, a fixed charge film 13 (“functional layer” in a broad sense), an insulating film 14, a light shielding film 15, and a planarization film 16 stacked in this order. A light-receiving layer 17 is disposed. Further, on the surface of the light-receiving layer 17 on the flattening film 16 side (hereinafter also referred to as "back surface S1"), a color filter layer 18 and a microlens array 19 are arranged in this order. Further, a wiring layer 20 is arranged on the surface of the light-receiving layer 17 on the semiconductor substrate 12 side (hereinafter also referred to as "surface S2").
　半導体基板１２は、例えば、シリコン（Si）によって構成されている。半導体基板１２には、各画素８の領域それぞれに光電変換部２１が形成されている。即ち、半導体基板１２には、複数の光電変換部２１が二次元アレイ状に配置されている。光電変換部２１には、半導体基板１２の光入射面（以下、「裏面Ｓ３」とも呼ぶ）側及び表面Ｓ２側のそれぞれに、Ｐ型の不純物を含むＰ型半導体領域２２と、Ｐ型の不純物を含むＰ型半導体領域２４とが形成されている。また、Ｐ型半導体領域２２とＰ型半導体領域２４との間には、光電変換部２１の周囲を囲む半導体層２７と接するように、半導体基板１２の厚さ方向に連続するＮ型半導体領域２３が形成されている。即ち、光電変換部２１は、半導体層２７と接する領域にＮ型半導体領域２３を有している。半導体層２７は、光電変換部２１間に形成されるトレンチ部２５の側壁面Ｓ４を被覆する層である。Ｐ型の不純物としては、例えば、ボロン(B)を採用できる。また、Ｎ型の不純物としては、例えば、リン（P）、ヒ素(As)を採用できる。光電変換部２１は、Ｐ型半導体領域２２とＮ型半導体領域２３との接合面、及びＰ型半導体領域２４とＮ型半導体領域２３との接合面のＰＮ接合によってフォトダイオードを構成する。そして、光電変換を行って、受光量に応じた電荷を生成する。また、光電変換部２１は、Ｎ型半導体領域２３に光電変換で生成した電荷を蓄積する。 The semiconductor substrate 12 is made of silicon (Si), for example. A photoelectric conversion section 21 is formed in each region of each pixel 8 on the semiconductor substrate 12 . That is, a plurality of photoelectric conversion units 21 are arranged in a two-dimensional array on the semiconductor substrate 12. The photoelectric conversion unit 21 includes a P-type semiconductor region 22 containing a P-type impurity, and a P-type semiconductor region 22 containing a P-type impurity on the light incident surface (hereinafter also referred to as "back surface S3") side and the front surface S2 side of the semiconductor substrate 12, respectively. A P-type semiconductor region 24 is formed. Further, between the P-type semiconductor region 22 and the P-type semiconductor region 24, an N-type semiconductor region 23 that is continuous in the thickness direction of the semiconductor substrate 12 is in contact with the semiconductor layer 27 surrounding the photoelectric conversion section 21. is formed. That is, the photoelectric conversion section 21 has an N-type semiconductor region 23 in a region in contact with the semiconductor layer 27 . The semiconductor layer 27 is a layer that covers the side wall surface S4 of the trench section 25 formed between the photoelectric conversion sections 21. For example, boron (B) can be used as the P-type impurity. Further, as the N-type impurity, for example, phosphorus (P) or arsenic (As) can be used. The photoelectric conversion section 21 constitutes a photodiode by a PN junction between a junction surface between the P-type semiconductor region 22 and the N-type semiconductor region 23 and a junction surface between the P-type semiconductor region 24 and the N-type semiconductor region 23. Then, photoelectric conversion is performed to generate charges according to the amount of received light. Further, the photoelectric conversion unit 21 accumulates charges generated by photoelectric conversion in the N-type semiconductor region 23 .
　また、Ｎ型半導体領域２３は、図３及び図４に示すように、光電変換部２１の中央部側よりもトレンチ部２５側でＮ型の不純物濃度が高くなっており、トレンチ部２５（半導体層２７）とＮ型半導体領域２３との界面において、Ｎ型の不純物濃度のピークを有している。これにより、Ｎ型半導体領域２３内において、界面付近のＮ型の不純物濃度を高くすることができ、光電変換部２１に蓄積できる電荷量（即ち、飽和電荷量Ｑs）を増大できる。図３では、Ｎ型半導体領域２３は、Ｎ型の不純物濃度が大きいところほど濃い色で表している。また、図３では、Ｎ型半導体領域２３に重ねてＮ型の不純物濃度を示す曲線を破線で示している。図４は、図３のＣ－Ｃ線の位置におけるＮ型の不純物濃度の分布を示す図である。また、Ｎ型半導体領域２３は、半導体基板１２の厚さ方向において、Ｎ型の不純物濃度が一定となっている。それゆえ、トレンチ部２５（半導体層２７）とＮ型半導体領域２３との界面におけるＮ型の不純物濃度のピークは、半導体基板１２の厚さ方向に連続している。これにより、半導体基板１２の裏面Ｓ３側に蓄積できる電荷量及び表面Ｓ２側に蓄積できる電荷量のそれぞれを増加でき、飽和電荷量Ｑsをより増大できる。なお、図４に示したＮ型半導体領域２３及び半導体層２７の不純物濃度の分布は、例えば、Nano-SIMS（Secondary Ion Mass Spectrometry）で解析を行うことで取得できる。 Further, as shown in FIGS. 3 and 4, in the N-type semiconductor region 23, the N-type impurity concentration is higher on the trench portion 25 side than on the central portion side of the photoelectric conversion section 21, and the N-type impurity concentration is higher on the trench portion 25 (semiconductor The N-type impurity concentration has a peak at the interface between the layer 27) and the N-type semiconductor region 23. Thereby, in the N-type semiconductor region 23, the N-type impurity concentration near the interface can be increased, and the amount of charge that can be accumulated in the photoelectric conversion section 21 (ie, the saturated charge amount Qs) can be increased. In FIG. 3, in the N-type semiconductor region 23, the higher the N-type impurity concentration, the darker the color. Further, in FIG. 3, a curve indicating the N-type impurity concentration is shown by a broken line, superimposed on the N-type semiconductor region 23. FIG. 4 is a diagram showing the distribution of N-type impurity concentration at the position of line CC in FIG. Further, the N-type semiconductor region 23 has a constant N-type impurity concentration in the thickness direction of the semiconductor substrate 12. Therefore, the peak of the N-type impurity concentration at the interface between the trench portion 25 (semiconductor layer 27) and the N-type semiconductor region 23 is continuous in the thickness direction of the semiconductor substrate 12. Thereby, the amount of charge that can be stored on the back surface S3 side of the semiconductor substrate 12 and the amount of charge that can be stored on the front surface S2 side can be increased, and the saturated charge amount Qs can be further increased. Note that the impurity concentration distribution of the N-type semiconductor region 23 and the semiconductor layer 27 shown in FIG. 4 can be obtained by, for example, analyzing with Nano-SIMS (Secondary Ion Mass Spectrometry).
　また、半導体基板１２には、隣り合う光電変換部２１間にトレンチ部２５が形成されている。トレンチ部２５は、光電変換部２１の側面に沿うように、半導体基板１２の表面Ｓ２から裏面Ｓ３まで形成されている。即ち、トレンチ部２５は、光電変換部２１それぞれを囲むように、半導体基板１２に格子状に形成されている。また、トレンチ部２５は、半導体層２７、固定電荷膜１３及び絶縁膜１４と一緒に素子分離部２６を形成している。
　トレンチ部２５の内部には、トレンチ部２５の側壁面Ｓ４を被覆する半導体層２７が配置されている。半導体層２７は、半導体基板１２の厚さ方向から見た場合に、光電変換部２１それぞれを囲むように形成されている。半導体層２７としては、例えば、ノンドープのエピタキシャル成長層等、半導体基板１２と異なるタイミングで形成されたノンドープの半導体層を採用できる。エピタキシャル成長層は、半導体結晶をエピタキシャル成長させて形成される半導体層である。このようなエピタキシャル成長層を用いることにより、半導体層２７のＰ型の不純物濃度は、１ｅ１６/ｃｍ3以下（低い数値）となっている。Ｐ型の不純物濃度を低くしたことにより、図３に示すように、半導体層２７は、半導体層２７から光電変換部２１内へのＰ型の不純物の拡散を抑制でき、光電変換部２１内のＮ型半導体領域２３の侵食を抑制できる。それゆえ、光電変換部２１の飽和電荷量Ｑsの低下を抑制できる。即ち、光電変換部２１の飽和電荷量Ｑsを向上することができる。 Furthermore, a trench portion 25 is formed in the semiconductor substrate 12 between adjacent photoelectric conversion portions 21 . The trench portion 25 is formed along the side surface of the photoelectric conversion portion 21 from the front surface S2 to the back surface S3 of the semiconductor substrate 12. That is, the trench portions 25 are formed in a grid pattern on the semiconductor substrate 12 so as to surround each of the photoelectric conversion portions 21 . Further, the trench portion 25 forms an element isolation portion 26 together with the semiconductor layer 27, the fixed charge film 13, and the insulating film 14.
Inside the trench portion 25, a semiconductor layer 27 is arranged to cover the side wall surface S4 of the trench portion 25. The semiconductor layer 27 is formed to surround each of the photoelectric conversion parts 21 when viewed from the thickness direction of the semiconductor substrate 12. As the semiconductor layer 27, for example, a non-doped semiconductor layer formed at a different timing from the semiconductor substrate 12, such as a non-doped epitaxial growth layer, can be used. The epitaxial growth layer is a semiconductor layer formed by epitaxially growing a semiconductor crystal. By using such an epitaxial growth layer, the P-type impurity concentration of the semiconductor layer 27 is 1e16/cm 3 or less (low value). By lowering the P-type impurity concentration, the semiconductor layer 27 can suppress the diffusion of P-type impurities from the semiconductor layer 27 into the photoelectric conversion section 21, as shown in FIG. Erosion of the N-type semiconductor region 23 can be suppressed. Therefore, a decrease in the saturation charge amount Qs of the photoelectric conversion section 21 can be suppressed. That is, the saturation charge amount Qs of the photoelectric conversion section 21 can be improved.
　また、図４に示すように、半導体層２７の面のうちの、トレンチ部２５の側壁面Ｓ４から遠い側の面（以下「内部側面Ｓ５」とも呼ぶ）側において、半導体層２７のＮ型の不純物濃度は、１ｅ１６/ｃｍ3以下とした。後述するように、固体撮像装置１の製造時には、半導体層２７として不純物濃度が１ｅ１６/ｃｍ3以下の半導体層（例えば、エピタキシャル成長層）を形成する。そのため、半導体層２７内のＮ型の不純物は、ほぼすべてＮ型半導体領域２３から拡散されたものである。そのため、半導体層２７のＮ型の不純物濃度（１ｅ１６/ｃｍ3以下）は、Ｎ型半導体領域２３や半導体層２７の厚さ等を調整することで実現される。半導体層２７の層厚（膜厚）としては、例えば、１０ｎｍ以上を採用できる。Ｎ型の不純物濃度を低くしたことにより、後述するように、半導体層２７の内部側面Ｓ５側に、固定電荷膜１３によってホール誘起層２７ａを形成できる。半導体層２７の材料としては、例えば、半導体基板１２と同じ材料（例えば、シリコン(Si)）を採用できる。 Further, as shown in FIG. 4, on the side of the semiconductor layer 27 that is far from the side wall surface S4 of the trench portion 25 (hereinafter also referred to as "inner side surface S5"), the N-type of the semiconductor layer 27 is The impurity concentration was 1e16/cm 3 or less. As will be described later, when manufacturing the solid-state imaging device 1, a semiconductor layer (for example, an epitaxially grown layer) with an impurity concentration of 1e16/cm 3 or less is formed as the semiconductor layer 27. Therefore, almost all of the N-type impurities in the semiconductor layer 27 are diffused from the N-type semiconductor region 23. Therefore, the N-type impurity concentration (1e16/cm 3 or less) of the semiconductor layer 27 is achieved by adjusting the thickness of the N-type semiconductor region 23 and the semiconductor layer 27, etc. As the layer thickness (film thickness) of the semiconductor layer 27, for example, 10 nm or more can be adopted. By lowering the N-type impurity concentration, the hole inducing layer 27a can be formed by the fixed charge film 13 on the inner side surface S5 side of the semiconductor layer 27, as described later. As the material of the semiconductor layer 27, for example, the same material as the semiconductor substrate 12 (for example, silicon (Si)) can be used.
　また、半導体層２７の内部側面Ｓ５は、固定電荷膜１３で被覆されている。即ち、固定電荷膜１３は、半導体層２７で被覆されたトレンチ部２５の内部の空間に、半導体層２７の内部側面Ｓ５に沿って配置されている。固定電荷膜１３の材料としては、例えば、半導体層２７上に堆積することで、負の固定電荷を発生させてピニングを実現させることが可能な材料を採用できる。例えば、負の固定電荷を有する高屈折率材料膜又は高誘電体膜を採用できる。具体的には、アルミニウム（Al）、ハフニウム（Hf）、タンタル（Ta）、ジルコニウム（Zr）及びチタン（Ti）の少なくとも１つの元素を含む酸化物又は窒化物（Al2O3、HfO2、Ta2O5等）が挙げられる。これにより、図３に示すように、固定電荷膜１３によって、半導体層２７の固定電荷膜１３側（内部側面Ｓ５側）にホール（正孔）を誘起させて高ホール濃度状態の部分（以下、「ホール誘起層２７ａ」とも呼ぶ）が形成され、トレンチ部２５の側壁のピニングが実現される。このピニングによって、トレンチ部２５の側壁で発生する暗電流を抑制することができる。即ち、固定電荷膜１３は、半導体層２７の固定電荷膜１３側（内部側面Ｓ５側）にホールを誘起させる層である、と言える。
　また、半導体層２７及び固定電荷膜１３で被覆されたトレンチ部２５の内部の溝状の空間には、絶縁膜１４が埋め込まれている。絶縁膜１４の材料としては、例えば、酸化シリコン（SiO2）、窒化シリコン（SiN）を採用できる。これに２５より、絶縁膜１４によって、隣接する光電変換部２１間において、一方の光電変換部２１で光電変換された電荷が他方の光電変換部２１へ移動するクロストークによる電気的混色の発生が抑制される。 Further, the inner side surface S5 of the semiconductor layer 27 is covered with the fixed charge film 13. That is, the fixed charge film 13 is arranged in a space inside the trench portion 25 covered with the semiconductor layer 27, along the inner side surface S5 of the semiconductor layer 27. As a material for the fixed charge film 13, for example, a material that can be deposited on the semiconductor layer 27 to generate negative fixed charges and realize pinning can be used. For example, a high refractive index material film or a high dielectric constant film having a negative fixed charge can be used. Specifically, oxides or nitrides (Al 2 O 3 , HfO 2 , Ta 2 O 5 , etc.). As a result, as shown in FIG. 3, holes are induced by the fixed charge film 13 on the fixed charge film 13 side (inner side surface S5 side) of the semiconductor layer 27, and a high hole concentration state (hereinafter referred to as A hole inducing layer 27a (also referred to as a "hole inducing layer 27a") is formed, and pinning of the sidewalls of the trench portion 25 is realized. By this pinning, dark current generated on the sidewalls of the trench portion 25 can be suppressed. That is, it can be said that the fixed charge film 13 is a layer that induces holes on the fixed charge film 13 side (the inner side surface S5 side) of the semiconductor layer 27.
Further, an insulating film 14 is embedded in a groove-shaped space inside the trench portion 25 covered with the semiconductor layer 27 and the fixed charge film 13. As the material of the insulating film 14, for example, silicon oxide (SiO 2 ) or silicon nitride (SiN) can be used. 25, the insulating film 14 prevents the occurrence of electrical color mixing between adjacent photoelectric conversion units 21 due to crosstalk in which charges photoelectrically converted in one photoelectric conversion unit 21 move to the other photoelectric conversion unit 21. suppressed.
　固定電荷膜１３は、半導体層２７と一緒に、トレンチ部２５の底面及び半導体基板１２の裏面Ｓ３も被覆している。また、絶縁膜１４は、トレンチ部２５内への埋め込みと一緒に、固定電荷膜１３の光入射面（以下「裏面Ｓ７」とも呼ぶ）の被覆も行っている。
　遮光膜１５は、絶縁膜１４の光入射面（以下、「裏面Ｓ８」とも呼ぶ）側に配置され、光電変換部２１それぞれの光入射面を開口するように形成されている。遮光膜１５の材料としては、例えば、アルミニウム（Al）、タングステン（W）、銅（Cu）を採用できる。
　平坦化膜１６は、絶縁膜１４の裏面Ｓ８側に配置され、受光層１７の裏面Ｓ１側が平坦面となるように、裏面Ｓ８及び遮光膜１５を連続的に被覆している。絶縁膜１４の材料としては、例えば、酸化シリコン（SiO2）、窒化シリコン（SiN）を採用できる。 The fixed charge film 13 covers the bottom surface of the trench portion 25 and the back surface S3 of the semiconductor substrate 12 together with the semiconductor layer 27. Further, the insulating film 14 not only fills the trench portion 25 but also covers the light incident surface (hereinafter also referred to as "back surface S7") of the fixed charge film 13.
The light shielding film 15 is disposed on the light incident surface (hereinafter also referred to as "back surface S8") side of the insulating film 14, and is formed so as to open the light incident surface of each of the photoelectric conversion sections 21. As a material for the light shielding film 15, for example, aluminum (Al), tungsten (W), or copper (Cu) can be used.
The planarization film 16 is disposed on the back surface S8 side of the insulating film 14, and continuously covers the back surface S8 and the light shielding film 15 so that the back surface S1 side of the light-receiving layer 17 becomes a flat surface. As the material of the insulating film 14, for example, silicon oxide (SiO 2 ) or silicon nitride (SiN) can be used.
　カラーフィルタ層１８は、平坦化膜１６の裏面Ｓ１側に形成され、光電変換部２１に対応して配置されたカラーフィルタ２８を複数有している。即ち、１つの光電変換部２１に対して１つのカラーフィルタ２８が形成されている。複数のカラーフィルタ２８には、マイクロレンズ２９が集光した光に含まれる所定波長の光を透過させる複数種類のカラーフィルタが含まれている。これにより、カラーフィルタ２８のそれぞれは、カラーフィルタ２８に応じた所定波長の光を透過し、透過した光を光電変換部２１に入射させる。
　マイクロレンズアレイ１９は、カラーフィルタ層１８の裏面Ｓ９側（受光面側）に形成され、光電変換部２１に対応して配置されたマイクロレンズ２９を複数有している。即ち、１つの光電変換部２１に対して１つのマイクロレンズ２９が形成されている。これにより、マイクロレンズ２９それぞれは、被写体からの像光（入射光）を集光し、集光した入射光を、カラーフィルタ２８を介して、対応する光電変換部２１内に入射させる。
　配線層２０は、半導体基板１２の表面Ｓ２側に配置されている。配線層２０は、層間絶縁膜と、層間絶縁膜を介して複数層に積層された配線（不図示）とを有している。そして、配線層２０は、複数層の配線を介して、各画素８の画素トランジスタを駆動する。 The color filter layer 18 is formed on the back surface S1 side of the planarizing film 16, and includes a plurality of color filters 28 arranged corresponding to the photoelectric conversion sections 21. That is, one color filter 28 is formed for one photoelectric conversion section 21. The plurality of color filters 28 include a plurality of types of color filters that transmit light of a predetermined wavelength included in the light condensed by the microlens 29. As a result, each of the color filters 28 transmits light of a predetermined wavelength corresponding to the color filter 28, and the transmitted light is incident on the photoelectric conversion unit 21.
The microlens array 19 is formed on the back surface S9 side (light receiving surface side) of the color filter layer 18, and has a plurality of microlenses 29 arranged corresponding to the photoelectric conversion sections 21. That is, one microlens 29 is formed for one photoelectric conversion section 21. Thereby, each of the microlenses 29 collects image light (incident light) from the subject, and causes the collected incident light to enter the corresponding photoelectric conversion unit 21 via the color filter 28.
The wiring layer 20 is arranged on the surface S2 side of the semiconductor substrate 12. The wiring layer 20 includes an interlayer insulating film and wiring (not shown) stacked in multiple layers with the interlayer insulating film interposed therebetween. The wiring layer 20 drives the pixel transistor of each pixel 8 via multiple layers of wiring.
　以上の構成を有する固体撮像装置１では、半導体基板１２の裏面Ｓ３側から光が照射され、照射された光がマイクロレンズ２９及びカラーフィルタ２８を透過し、透過した光が光電変換部２１で光電変換されて信号電荷が生成される。そして、生成された信号電荷が、配線層２０の配線で形成された図１の垂直信号線１０から画素信号として出力される。
　また、固体撮像装置１では、固定電荷膜１３によって、半導体層２７の固定電荷膜１３側にホール誘起層２７ａが形成され、トレンチ部２５の側壁のピニングが実現される。そして、このピニングによって、トレンチ部２５の側壁で発生する暗電流が抑制される。 In the solid-state imaging device 1 having the above configuration, light is irradiated from the back surface S3 side of the semiconductor substrate 12, the irradiated light is transmitted through the microlens 29 and the color filter 28, and the transmitted light is photoelectrically converted by the photoelectric conversion unit 21. The signal charge is generated by conversion. The generated signal charge is then output as a pixel signal from the vertical signal line 10 of FIG. 1 formed by the wiring of the wiring layer 20.
Further, in the solid-state imaging device 1, the hole inducing layer 27a is formed on the fixed charge film 13 side of the semiconductor layer 27 by the fixed charge film 13, and pinning of the side wall of the trench portion 25 is realized. This pinning suppresses dark current generated on the sidewalls of the trench portion 25.
　ここで、例えば、図５に示すように、半導体層２７がＰ型の不純物濃度が比較的高いＰ＋型の半導体層２７である場合には、Ｐ＋型の半導体層２７から光電変換部２１内にＰ型の不純物が拡散し、光電変換部２１内のＮ型半導体領域２３が侵食される可能性があった。図５では、Ｐ型の不純物に侵食され、Ｎ型半導体領域２３の幅がＷ1からＷ2に減少した場合を例示している。それゆえ、光電変換部２１の飽和電荷量Ｑsが低下する可能性があった。図５では、Ｐ型の不純物濃度が大きいところほど濃い色で表している。また図５では、Ｐ＋型の半導体層２７に重ねてＰ型の不純物濃度を示す曲線を破線で示している。
　また、固体撮像装置１を多画素化させる場合、画素８を微細化することになる。しかし、図５に示した固体撮像装置１において、画素８を微細化した場合、上記したＰ型の不純物の拡散によるＮ型半導体領域２３の減少に加え、画素８の微細化によるＮ型半導体領域２３の減少も生じるため、必要な飽和電荷量Ｑsの確保が困難となる可能性があった。 Here, for example, as shown in FIG. 5, when the semiconductor layer 27 is a P+ type semiconductor layer 27 with a relatively high P type impurity concentration, there is a There was a possibility that the P-type impurity would diffuse and the N-type semiconductor region 23 within the photoelectric conversion section 21 would be eroded. FIG. 5 illustrates a case where the width of the N-type semiconductor region 23 is reduced from W 1 to W 2 due to erosion by P-type impurities. Therefore, there was a possibility that the saturation charge amount Qs of the photoelectric conversion section 21 would decrease. In FIG. 5, the higher the P-type impurity concentration, the darker the color. Further, in FIG. 5, a curve indicating the P-type impurity concentration is shown by a broken line superimposed on the P+-type semiconductor layer 27.
Moreover, when increasing the number of pixels in the solid-state imaging device 1, the pixels 8 are made smaller. However, when the pixel 8 is miniaturized in the solid-state imaging device 1 shown in FIG. 23 also occurs, which may make it difficult to secure the necessary saturation charge amount Qs.
　これに対し、第１の実施形態に係る固体撮像装置１では、図３に示すように、半導体層２７は、Ｐ型の不純物濃度が１ｅ１６/ｃｍ3以下となるように構成した。それゆえ、半導体層２７から光電変換部２１内へのＰ型の不純物の拡散を抑制でき、光電変換部２１内のＮ型半導体領域２３の侵食を抑制できる。図３では、Ｐ型の不純物に侵食されず、Ｎ型半導体領域２３の幅がＷ1に維持された場合を例示している。そのため、光電変換部２１に蓄積できる電荷量（飽和電荷量Ｑs）の低下を抑制できる。即ち、光電変換部２１の飽和電荷量Ｑsを向上することができる。また、画素８を微細化させた場合においても、Ｐ型の不純物の拡散によるＮ型半導体領域２３の減少を生じないため、必要な飽和電荷量Ｑsを確保でき、固体撮像装置１の多画素化を比較的容易に実現することができる。 In contrast, in the solid-state imaging device 1 according to the first embodiment, as shown in FIG. 3, the semiconductor layer 27 is configured to have a P-type impurity concentration of 1e16/cm 3 or less. Therefore, diffusion of P-type impurities from the semiconductor layer 27 into the photoelectric conversion section 21 can be suppressed, and erosion of the N-type semiconductor region 23 within the photoelectric conversion section 21 can be suppressed. FIG. 3 illustrates a case where the width of the N-type semiconductor region 23 is maintained at W 1 without being corroded by P-type impurities. Therefore, it is possible to suppress a decrease in the amount of charge that can be accumulated in the photoelectric conversion section 21 (the amount of saturated charge Qs). That is, the saturation charge amount Qs of the photoelectric conversion section 21 can be improved. Furthermore, even when the pixels 8 are miniaturized, the N-type semiconductor region 23 does not decrease due to the diffusion of P-type impurities, so the necessary saturation charge amount Qs can be secured, and the solid-state imaging device 1 can have a large number of pixels. can be realized relatively easily.
［１－３　固体撮像装置の製造方法］
　次に、第１の実施形態に係る固体撮像装置１の製造方法について説明する。
　まず、図６Ａに示すように、半導体基板１２の表面Ｓ２に対して、トレンチ部２５を形成する位置に開口を有するマスク３０を形成する。続いて、マスク３０を介して異方性のドライエッチングを行って、トレンチ部２５を形成する。このように、トレンチ部２５の形成をＦＥＯＬ工程（Front-End-Of-Line工程）で行うことにより、後の工程で行われる熱処理を利用して、トレンチ部２５の形成時の加工ダメージを回復させることができ、白点・暗電流を抑制できる。続いて、トレンチ部２５の側壁面Ｓ４にコンフォーマルドーピング(Conformal Doping)技術を用いて、図６Ｂに示すように、光電変換部２１のＮ型半導体領域２３を形成する。上記のように、トレンチ部２５の形成をＦＥＯＬ工程で行ったため、Ｎ型半導体領域２３の形成には、トレンチ部２５の内部側からＮ型の不純物を導入するプロセスを適用できる。Ｎ型の不純物をドープする方法としては、例えば、固相拡散法、プラズマドーピング、イオンインプラント注入法を採用できる。なお、図６Ｂでは、Ｎ型半導体領域２３のうち、図３で濃い色で表した部分のみ（Ｎ型の不純物濃度が大きい部分のみ）をドットで表現している。また、図６Ｃ～図６Ｈでも同様の表現を用いた。 [1-3 Method for manufacturing solid-state imaging device]
Next, a method for manufacturing the solid-state imaging device 1 according to the first embodiment will be described.
First, as shown in FIG. 6A, a mask 30 having an opening at a position where the trench portion 25 is to be formed is formed on the surface S2 of the semiconductor substrate 12. Subsequently, anisotropic dry etching is performed through the mask 30 to form the trench portion 25. In this way, by forming the trench portion 25 in the FEOL process (Front-End-Of-Line process), the processing damage during the formation of the trench portion 25 can be recovered using the heat treatment performed in the later process. white spots and dark current can be suppressed. Subsequently, the N-type semiconductor region 23 of the photoelectric conversion section 21 is formed on the side wall surface S4 of the trench section 25 using a conformal doping technique, as shown in FIG. 6B. As described above, since the trench portion 25 is formed by the FEOL process, the N-type semiconductor region 23 can be formed by a process of introducing N-type impurities from the inside of the trench portion 25. As a method for doping with N-type impurities, for example, solid phase diffusion, plasma doping, and ion implantation can be used. Note that in FIG. 6B, only the portions of the N-type semiconductor region 23 shown in dark colors in FIG. 3 (only the portions where the N-type impurity concentration is high) are expressed with dots. Further, similar expressions were used in FIGS. 6C to 6H.
　続いて、図６Ｃに示すように、トレンチ部２５の側壁面Ｓ４に半導体結晶（例えば、シリコン(Si)）をエピタキシャル成長させ、トレンチ部２５の側壁面Ｓ４及び底面を被覆するように、トレンチ部２５内に半導体層２７を形成する。半導体層２７としては、不純物濃度が１ｅ１６/ｃｍ3以下のエピタキシャル成長層を形成する。続いて、図６Ｄに示すように、半導体層２７で被覆されたトレンチ部２５の内部の空間に酸化シリコン(SiO)３１及びドープドポリシリコン３２をこの順に埋め込む。続いて、図６Ｅに示すように、半導体基板１２の表面Ｓ２側に配線層２０を形成する。続いて、半導体基板１２と配線層２０とを含んで構成されるセンサ基板と、図示しないロジック基板とを接合した後、ＣＭＰ技術を用いて、図６Ｆに示すように半導体基板１２を裏面Ｓ３側から研磨して薄肉化する。
　続いて、図６Ｇに示すように、トレンチ部２５内から酸化シリコン３１及びドープドポリシリコン３２を除去する。続いて、図６Ｈに示すように、トレンチ部２５内に固定電荷膜１３及び絶縁膜１４をこの順に形成する。続いて、図２に示すように、絶縁膜１４の裏面Ｓ８に遮光膜１５、平坦化膜１６、カラーフィルタ層１８及びマイクロレンズアレイ１９をこの順に形成する。これにより第１の実施形態に係る固体撮像装置１が製造される。 Subsequently, as shown in FIG. 6C, a semiconductor crystal (for example, silicon (Si)) is epitaxially grown on the side wall surface S4 of the trench portion 25, and the trench portion 25 is grown so as to cover the side wall surface S4 and the bottom surface of the trench portion 25. A semiconductor layer 27 is formed inside. As the semiconductor layer 27, an epitaxially grown layer having an impurity concentration of 1e16/cm 3 or less is formed. Subsequently, as shown in FIG. 6D, silicon oxide (SiO) 31 and doped polysilicon 32 are embedded in this order into the space inside the trench portion 25 covered with the semiconductor layer 27. Subsequently, as shown in FIG. 6E, a wiring layer 20 is formed on the surface S2 side of the semiconductor substrate 12. Subsequently, after bonding the sensor substrate including the semiconductor substrate 12 and the wiring layer 20 and the logic substrate (not shown), the semiconductor substrate 12 is bonded to the back surface S3 side as shown in FIG. 6F using CMP technology. Polish it to make it thinner.
Subsequently, as shown in FIG. 6G, silicon oxide 31 and doped polysilicon 32 are removed from within trench portion 25. Subsequently, as shown in FIG. 6H, the fixed charge film 13 and the insulating film 14 are formed in this order within the trench portion 25. Subsequently, as shown in FIG. 2, a light shielding film 15, a planarization film 16, a color filter layer 18, and a microlens array 19 are formed in this order on the back surface S8 of the insulating film 14. In this way, the solid-state imaging device 1 according to the first embodiment is manufactured.
［１－４　変形例］
（１）なお、第１の実施形態では、半導体層３７を、センサ基板とロジック基板との接合や、半導体基板１２の薄肉化を行う前の工程（ＦＥＯＬ工程）で形成する例を示したが、他の構成を採用することもできる。例えば、ＦＥＯＬ工程後に形成する構成としてもよい。例えば、まず、上記した図６Ａ及び図６Ｂに示した工程を行った後、図７Ａに示すように、トレンチ部２５の内部の空間に酸化シリコン(SiO)３１及びドープドポリシリコン３２をこの順に埋め込む。続いて、図７Ｂに示すように、半導体基板１２の表面Ｓ２側に配線層２０を形成する。続いて、半導体基板１２と配線層２０とを含むセンサ基板と、図示しないロジック基板とを接合した後、ＣＭＰ(Chemical Mechanical Polishing)技術を用いて、図７Ｃに示すように、半導体基板１２を裏面Ｓ３側から研磨して薄肉化する。 [1-4 Modification example]
(1) In the first embodiment, an example was shown in which the semiconductor layer 37 is formed in a process (FEOL process) before joining the sensor substrate and the logic board or thinning the semiconductor substrate 12. , other configurations may also be adopted. For example, it may be formed after the FEOL process. For example, first, after performing the steps shown in FIGS. 6A and 6B, as shown in FIG. 7A, silicon oxide (SiO) 31 and doped polysilicon 32 are placed in the space inside the trench portion 25 in this order. Embed. Subsequently, as shown in FIG. 7B, a wiring layer 20 is formed on the surface S2 side of the semiconductor substrate 12. Subsequently, after bonding the sensor substrate including the semiconductor substrate 12 and the wiring layer 20 to a logic substrate (not shown), the back surface of the semiconductor substrate 12 is polished using CMP (Chemical Mechanical Polishing) technology, as shown in FIG. 7C. Polish from the S3 side to make it thinner.
　続いて、図７Ｄに示すように、トレンチ部２５内から酸化シリコン(SiO)３１及びドープドポリシリコン３２を除去する。続いて、図６Ｇに示すように、トレンチ部２５の側壁面Ｓ４に半導体結晶（例えば、シリコン(Si)）をエピタキシャル成長させ、トレンチ部２５の側壁面Ｓ４及び底面を被覆するように、トレンチ部２５内に半導体層２７を形成する。続いて、図６Ｈに示すように、トレンチ部２５内に固定電荷膜１３及び絶縁膜１４をこの順に形成する。続いて、図２に示すように、絶縁膜１４の裏面Ｓ８に遮光膜１５、平坦化膜１６、カラーフィルタ層１８及びマイクロレンズアレイ１９をこの順に形成する。 Subsequently, as shown in FIG. 7D, silicon oxide (SiO) 31 and doped polysilicon 32 are removed from inside the trench portion 25. Subsequently, as shown in FIG. 6G, a semiconductor crystal (for example, silicon (Si)) is epitaxially grown on the side wall surface S4 of the trench portion 25, and the trench portion 25 is grown so as to cover the side wall surface S4 and the bottom surface of the trench portion 25. A semiconductor layer 27 is formed inside. Subsequently, as shown in FIG. 6H, the fixed charge film 13 and the insulating film 14 are formed in this order within the trench portion 25. Subsequently, as shown in FIG. 2, a light shielding film 15, a planarization film 16, a color filter layer 18, and a microlens array 19 are formed in this order on the back surface S8 of the insulating film 14.
〈２．第２の実施形態：固体撮像装置〉
［２－１　要部の構成］
　次に、本開示の第２の実施形態に係る固体撮像装置１について説明する。第２の実施形態に係る固体撮像装置１の全体構成は、図１と同様であるから図示を省略する。図８は、第２の実施形態に係る固体撮像装置１の断面構成を示す図である。また、図９は、図８の領域Ｄを拡大した場合の、固体撮像装置１の断面構成を示す図である。図８、図９において、図２、図３に対応する部分には同一符号を付し重複説明を省略する。 <2. Second embodiment: solid-state imaging device>
[2-1 Configuration of main parts]
Next, a solid-state imaging device 1 according to a second embodiment of the present disclosure will be described. The overall configuration of the solid-state imaging device 1 according to the second embodiment is the same as that in FIG. 1, so illustration thereof is omitted. FIG. 8 is a diagram showing a cross-sectional configuration of a solid-state imaging device 1 according to the second embodiment. Further, FIG. 9 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 when region D in FIG. 8 is enlarged. In FIGS. 8 and 9, parts corresponding to those in FIGS. 2 and 3 are denoted by the same reference numerals, and redundant explanation will be omitted.
　第２の実施形態では、図８及び図９に示すように、トレンチ部２５の内部の空間に、図２に示した固定電荷膜１３及び絶縁膜１４に代えて、絶縁膜３３及び負のバイアス電圧が印加される導体部３４がこの順に埋め込まれている点が第１の実施形態と異なっている。
　半導体層２７の内部側面Ｓ５は、絶縁膜３３で被覆されている。これにより、絶縁膜３３によって、導体部３４と光電変換部２１（Ｎ型半導体領域２３）とが絶縁されている。絶縁膜３３の材料としては、例えば酸化シリコン(SiO)、高誘電率絶縁膜を採用できる。
　また、半導体層２７及び絶縁膜３３で被覆されたトレンチ部２５の内部の溝状の空間には、導体部３４が埋め込まれている。即ち、導体部３４は、絶縁膜３３を介して、半導体層２７の内部側面Ｓ５に沿って配置されている。導体部３４の材料としては、例えば、ボロン(B)を添加したポリシリコン、金属材料を採用できる。また、導体部３４には負のバイアス電圧が印加される。これにより、図９に示すように、導体部３４によって、半導体層２７の導体部３４側（内部側面Ｓ５側）にホール（正孔）を誘起させて高ホール濃度状態の部分（ホール誘起層２７ａ）が形成され、トレンチ部２５の側壁のピニングが実現される。このピニングによって、トレンチ部２５の側壁で発生する暗電流を抑制することができる。導体部３４への負のバイアス電圧の印加方法としては、例えば、ロジック基板（不図示）側から給電する方法、半導体基板１２の裏面Ｓ３側から印加する方法が挙げられる。 In the second embodiment, as shown in FIGS. 8 and 9, in place of the fixed charge film 13 and insulating film 14 shown in FIG. This embodiment differs from the first embodiment in that the conductor portions 34 to which voltage is applied are embedded in this order.
An inner side surface S5 of the semiconductor layer 27 is covered with an insulating film 33. Thereby, the conductor section 34 and the photoelectric conversion section 21 (N-type semiconductor region 23) are insulated by the insulating film 33. As a material for the insulating film 33, silicon oxide (SiO) or a high dielectric constant insulating film can be used, for example.
Further, a conductor portion 34 is embedded in a groove-shaped space inside the trench portion 25 covered with the semiconductor layer 27 and the insulating film 33. That is, the conductor portion 34 is arranged along the inner side surface S5 of the semiconductor layer 27 with the insulating film 33 interposed therebetween. As the material of the conductor portion 34, for example, polysilicon doped with boron (B) or a metal material can be used. Further, a negative bias voltage is applied to the conductor portion 34. As a result, as shown in FIG. 9, holes are induced by the conductor part 34 on the conductor part 34 side (inner side surface S5 side) of the semiconductor layer 27, and the high hole concentration state (hole inducing layer 27a ) is formed, and pinning of the side wall of the trench portion 25 is realized. By this pinning, dark current generated on the sidewalls of the trench portion 25 can be suppressed. Examples of methods for applying a negative bias voltage to the conductor portion 34 include a method of supplying power from the logic board (not shown) side and a method of applying it from the back surface S3 side of the semiconductor substrate 12.
［２－２　変形例］
（１）なお、第２の実施形態では、導体部３４を、トレンチ部２５の内部の空間に埋め込む例を示したが、他の構成を採用することもできる。例えば、図１０及び図１１に示すように、導体部３４が、トレンチ部２５の内部に側壁部が導体部３４で形成された溝状の空間を有するように、トレンチ部２５の側壁面Ｓ４を被覆する構成としてもよい。ここで、ポリシリコンは光を吸収する性質を有している。それゆえ、例えば、図８及び図９に示した導体部３４をポリシリコンで形成した場合、つまり、ポリシリコンをトレンチ部２５の内部の空間に埋め込んだ構成（充填した構成）とした場合、量子効率ＱＥが低下する可能性があった。これに対し、本変形例では、トレンチ部２５の内部に溝状の空間を有するように導体部３５を形成する構成とした。そのため、例えば、導体部３４をポリシリコンで形成した場合に、トレンチ部２５の内部の空間の分だけポリシリコンの量を低減でき、ポリシリコンによる光の吸収を抑制できる。その結果、量子効率ＱＥの低下を抑制できる。 [2-2 Modification example]
(1) Although the second embodiment shows an example in which the conductor portion 34 is embedded in the space inside the trench portion 25, other configurations may also be adopted. For example, as shown in FIGS. 10 and 11, the side wall surface S4 of the trench portion 25 is formed so that the conductor portion 34 has a groove-shaped space inside the trench portion 25, the side wall portion of which is formed by the conductor portion 34. It may also be configured to cover. Here, polysilicon has the property of absorbing light. Therefore, for example, when the conductor portion 34 shown in FIGS. 8 and 9 is formed of polysilicon, that is, when the polysilicon is embedded in the space inside the trench portion 25 (filled configuration), the quantum There was a possibility that the efficiency QE would decrease. In contrast, in this modification, the conductor portion 35 is formed so as to have a groove-shaped space inside the trench portion 25. Therefore, for example, when the conductor portion 34 is formed of polysilicon, the amount of polysilicon can be reduced by the space inside the trench portion 25, and light absorption by the polysilicon can be suppressed. As a result, a decrease in quantum efficiency QE can be suppressed.
〈３．第３の実施形態：固体撮像装置〉
［３－１　要部の構成］
　次に、本開示の第３の実施形態に係る固体撮像装置１について説明する。第３の実施形態に係る固体撮像装置１の全体構成は、図１と同様であるから図示を省略する。図１２は、第３の実施形態に係る固体撮像装置１の断面構成を示す図である。また、図１３は、図１２の領域Ｆを拡大した場合の、固体撮像装置１の断面構成を示す図である。図１２、図１３において、図８、図９に対応する部分には同一符号を付し重複説明を省略する。 <3. Third embodiment: solid-state imaging device>
[3-1 Configuration of main parts]
Next, a solid-state imaging device 1 according to a third embodiment of the present disclosure will be described. The overall configuration of the solid-state imaging device 1 according to the third embodiment is the same as that in FIG. 1, so illustration thereof is omitted. FIG. 12 is a diagram showing a cross-sectional configuration of a solid-state imaging device 1 according to the third embodiment. Further, FIG. 13 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 when region F in FIG. 12 is enlarged. In FIGS. 12 and 13, parts corresponding to those in FIGS. 8 and 9 are designated by the same reference numerals, and redundant explanation will be omitted.
　第３の実施形態では、図１２及び図１３に示すように、図８に示した半導体層２７に代えて、Ｐ型固相拡散層３８を用いる点が、第２の実施形態と異なっている。
　Ｐ型固相拡散層３８は、トレンチ部２５内に配置され、トレンチ部２５の側壁面Ｓ４を被覆する層である。Ｐ型固相拡散層３８としては、例えば、ノンドープのエピタキシャル成長層に固相拡散によってＰ型の不純物（例えば、ボロン(B)）を導入して得られる半導体層を採用できる。このような半導体層を用いることにより、図１３に示すように、Ｐ型固相拡散層３８のＮ型の不純物濃度は、１ｅ１６/ｃｍ3以下（低い数値）となっている。Ｎ型の不純物濃度を低くしたことにより、図１４に示すように、Ｐ型固相拡散層３８は、Ｐ型固相拡散層３８とＮ型半導体領域２３とのＰＮ接合によるポテンシャル勾配を急峻化できる。それゆえ、光電変換部２１の飽和電荷量Ｑsを向上することができる。図１３では、Ｎ型半導体領域２３及びＰ型固相拡散層３８に重ねてＮ型の不純物濃度を示す曲線を破線で示し、Ｐ型の不純物濃度を示す曲線を一点鎖線で示している。図１４は、ポテンシャル分布を示す図である。また、図１４では、Ｎ型半導体領域２３及びＰ型固相拡散層３８に重ねてポテンシャル分布を示す曲線を破線で示している。なお、図１３に示したＮ型及びＰ型の不純物濃度の分布は、例えば、Nano-SIMSで解析を行うことで取得できる。 The third embodiment differs from the second embodiment in that, as shown in FIGS. 12 and 13, a P-type solid phase diffusion layer 38 is used instead of the semiconductor layer 27 shown in FIG. .
The P-type solid phase diffusion layer 38 is a layer that is disposed within the trench portion 25 and covers the side wall surface S4 of the trench portion 25. As the P-type solid-phase diffusion layer 38, for example, a semiconductor layer obtained by introducing a P-type impurity (for example, boron (B)) into a non-doped epitaxial growth layer by solid-phase diffusion can be employed. By using such a semiconductor layer, as shown in FIG. 13, the N-type impurity concentration of the P-type solid phase diffusion layer 38 is 1e16/cm 3 or less (a low value). By lowering the N-type impurity concentration, the P-type solid-phase diffusion layer 38 steepens the potential gradient due to the PN junction between the P-type solid-phase diffusion layer 38 and the N-type semiconductor region 23, as shown in FIG. can. Therefore, the saturation charge amount Qs of the photoelectric conversion section 21 can be improved. In FIG. 13, a curve showing the N-type impurity concentration overlapping the N-type semiconductor region 23 and the P-type solid phase diffusion layer 38 is shown by a broken line, and a curve showing the P-type impurity concentration is shown by a dashed line. FIG. 14 is a diagram showing the potential distribution. Moreover, in FIG. 14, a curve showing the potential distribution is shown by a broken line, overlapping the N-type semiconductor region 23 and the P-type solid phase diffusion layer 38. Note that the N-type and P-type impurity concentration distributions shown in FIG. 13 can be obtained by performing analysis using Nano-SIMS, for example.
　また、光電変換部２１は、Ｐ型固相拡散層３８と接する領域にＮ型半導体領域２３を有している。Ｎ型半導体領域２３としては、例えば、半導体基板１２の表面Ｓ２側からＮ型の不純物をイオン注入して得られる半導体領域を用いる。これにより、図１３に示すように、Ｎ型半導体領域２３のＮ型の不純物濃度は表面Ｓ２からの各深さにおいて一定となっている。なお、図１２では図８に示した固定電荷膜１３が省略した場合を例示している。
　また、素子分離部２６の裏面Ｓ３側の部分（以下、「第１素子分離部２６ａ」とも呼ぶ）と、表面Ｓ２側の部分（以下、「第２素子分離部２６ｂ」とも呼ぶ）と、を含んで構成されている。第２素子分離部２６ｂの幅は、第１素子分離部２６ａの幅よりも広く形成されている。また、第２素子分離部２６ｂの内部には、絶縁材料３９が埋め込まれている。 Further, the photoelectric conversion section 21 has an N-type semiconductor region 23 in a region in contact with the P-type solid phase diffusion layer 38 . As the N-type semiconductor region 23, for example, a semiconductor region obtained by ion-implanting N-type impurities from the surface S2 side of the semiconductor substrate 12 is used. Thereby, as shown in FIG. 13, the N-type impurity concentration of the N-type semiconductor region 23 is constant at each depth from the surface S2. Note that FIG. 12 illustrates a case where the fixed charge film 13 shown in FIG. 8 is omitted.
Furthermore, a portion of the element isolation section 26 on the back surface S3 side (hereinafter also referred to as "first element isolation section 26a") and a portion on the front surface S2 side (hereinafter also referred to as "second element isolation section 26b") are It is composed of: The width of the second element isolation part 26b is formed wider than the width of the first element isolation part 26a. Furthermore, an insulating material 39 is embedded inside the second element isolation section 26b.
　ここで、例えば、図１５に示すように、Ｐ型固相拡散層３８に代えて、トレンチ部２５の側壁面Ｓ４からＮ型半導体領域２３内にＰ型の不純物をイオン注入して得られたＰ型半導体領域５５を用いた場合には、Ｐ型半導体領域５５にＮ型の不純物が混ざり、図１６に示すように、Ｐ型半導体領域５５とＮ型半導体領域２３とのＰＮ接合によるポテンシャル勾配が緩やかになる。それゆえ、光電変換部２１の飽和電荷量Ｑsが低下する可能性がある。図１５では、Ｎ型半導体領域２３及びＰ型半導体領域５５に重ねてＮ型の不純物濃度を示す曲線を破線で示し、Ｐ型の不純物濃度を示す曲線を一点鎖線で示している。図１６は、ポテンシャル分布を示す図である。また、図１６では、Ｎ型半導体領域２３及びＰ型半導体領域５５に重ねてポテンシャル分布を示す曲線を破線で示している。 Here, for example, as shown in FIG. 15, instead of the P-type solid phase diffusion layer 38, a P-type impurity is ion-implanted into the N-type semiconductor region 23 from the side wall surface S4 of the trench portion 25. When the P-type semiconductor region 55 is used, N-type impurities are mixed into the P-type semiconductor region 55, and a potential gradient due to the PN junction between the P-type semiconductor region 55 and the N-type semiconductor region 23 is created as shown in FIG. becomes more gradual. Therefore, the saturation charge amount Qs of the photoelectric conversion section 21 may decrease. In FIG. 15, a curve showing the N-type impurity concentration overlapping the N-type semiconductor region 23 and the P-type semiconductor region 55 is shown by a broken line, and a curve showing the P-type impurity concentration is shown by a dashed line. FIG. 16 is a diagram showing the potential distribution. Further, in FIG. 16, a curve showing the potential distribution is shown by a broken line overlapping the N-type semiconductor region 23 and the P-type semiconductor region 55.
　これに対し、第１の実施形態に係る固体撮像装置１では、図１３に示すように、Ｐ型固相拡散層３８は、Ｎ型の不純物濃度が１ｅ１６/ｃｍ3以下とした。それゆえ、Ｐ型固相拡散層３８にＮ型の不純物が混ざることを防止でき、Ｐ型固相拡散層３８とＮ型半導体領域２３とのＰＮ接合によるポテンシャル勾配を急峻化でき、光電変換部２１の飽和電荷量Ｑsを向上することができる。また、画素８を微細化させた場合においても、必要な飽和電荷量Ｑsを確保でき、固体撮像装置１の多画素化を比較的容易に実現することができる。 In contrast, in the solid-state imaging device 1 according to the first embodiment, as shown in FIG. 13, the P-type solid phase diffusion layer 38 has an N-type impurity concentration of 1e16/cm 3 or less. Therefore, it is possible to prevent N-type impurities from being mixed into the P-type solid-phase diffusion layer 38, to steepen the potential gradient due to the PN junction between the P-type solid-phase diffusion layer 38 and the N-type semiconductor region 23, and to make the photoelectric conversion section The saturation charge amount Qs of 21 can be improved. Furthermore, even when the pixels 8 are miniaturized, the necessary saturation charge amount Qs can be ensured, and the solid-state imaging device 1 can be made to have a large number of pixels with relative ease.
［３－２　固体撮像装置の製造方法］
　次に、第３の実施形態に係る固体撮像装置１の製造方法について説明する。
　まず、図１７Ａに示すように、Ｐ型の半導体基板１２を用意し、用意した半導体基板１２の表面Ｓ２側からＮ型の不純物（例えば、リン（P）、ヒ素(As)）をイオン注入し、Ｎ型半導体領域２３を形成する。Ｎ型半導体領域２３は、表面Ｓ２からの各深さにおいて、Ｎ型の不純物濃度が一定となるようにする。続いて、半導体基板１２の表面Ｓ２に対して、トレンチ部２５を形成する位置に開口を有するマスク４０を形成する。マスク４０は、窒化シリコン(SiN)膜４１及び酸化シリコン(SiO)膜４２を積層して構成される。続いて、マスク４０を介して異方性のドライエッチングを行って、トレンチ部２５を形成する。 [3-2 Method for manufacturing solid-state imaging device]
Next, a method for manufacturing the solid-state imaging device 1 according to the third embodiment will be described.
First, as shown in FIG. 17A, a P-type semiconductor substrate 12 is prepared, and N-type impurities (for example, phosphorus (P), arsenic (As)) are ion-implanted from the surface S2 side of the prepared semiconductor substrate 12. , an N-type semiconductor region 23 is formed. The N-type semiconductor region 23 has a constant N-type impurity concentration at each depth from the surface S2. Subsequently, a mask 40 having an opening at a position where the trench portion 25 is to be formed is formed on the surface S2 of the semiconductor substrate 12. The mask 40 is constructed by laminating a silicon nitride (SiN) film 41 and a silicon oxide (SiO) film 42. Subsequently, anisotropic dry etching is performed through the mask 40 to form the trench portion 25.
　続いて、図１７Ｂに示すように、トレンチ部２５の側壁面Ｓ４に半導体結晶（シリコン(Si)）をエピタキシャル成長させ、トレンチ部２５の側壁面Ｓ４及び底面を被覆するように、トレンチ部２５内に半導体層４３を形成する。半導体層４３の形成は、トレンチ部２５の表面Ｓ２側を窒化シリコン膜４１で覆い、第１素子分離部２６ａ（図１２参照）を形成する位置にのみ行う。半導体層４３としては、不純物濃度が１ｅ１６/ｃｍ3以下のノンドープのエピタキシャル成長層を形成する。続いて、図１７Ｃに示すように、固相拡散法を用い、トレンチ部２５内から半導体層４３にＰ型の不純物（例えば、ボロン(B)）をドープして、Ｐ型固相拡散層３８を形成する。即ち、半導体層４３をＰ型固相拡散層３８に変化させる。これにより、Ｐ型固相拡散層３８にＮ型の不純物が混ざることを防止でき、Ｐ型固相拡散層３８のＮ型の不純物の濃度を１ｅ１６/ｃｍ3以下とすることができる。 Subsequently, as shown in FIG. 17B, a semiconductor crystal (silicon (Si)) is epitaxially grown on the side wall surface S4 of the trench portion 25, and a semiconductor crystal (silicon (Si)) is grown in the trench portion 25 so as to cover the side wall surface S4 and the bottom surface of the trench portion 25. A semiconductor layer 43 is formed. The semiconductor layer 43 is formed by covering the surface S2 side of the trench portion 25 with the silicon nitride film 41, and is performed only at the position where the first element isolation portion 26a (see FIG. 12) is to be formed. As the semiconductor layer 43, a non-doped epitaxial growth layer with an impurity concentration of 1e16/cm 3 or less is formed. Subsequently, as shown in FIG. 17C, a P-type impurity (for example, boron (B)) is doped into the semiconductor layer 43 from within the trench portion 25 using a solid-phase diffusion method to form a P-type solid-phase diffusion layer 38. form. That is, the semiconductor layer 43 is changed to the P-type solid phase diffusion layer 38. This can prevent N-type impurities from being mixed into the P-type solid-phase diffusion layer 38, and the concentration of N-type impurities in the P-type solid-phase diffusion layer 38 can be set to 1e16/cm 3 or less.
　続いて、図１７Ｄに示すように、Ｐ型固相拡散層３８で被覆されたトレンチ部２５の内部の空間に酸化シリコン(SiO)４４及びドープドポリシリコン４５をこの順に埋め込む。酸化シリコン４４の埋め込みは、Ｐ型固相拡散層３８の側面を被覆するように行う。またドープドポリシリコン４５の埋め込みは、ドープドポリシリコン４５が、マスク４０の表面Ｓ１０全体を覆うまで行う。続いて、図１７Ｅに示すように、エッチバックを行い、マスク４０の表面Ｓ１０、及びトレンチ部２５内の絶縁材料３９（図１２参照）を埋め込む位置からドープドポリシリコン４５を除去する。続いて、図１７Ｆに示すように、トレンチ部２５の表面Ｓ２側に絶縁材料４６を埋め込む。絶縁材料４６の埋め込みは、絶縁材料４６が、マスク４０の表面Ｓ１０全体を覆うまで行う。続いて、図１７Ｇに示すように、ＣＭＰ技術を用い、絶縁材料４６を表面Ｓ１１側から研磨して、絶縁材料３９を形成する。このような手順により、図１２に示した素子分離部２６を形成する。続いて、図１２に示すように、絶縁膜１４、遮光膜１５、平坦化膜１６、カラーフィルタ層１８及びマイクロレンズアレイ１９を形成する。これにより図１２に示した固体撮像装置１を製造する。 Subsequently, as shown in FIG. 17D, silicon oxide (SiO) 44 and doped polysilicon 45 are embedded in this order into the space inside the trench portion 25 covered with the P-type solid phase diffusion layer 38. The silicon oxide 44 is buried so as to cover the side surfaces of the P-type solid phase diffusion layer 38. Further, the doped polysilicon 45 is buried until the doped polysilicon 45 covers the entire surface S10 of the mask 40. Subsequently, as shown in FIG. 17E, an etch-back is performed to remove the doped polysilicon 45 from the surface S10 of the mask 40 and the position in the trench portion 25 where the insulating material 39 (see FIG. 12) is buried. Subsequently, as shown in FIG. 17F, an insulating material 46 is embedded in the surface S2 side of the trench portion 25. The insulating material 46 is embedded until the insulating material 46 covers the entire surface S10 of the mask 40. Subsequently, as shown in FIG. 17G, the insulating material 46 is polished from the surface S11 side using the CMP technique to form the insulating material 39. Through such a procedure, the element isolation portion 26 shown in FIG. 12 is formed. Subsequently, as shown in FIG. 12, an insulating film 14, a light shielding film 15, a planarizing film 16, a color filter layer 18, and a microlens array 19 are formed. In this way, the solid-state imaging device 1 shown in FIG. 12 is manufactured.
　次に、固体撮像装置１の他の製造方法について説明する。なお、図１８Ｉに示すように、この製造方法で形成した場合の第２素子分離部２６ｂの構成は、上記の形成方法で形成した場合の第２素子分離部２６ｂの構成とは、若干異なった構成となる。
　まず、図１８Ａに示すように、上記の形成方法と同様に、Ｐ型の半導体基板１２にＮ型の不純物をイオン注入し、Ｎ型半導体領域２３を形成する。続いて、半導体基板１２の表面Ｓ２側からマスク（不図示）を介してエッチングを行って、トレンチ部２５を形成する。続いて、図１８Ｂに示すように、トレンチ部２５の側壁面Ｓ４等に半導体結晶をエピタキシャル成長させ、トレンチ部２５の側壁面Ｓ４全体及び底面、並びに半導体基板１２の表面Ｓ２を連続的に被覆するように、トレンチ部２５内及び半導体基板１２の表面Ｓ２に半導体層４３を形成する。半導体層４３としては、不純物濃度が１ｅ１６/ｃｍ3以下のノンドープのエピタキシャル成長層を形成する。続いて、図１８Ｃに示すように、固相拡散法を用い、トレンチ部２５内等から半導体層４３にＰ型の不純物（例えば、ボロン(B)）をドープして、Ｐ型固相拡散層３８を形成する。即ち半導体層４３をＰ型固相拡散層３８に変化させる。これにより、Ｐ型固相拡散層３８にＮ型の不純物が混ざることを防止でき、Ｐ型固相拡散層３８のＮ型の不純物の濃度を１ｅ１６/ｃｍ3以下とすることができる。 Next, another method of manufacturing the solid-state imaging device 1 will be described. Note that, as shown in FIG. 18I, the configuration of the second element isolation part 26b when formed by this manufacturing method is slightly different from the configuration of the second element isolation part 26b when formed by the above-mentioned formation method. It becomes the composition.
First, as shown in FIG. 18A, similarly to the above-described formation method, N-type impurity ions are implanted into the P-type semiconductor substrate 12 to form the N-type semiconductor region 23. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through a mask (not shown) to form the trench portion 25. Subsequently, as shown in FIG. 18B, a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25, etc., so as to continuously cover the entire side wall surface S4 and the bottom surface of the trench portion 25, as well as the surface S2 of the semiconductor substrate 12. Next, a semiconductor layer 43 is formed within the trench portion 25 and on the surface S2 of the semiconductor substrate 12. As the semiconductor layer 43, a non-doped epitaxial growth layer with an impurity concentration of 1e16/cm 3 or less is formed. Subsequently, as shown in FIG. 18C, a P-type impurity (for example, boron (B)) is doped into the semiconductor layer 43 from within the trench portion 25 using a solid-phase diffusion method to form a P-type solid-phase diffusion layer. form 38. That is, the semiconductor layer 43 is changed to the P-type solid phase diffusion layer 38. This can prevent N-type impurities from being mixed into the P-type solid-phase diffusion layer 38, and the concentration of N-type impurities in the P-type solid-phase diffusion layer 38 can be set to 1e16/cm 3 or less.
　続いて、図１８Ｄに示すように、Ｐ型固相拡散層３８で被覆されたトレンチ部２５の内部の空間に酸化シリコン(SiO)４４及びドープドポリシリコン４５をこの順に埋め込む。酸化シリコン４４の埋め込みは、Ｐ型固相拡散層３８の側面を被覆するように行う。また、ドープドポリシリコン４５の埋め込みは、ドープドポリシリコン４５が、酸化シリコン４４の表面Ｓ１２全体を覆うまで行う。続いて、図１８Ｅに示すように、ＣＭＰ技術又はエッチバックを用い、半導体基板１２の表面Ｓ２側から研磨等して、半導体基板１２の表面Ｓ２を露出させる。続いて、図１８Ｆに示すように、半導体基板１２の表面Ｓ２に対して、第２素子分離部２６ｂ（図１２参照）を形成する位置に開口を有するマスク４７を形成する。マスク４７は、窒化シリコン(SiN)膜４８及び酸化シリコン(SiO)膜４９を積層して構成される。続いて、図１８Ｇに示すように、マスク４７を介してエッチングを行って、トレンチ部２５のうちの第２素子分離部２６ｂ（図１２参照）を形成する部分（以下、「トレンチ部５０」とも呼ぶ）を形成する。続いて、図１８Ｈに示すように、トレンチ部５０内に絶縁材料４６を埋め込む。絶縁材料４６の埋め込みは、絶縁材料４６が、マスク４７の表面Ｓ１０全体を覆うまで行う。続いて、図１８Ｉに示すように、ＣＭＰ技術を用い、絶縁材料４６を表面Ｓ１１側から研磨して、図１２に示した絶縁材料３９を形成する。このような手順により、図１２に示した素子分離部２６を形成する。続いて、図１２に示すように、絶縁膜１４、遮光膜１５、平坦化膜１６、カラーフィルタ層１８及びマイクロレンズアレイ１９を形成する。これにより図１２に示した固体撮像装置１を製造する。 Subsequently, as shown in FIG. 18D, silicon oxide (SiO) 44 and doped polysilicon 45 are embedded in this order into the space inside the trench portion 25 covered with the P-type solid phase diffusion layer 38. The silicon oxide 44 is buried so as to cover the side surfaces of the P-type solid phase diffusion layer 38. Further, the doped polysilicon 45 is buried until the doped polysilicon 45 covers the entire surface S12 of the silicon oxide 44. Subsequently, as shown in FIG. 18E, the surface S2 of the semiconductor substrate 12 is exposed by polishing or the like from the surface S2 side of the semiconductor substrate 12 using CMP technology or etchback. Subsequently, as shown in FIG. 18F, a mask 47 having an opening at a position where the second element isolation portion 26b (see FIG. 12) is to be formed is formed on the surface S2 of the semiconductor substrate 12. The mask 47 is constructed by laminating a silicon nitride (SiN) film 48 and a silicon oxide (SiO) film 49. Subsequently, as shown in FIG. 18G, etching is performed through the mask 47 to form a portion of the trench portion 25 where the second element isolation portion 26b (see FIG. 12) is to be formed (hereinafter also referred to as “trench portion 50”). form). Subsequently, as shown in FIG. 18H, an insulating material 46 is embedded in the trench portion 50. The insulating material 46 is embedded until the insulating material 46 covers the entire surface S10 of the mask 47. Subsequently, as shown in FIG. 18I, the insulating material 46 is polished from the surface S11 side using the CMP technique to form the insulating material 39 shown in FIG. 12. Through such a procedure, the element isolation portion 26 shown in FIG. 12 is formed. Subsequently, as shown in FIG. 12, an insulating film 14, a light shielding film 15, a planarizing film 16, a color filter layer 18, and a microlens array 19 are formed. In this way, the solid-state imaging device 1 shown in FIG. 12 is manufactured.
［３－３　変形例］
（１）なお、第３の実施形態では、光電変換部２１のＮ型の領域として、Ｎ型半導体領域２３を有する例を示したが、他の構成を採用することもできる。例えば、図１９及び図２０に示すように、Ｎ型半導体領域２３の一部として、光電変換部２１のうちのトレンチ部２５と接する領域に、Ｎ型の不純物濃度が比較的高いＮ型の半導体領域（以下「Ｎ＋型半導体領域５１」とも呼ぶ）を有する構成としてもよい。これにより、Ｐ型固相拡散層３８とＮ＋型半導体領域５１（Ｎ型の不純物濃度が比較的高い領域）とでＰＮ接合を形成するため、ポテンシャル勾配をより急峻化でき、光電変換部２１の飽和電荷量Ｑsを増大することができる。図２０では、Ｎ型半導体領域２３及びＰ型固相拡散層３８に重ねてＮ型の不純物濃度を示す曲線を破線で示し、Ｐ型の不純物濃度を示す曲線を一点鎖線で示している。 [3-3 Modification example]
(1) Note that in the third embodiment, an example is shown in which the N-type semiconductor region 23 is provided as the N-type region of the photoelectric conversion section 21, but other configurations may also be adopted. For example, as shown in FIGS. 19 and 20, as part of the N-type semiconductor region 23, an N-type semiconductor with a relatively high N-type impurity concentration is added to a region of the photoelectric conversion section 21 that is in contact with the trench section 25. A structure having a region (hereinafter also referred to as "N+ type semiconductor region 51") may be used. As a result, a PN junction is formed between the P-type solid phase diffusion layer 38 and the N+ type semiconductor region 51 (a region with a relatively high N-type impurity concentration), so that the potential gradient can be made steeper, and the photoelectric conversion section 21 The saturation charge amount Qs can be increased. In FIG. 20, the curve showing the N-type impurity concentration overlapping the N-type semiconductor region 23 and the P-type solid phase diffusion layer 38 is shown by a broken line, and the curve showing the P-type impurity concentration is shown by a dashed line.
　このような構成を採用する場合の、素子分離部２６の形成方法について説明する。図１７Ａ～図１７Ｇに示した製造方法と同様の形成方法を採用する場合、まず、図１７Ａに示した工程と同様に、Ｐ型の半導体基板１２にＮ型の不純物をイオン注入し、Ｎ型半導体領域２３を形成する。続いて、半導体基板１２の表面Ｓ２側からマスク４０を介してエッチングを行って、トレンチ部２５を形成する。続いて、図２１に示すように、トレンチ部２５内からＮ型の不純物をイオン注入し、トレンチ部２５の側壁面Ｓ４及び底面にＮ＋型半導体領域５１を形成する。続いて、図１７Ｂに示した工程と同様に、トレンチ部２５の側壁面Ｓ４に半導体結晶をエピタキシャル成長させ、トレンチ部２５の側壁面Ｓ４及び底面を被覆するように、トレンチ部２５内に半導体層４３を形成する。その後、図１７Ｃ～図１７Ｇに示した工程を経ることで、図１９に示した素子分離部２６を形成する。 A method for forming the element isolation portion 26 when adopting such a configuration will be described. When adopting a manufacturing method similar to the manufacturing method shown in FIGS. 17A to 17G, first, similar to the process shown in FIG. 17A, an N-type impurity is ion-implanted into the P-type semiconductor substrate 12, A semiconductor region 23 is formed. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through the mask 40 to form the trench portion 25. Subsequently, as shown in FIG. 21, N type impurity ions are implanted from within the trench portion 25 to form an N+ type semiconductor region 51 on the side wall surface S4 and the bottom surface of the trench portion 25. Subsequently, similarly to the step shown in FIG. 17B, a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25, and a semiconductor layer 43 is formed in the trench portion 25 so as to cover the side wall surface S4 and the bottom surface of the trench portion 25. form. Thereafter, by going through the steps shown in FIGS. 17C to 17G, the element isolation portion 26 shown in FIG. 19 is formed.
　また、図１８Ａ～図１８Ｉに示した素子分離部２６の形成方法と同様の形成方法を採用する場合、まず、図１８Ａに示した工程と同様に、Ｐ型の半導体基板１２にＮ型の不純物をイオン注入し、Ｎ型半導体領域２３を形成する。続いて、半導体基板１２の表面Ｓ２側からマスク（不図示）を介してエッチングを行って、トレンチ部２５を形成する。続いて、図２２Ａに示すように、トレンチ部２５内からＮ型の不純物をイオン注入し、トレンチ部２５の側壁面Ｓ４全体及び底面にＮ＋型半導体領域５１を形成する。続いて、図１８Ｂに示した工程と同様に、トレンチ部２５の側壁面Ｓ４に半導体結晶をエピタキシャル成長させ、トレンチ部２５の側壁面Ｓ４全体及び底面、並びに半導体基板１２の表面Ｓ２を連続的に被覆するように、トレンチ部２５内及び半導体基板１２の表面Ｓ２に半導体層４３を形成する。その後、図１８Ｃ～図１８Ｉに示した工程を経ることで、図２２Ｂに示した素子分離部２６を形成する。なお、図２２Ｂに示すように、この形成方法で形成した場合の第２素子分離部２６ｂの構成は、上記の形成方法で形成した場合の第２素子分離部２６ｂの構成（図１９の第２素子分離部２６ｂの構成）とは、若干異なった構成となる。 Furthermore, when adopting a formation method similar to that of the element isolation portion 26 shown in FIGS. 18A to 18I, first, an N-type impurity is added to the P-type semiconductor substrate 12 in the same manner as the step shown in FIG. 18A. is ion-implanted to form an N-type semiconductor region 23. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through a mask (not shown) to form the trench portion 25. Subsequently, as shown in FIG. 22A, N type impurity ions are implanted from within the trench portion 25 to form an N + type semiconductor region 51 on the entire sidewall surface S4 and the bottom surface of the trench portion 25. Subsequently, similarly to the step shown in FIG. 18B, a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25 to continuously cover the entire side wall surface S4 and the bottom surface of the trench portion 25, as well as the surface S2 of the semiconductor substrate 12. The semiconductor layer 43 is formed in the trench portion 25 and on the surface S2 of the semiconductor substrate 12 so as to do so. Thereafter, by going through the steps shown in FIGS. 18C to 18I, the element isolation portion 26 shown in FIG. 22B is formed. Note that, as shown in FIG. 22B, the configuration of the second element isolation part 26b when formed by this formation method is the same as the configuration of the second element isolation part 26b when formed by the above-mentioned formation method (the second element isolation part 26b in FIG. 19). The configuration is slightly different from the configuration of the element isolation section 26b.
（２）また、第３の実施形態では、素子分離部２６のＰ型の層として、Ｐ型固相拡散層３８を有する例を示したが、他の構成を採用することもできる。例えば、図２３及び図２４に示すように、Ｐ型固相拡散層３８に代えて、Ｐ型の不純物を添加しながらのエピタキシャル成長によって形成されたＰ型エピタキシャル成長層５２を有する構成としてもよい。ここで、例えば、Ｐ型エピタキシャル成長層５２に代えて、トレンチ部２５内からＰ型の不純物をイオン注入して形成した層を用いる場合、この層の形成時にＮ型半導体領域２３にＰ型の不純物がイオン注入される可能性がある。これに対し、Ｐ型エピタキシャル成長層５２を用いる場合には、Ｐ型エピタキシャル成長層５２の形成時に、図２４に示すように、Ｎ型半導体領域２３にＰ型の不純物が混入されずに済む。それゆえ、Ｐ型の不純物濃度が低いＮ型半導体領域２３とＰ型エピタキシャル成長層５２とでＰＮ接合を形成するため、ポテンシャル勾配をより急峻化でき、光電変換部２１の飽和電荷量Ｑsを増大することができる。図２４では、Ｎ型半導体領域２３及びＰ型固相拡散層３８に重ねてＮ型の不純物濃度を示す曲線を破線で示し、Ｐ型の不純物濃度を示す曲線を一点鎖線で示している。 (2) Furthermore, in the third embodiment, an example is shown in which the P-type solid phase diffusion layer 38 is provided as the P-type layer of the element isolation section 26, but other configurations may also be adopted. For example, as shown in FIGS. 23 and 24, instead of the P-type solid phase diffusion layer 38, a P-type epitaxial growth layer 52 formed by epitaxial growth while adding P-type impurities may be used. Here, for example, if a layer formed by ion-implanting P-type impurities from within the trench portion 25 is used instead of the P-type epitaxial growth layer 52, the P-type impurity is added to the N-type semiconductor region 23 when forming this layer. may be ion-implanted. On the other hand, when the P-type epitaxial growth layer 52 is used, the P-type impurity is not mixed into the N-type semiconductor region 23 as shown in FIG. 24 when the P-type epitaxial growth layer 52 is formed. Therefore, since a PN junction is formed between the N-type semiconductor region 23 with a low P-type impurity concentration and the P-type epitaxial growth layer 52, the potential gradient can be made steeper, and the saturated charge amount Qs of the photoelectric conversion section 21 can be increased. be able to. In FIG. 24, the curve showing the N-type impurity concentration overlapping the N-type semiconductor region 23 and the P-type solid phase diffusion layer 38 is shown by a broken line, and the curve showing the P-type impurity concentration is shown by a dashed line.
　このような構成を採用する場合の、素子分離部２６の形成方法について説明する。図１７Ａ～図１７Ｇに示した製造方法と同様の形成方法を採用する場合、まず、図１７Ａに示した工程と同様に、Ｐ型の半導体基板１２にＮ型の不純物をイオン注入し、Ｎ型半導体領域２３を形成する。続いて、半導体基板１２の表面Ｓ２側からマスク４０を介してエッチングを行って、トレンチ部２５を形成する。続いて、図２５に示すように、トレンチ部２５の側壁面Ｓ４に、Ｐ型の不純物を添加しながら半導体結晶をエピタキシャル成長させ、トレンチ部２５の側壁面Ｓ４及び底面を被覆するように、トレンチ部２５内にＰ型エピタキシャル成長層５２を形成する。その後、図１７Ｃに示した工程を省略し、図１７Ｄ～図１７Ｇに示した工程を経ることで、図２３に示した素子分離部２６を形成する。 A method for forming the element isolation portion 26 when adopting such a configuration will be described. When adopting a manufacturing method similar to the manufacturing method shown in FIGS. 17A to 17G, first, similar to the process shown in FIG. 17A, an N-type impurity is ion-implanted into the P-type semiconductor substrate 12, A semiconductor region 23 is formed. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through the mask 40 to form the trench portion 25. Subsequently, as shown in FIG. 25, a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25 while adding a P-type impurity, and the trench portion is grown so as to cover the side wall surface S4 and the bottom surface of the trench portion 25. A P-type epitaxial growth layer 52 is formed within 25. Thereafter, by omitting the step shown in FIG. 17C and passing through the steps shown in FIGS. 17D to 17G, the element isolation portion 26 shown in FIG. 23 is formed.
　また、図１８Ａ～図１８Ｉに示した素子分離部２６の形成方法と同様の形成方法を採用する場合、まず、図１８Ａに示した工程と同様に、Ｐ型の半導体基板１２にＮ型の不純物をイオン注入し、Ｎ型半導体領域２３を形成する。続いて、半導体基板１２の表面Ｓ２側からマスク（不図示）を介してエッチングを行って、トレンチ部２５を形成する。続いて、図２６Ａに示すように、トレンチ部２５の側壁面Ｓ４等に、Ｐ型の不純物を添加しながら半導体結晶をエピタキシャル成長させ、トレンチ部２５の側壁面Ｓ４全体及び底面、並びに半導体基板１２の表面Ｓ２を連続的に被覆するように、トレンチ部２５内及び半導体基板１２の表面Ｓ２にＰ型エピタキシャル成長層５２を形成する。その後、図１８Ｃに示した工程を省略し、図１８Ｄ～図１８Ｉに示した工程を経ることで、図２６Ｂに示した素子分離部２６を形成する。なお、図２６Ｂに示すように、この形成方法で形成した場合の第２素子分離部２６ｂの構成は、上記の形成方法で形成した場合の第２素子分離部２６ｂの構成（図２３の第２素子分離部２６ｂの構成）とは、若干異なった構成となる。 Furthermore, when adopting a formation method similar to that of the element isolation portion 26 shown in FIGS. 18A to 18I, first, an N-type impurity is added to the P-type semiconductor substrate 12 in the same manner as the step shown in FIG. 18A. is ion-implanted to form an N-type semiconductor region 23. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through a mask (not shown) to form the trench portion 25. Subsequently, as shown in FIG. 26A, a semiconductor crystal is epitaxially grown while adding P-type impurities to the sidewall surface S4 of the trench portion 25, etc., so that the entire sidewall surface S4 and bottom surface of the trench portion 25, as well as the semiconductor substrate 12 are grown. A P-type epitaxial growth layer 52 is formed in the trench portion 25 and on the surface S2 of the semiconductor substrate 12 so as to continuously cover the surface S2. Thereafter, by omitting the step shown in FIG. 18C and passing through the steps shown in FIGS. 18D to 18I, the element isolation portion 26 shown in FIG. 26B is formed. Note that, as shown in FIG. 26B, the configuration of the second element isolation part 26b when formed by this formation method is different from the configuration of the second element isolation part 26b when formed by the above-mentioned formation method (the second element isolation part 26b in FIG. 23). The configuration is slightly different from the configuration of the element isolation section 26b.
（３）また、例えば、図２７及び図２８に示すように、上記の変形例（１）（２）を組み合わせて、図１９に示したＮ＋型半導体領域５１と、図２３に示したＰ型エピタキシャル成長層５２とを有する構成としてもよい。これにより、光電変換部２１の飽和電荷量Ｑsを増大できる。図２８では、Ｎ型半導体領域２３及びＰ型固相拡散層３８に重ねてＮ型の不純物濃度を示す曲線を破線で示し、Ｐ型の不純物濃度を示す曲線を一点鎖線で示している。
　このような構成を採用する場合の、素子分離部２６の形成方法について説明する。図１７Ａ～図１７Ｇに示した製造方法と同様の形成方法を採用する場合、まず、図１７Ａに示した工程と同様に、Ｐ型の半導体基板１２にＮ型の不純物をイオン注入し、Ｎ型半導体領域２３を形成する。続いて、半導体基板１２の表面Ｓ２側からマスク４０を介してエッチングを行って、トレンチ部２５を形成する。続いて、図２１に示した工程と同様に、トレンチ部２５内からＮ型の不純物をイオン注入し、トレンチ部２５の側壁面Ｓ４及び底面にＮ＋型半導体領域５１を形成する。続いて、図２９に示すように、トレンチ部２５の側壁面Ｓ４に、Ｐ型の不純物を添加しながら半導体結晶をエピタキシャル成長させ、トレンチ部２５の側壁面Ｓ４及び底面を被覆するように、トレンチ部２５内にＰ型エピタキシャル成長層５２を形成する。その後、図１７Ｃに示した工程を省略し、図１７Ｄ～図１７Ｇに示した工程を経ることで、図２７に示した素子分離部２６を形成する。 (3) For example, as shown in FIGS. 27 and 28, by combining the above modifications (1) and (2), the N+ type semiconductor region 51 shown in FIG. 19 and the P type semiconductor region 51 shown in FIG. A structure including an epitaxial growth layer 52 may also be used. Thereby, the saturated charge amount Qs of the photoelectric conversion section 21 can be increased. In FIG. 28, a curve showing the N-type impurity concentration overlapping the N-type semiconductor region 23 and the P-type solid phase diffusion layer 38 is shown by a broken line, and a curve showing the P-type impurity concentration is shown by a dashed line.
A method of forming the element isolation portion 26 when such a configuration is adopted will be described. When adopting a manufacturing method similar to the manufacturing method shown in FIGS. 17A to 17G, first, similar to the process shown in FIG. 17A, an N-type impurity is ion-implanted into the P-type semiconductor substrate 12, A semiconductor region 23 is formed. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through the mask 40 to form the trench portion 25. Subsequently, similarly to the step shown in FIG. 21, N type impurity ions are implanted from within the trench portion 25 to form an N+ type semiconductor region 51 on the side wall surface S4 and the bottom surface of the trench portion 25. Subsequently, as shown in FIG. 29, a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25 while adding a P-type impurity, and the trench portion is grown so as to cover the side wall surface S4 and the bottom surface of the trench portion 25. A P-type epitaxial growth layer 52 is formed within 25. Thereafter, by omitting the step shown in FIG. 17C and passing through the steps shown in FIGS. 17D to 17G, the element isolation portion 26 shown in FIG. 27 is formed.
　また、図１８Ａ～図１８Ｉに示した素子分離部２６の形成方法と同様の形成方法を採用する場合、まず、図１８Ａに示した工程と同様に、Ｐ型の半導体基板１２にＮ型の不純物をイオン注入し、Ｎ型半導体領域２３を形成する。続いて、半導体基板１２の表面Ｓ２側からマスク（不図示）を介してエッチングを行って、トレンチ部２５を形成する。続いて、図２２Ａに示した工程と同様に、トレンチ部２５内からＮ型の不純物をイオン注入し、トレンチ部２５の側壁面Ｓ４全体及び底面にＮ＋型半導体領域５１を形成する。続いて、図３０Ａに示すように、トレンチ部２５の側壁面Ｓ４等に、Ｐ型の不純物を添加しながら半導体結晶をエピタキシャル成長させ、トレンチ部２５の側壁面Ｓ４全体及び底面、並びに半導体基板１２の表面Ｓ２を連続的に被覆するように、トレンチ部２５内及び半導体基板１２の表面Ｓ２にＰ型エピタキシャル成長層５２を形成する。その後、図１８Ｃに示した工程を省略し、図１８Ｄ～図１８Ｉに示した工程を経ることで、図３０Ｂに示した素子分離部２６を形成する。なお、図３０Ｂに示すように、この形成方法で形成した場合の第２素子分離部２６ｂの構成は、上記の形成方法で形成した場合の第２素子分離部２６ｂの構成（図２７の第２素子分離部２６ｂの構成）とは、若干異なった構成となる。 Furthermore, when adopting a formation method similar to that of the element isolation portion 26 shown in FIGS. 18A to 18I, first, an N-type impurity is added to the P-type semiconductor substrate 12 in the same manner as the step shown in FIG. 18A. is ion-implanted to form an N-type semiconductor region 23. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through a mask (not shown) to form the trench portion 25. Subsequently, similarly to the step shown in FIG. 22A, N type impurity ions are implanted from within the trench portion 25 to form an N + type semiconductor region 51 on the entire sidewall surface S4 and the bottom surface of the trench portion 25. Subsequently, as shown in FIG. 30A, a semiconductor crystal is epitaxially grown while adding P-type impurities to the sidewall surface S4 of the trench portion 25, etc., so that the entire sidewall surface S4 and bottom surface of the trench portion 25 and the semiconductor substrate 12 are grown. A P-type epitaxial growth layer 52 is formed in the trench portion 25 and on the surface S2 of the semiconductor substrate 12 so as to continuously cover the surface S2. Thereafter, by omitting the step shown in FIG. 18C and passing through the steps shown in FIGS. 18D to 18I, the element isolation portion 26 shown in FIG. 30B is formed. Note that, as shown in FIG. 30B, the configuration of the second element isolation part 26b when formed by this formation method is different from the configuration of the second element isolation part 26b when formed by the above-mentioned formation method (the second element isolation part 26b in FIG. 27). The configuration is slightly different from the configuration of the element isolation section 26b.
〈４．第４の実施形態：固体撮像装置〉
［４－１　要部の構成］
　次に、本開示の第４の実施形態に係る固体撮像装置１について説明する。第４の実施形態に係る固体撮像装置１の全体構成は、図１と同様であるから図示を省略する。図３１は、第４の実施形態に係る固体撮像装置１の断面構成を示す図である。また、図３２は、図３１の領域Ｊを拡大した場合の、固体撮像装置１の断面構成を示す図である。図３１、図３２において、図１２、図１３に対応する部分には同一符号を付し重複説明を省略する。 <4. Fourth embodiment: solid-state imaging device>
[4-1 Configuration of main parts]
Next, a solid-state imaging device 1 according to a fourth embodiment of the present disclosure will be described. The overall configuration of the solid-state imaging device 1 according to the fourth embodiment is the same as that in FIG. 1, so illustration thereof is omitted. FIG. 31 is a diagram showing a cross-sectional configuration of a solid-state imaging device 1 according to the fourth embodiment. Further, FIG. 32 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 when region J in FIG. 31 is enlarged. In FIGS. 31 and 32, parts corresponding to those in FIGS. 12 and 13 are denoted by the same reference numerals, and redundant explanation will be omitted.
　第４の実施形態では、図３１及び図３２に示すように、図１２に示したＰ型固相拡散層３８に代えて、Ｎ型エピタキシャル成長層５３及びＰ型エピタキシャル成長層５４を用いる点が、第３の実施形態と異なっている。Ｎ型エピタキシャル成長層５３及びＰ型エピタキシャル成長層５４は、トレンチ部２５の側壁面Ｓ４にこの順に積層されている。
　Ｎ型エピタキシャル成長層５３は、トレンチ部２５内に配置され、トレンチ部２５の側壁面Ｓ４を被覆する層である。Ｎ型エピタキシャル成長層５３としては、例えば、Ｎ型の不純物を添加しながらのエピタキシャル成長によって形成されたエピタキシャル成長層を採用できる。このようなエピタキシャル成長層を用いることにより、図３１に示すように、Ｎ型エピタキシャル成長層５３のＰ型の不純物濃度は、１ｅ１６/ｃｍ3以下となっている。Ｐ型の不純物濃度を低くしたことにより、Ｎ型エピタキシャル成長層５３は、Ｎ型エピタキシャル成長層５３とＰ型エピタキシャル成長層５４とのＰＮ接合によるポテンシャル勾配を急峻化することができる。それゆえ、光電変換部２１の飽和電荷量Ｑsを向上することができる。図３１では、Ｎ型半導体領域２３、Ｎ型エピタキシャル成長層５３及びＰ型エピタキシャル成長層５４に重ねてＮ型の不純物濃度を示す曲線を破線で示し、Ｐ型の不純物濃度を示す曲線を一点鎖線で示している。 In the fourth embodiment, as shown in FIGS. 31 and 32, an N-type epitaxial growth layer 53 and a P-type epitaxial growth layer 54 are used in place of the P-type solid phase diffusion layer 38 shown in FIG. This embodiment is different from the third embodiment. The N-type epitaxial growth layer 53 and the P-type epitaxial growth layer 54 are laminated in this order on the side wall surface S4 of the trench portion 25.
The N-type epitaxial growth layer 53 is a layer disposed within the trench portion 25 and covering the side wall surface S4 of the trench portion 25. As the N-type epitaxial growth layer 53, for example, an epitaxial growth layer formed by epitaxial growth while adding N-type impurities can be used. By using such an epitaxial growth layer, as shown in FIG. 31, the P-type impurity concentration of the N-type epitaxial growth layer 53 is 1e16/cm 3 or less. By lowering the P-type impurity concentration, the N-type epitaxial growth layer 53 can steepen the potential gradient due to the PN junction between the N-type epitaxial growth layer 53 and the P-type epitaxial growth layer 54. Therefore, the saturation charge amount Qs of the photoelectric conversion section 21 can be improved. In FIG. 31, the curve showing the N-type impurity concentration overlapping the N-type semiconductor region 23, the N-type epitaxial growth layer 53, and the P-type epitaxial growth layer 54 is shown by a broken line, and the curve showing the P-type impurity concentration is shown by a dashed line. ing.
　Ｐ型エピタキシャル成長層５４は、Ｎ型エピタキシャル成長層５３で被覆されたトレンチ部２５の内部の空間に配置され、Ｎ型エピタキシャル成長層５３と接する層である。これにより、Ｐ型エピタキシャル成長層５４は、Ｎ型エピタキシャル成長層５３のトレンチ部２５幅方向中心側の面に積層され、Ｎ型エピタキシャル成長層５３とＰＮ接合を形成している。Ｐ型エピタキシャル成長層５４としては、例えば、Ｐ型の不純物を添加しながらのエピタキシャル成長によって形成されたエピタキシャル成長層を採用できる。このようなエピタキシャル成長層を用いることにより、図３１に示すように、Ｐ型エピタキシャル成長層５４のＮ型の不純物濃度は、１ｅ１６/ｃｍ3以下となっている。Ｎ型の不純物濃度を低くしたことにより、Ｐ型エピタキシャル成長層５４は、ＰＮ接合によるポテンシャル勾配をより急峻化できる。それゆえ、光電変換部２１の飽和電荷量Ｑsの低下をより抑制できる。なお、図１２では図８に示した固定電荷膜１３が省略した場合を例示している。 The P-type epitaxial growth layer 54 is a layer that is disposed in the space inside the trench portion 25 covered with the N-type epitaxial growth layer 53 and is in contact with the N-type epitaxial growth layer 53 . As a result, the P-type epitaxial growth layer 54 is stacked on the surface of the N-type epitaxial growth layer 53 on the center side in the width direction of the trench portion 25, forming a PN junction with the N-type epitaxial growth layer 53. As the P-type epitaxial growth layer 54, for example, an epitaxial growth layer formed by epitaxial growth while adding P-type impurities can be employed. By using such an epitaxial growth layer, as shown in FIG. 31, the N-type impurity concentration of the P-type epitaxial growth layer 54 is 1e16/cm 3 or less. By lowering the N-type impurity concentration, the P-type epitaxial growth layer 54 can have a steeper potential gradient due to the PN junction. Therefore, a decrease in the saturation charge amount Qs of the photoelectric conversion section 21 can be further suppressed. Note that FIG. 12 illustrates a case where the fixed charge film 13 shown in FIG. 8 is omitted.
［４－２　固体撮像装置の製造方法］
　次に、第４の実施形態に係る固体撮像装置１の製造方法について説明する。
　図１７Ａ～図１７Ｇに示した製造方法と同様の製造方法を採用する場合、図１７Ａに示した工程と同様に、Ｐ型の半導体基板１２にＮ型の不純物をイオン注入し、Ｎ型半導体領域２３を形成する。続いて、半導体基板１２の表面Ｓ２側からマスク４０を介してエッチングを行って、トレンチ部２５を形成する。続いて、図３３Ａに示すように、トレンチ部２５の側壁面Ｓ４に、Ｎ型の不純物を添加しながら半導体結晶をエピタキシャル成長させ、トレンチ部２５の側壁面Ｓ４及び底面を被覆するように、トレンチ部２５内にＮ型エピタキシャル成長層５３を形成する。続いて、図３３Ｂに示すように、Ｎ型エピタキシャル成長層５３のトレンチ部２５幅方向中心側の面（以下「中心側面Ｓ１３」とも呼ぶ）に、Ｐ型の不純物を添加しながら半導体結晶をエピタキシャル成長させ、Ｎ型エピタキシャル成長層５３の中心側面Ｓ１３を被覆するように、トレンチ部２５内にＰ型エピタキシャル成長層５４を形成する。その後、図１７Ｃに示した工程を省略し、図１７Ｄ～図１７Ｇに示した工程を経ることで、図３１に示した素子分離部２６を形成する。続いて、図３１に示すように、絶縁膜１４、遮光膜１５、平坦化膜１６、カラーフィルタ層１８及びマイクロレンズアレイ１９を形成する。これにより図３１に示した固体撮像装置１を製造する。 [4-2 Method for manufacturing solid-state imaging device]
Next, a method for manufacturing the solid-state imaging device 1 according to the fourth embodiment will be described.
When employing a manufacturing method similar to the manufacturing method shown in FIGS. 17A to 17G, an N-type impurity is ion-implanted into the P-type semiconductor substrate 12 in the same way as the process shown in FIG. 17A, and the N-type semiconductor region form 23. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through the mask 40 to form the trench portion 25. Subsequently, as shown in FIG. 33A, a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25 while adding an N-type impurity, and the trench portion is grown so as to cover the side wall surface S4 and the bottom surface of the trench portion 25. An N-type epitaxial growth layer 53 is formed within 25. Subsequently, as shown in FIG. 33B, a semiconductor crystal is epitaxially grown on the surface of the N-type epitaxial growth layer 53 on the center side in the width direction of the trench portion 25 (hereinafter also referred to as "center side surface S13") while adding P-type impurities. , a P-type epitaxial growth layer 54 is formed in the trench portion 25 so as to cover the central side surface S13 of the N-type epitaxial growth layer 53. Thereafter, by omitting the step shown in FIG. 17C and passing through the steps shown in FIGS. 17D to 17G, the element isolation portion 26 shown in FIG. 31 is formed. Subsequently, as shown in FIG. 31, an insulating film 14, a light shielding film 15, a planarizing film 16, a color filter layer 18, and a microlens array 19 are formed. As a result, the solid-state imaging device 1 shown in FIG. 31 is manufactured.
　また、図１８Ａ～図１８Ｉに示した固体撮像装置１の製造方法と同様の製造方法を採用する場合、まず、図１８Ａに示した工程と同様に、Ｐ型の半導体基板１２にＮ型の不純物をイオン注入し、Ｎ型半導体領域２３を形成する。続いて、半導体基板１２の表面Ｓ２側からマスク（不図示）を介してエッチングを行って、トレンチ部２５を形成する。続いて、図３４Ａに示すように、トレンチ部２５の側壁面Ｓ４等に、Ｎ型の不純物を添加しながら半導体結晶をエピタキシャル成長させ、トレンチ部２５の側壁面Ｓ４全体及び底面、並びに半導体基板１２の表面Ｓ２を連続的に被覆するように、トレンチ部２５内及び半導体基板１２の表面Ｓ２にＮ型エピタキシャル成長層５３を形成する。続いて、図３４Ｂに示すように、Ｎ型エピタキシャル成長層５３のトレンチ部２５幅方向中心側の面（中心側面Ｓ１３）等に、Ｐ型の不純物を添加しながら半導体結晶をエピタキシャル成長させ、Ｎ型エピタキシャル成長層５３の中心側面Ｓ１３全体を連続的に被覆するように、トレンチ部２５内などにＰ型エピタキシャル成長層５４を形成する。その後、図１８Ｃに示した工程を省略し、図１８Ｄ～図１８Ｉに示した工程を経ることで、図３４Ｃに示した素子分離部２６を形成する。なお、図３４Ｃに示すように、この製造方法で形成した場合の第２素子分離部２６ｂの構成は、上記の製造方法で形成した場合の第２素子分離部２６ｂの構成（図３１の第２素子分離部２６ｂの構成）とは若干異なった構成となる。続いて、図３１に示すように、絶縁膜１４、遮光膜１５、平坦化膜１６、カラーフィルタ層１８及びマイクロレンズアレイ１９を形成する。これにより図３１に示した固体撮像装置１を製造する。 In addition, when adopting a manufacturing method similar to that of the solid-state imaging device 1 shown in FIGS. 18A to 18I, first, similar to the process shown in FIG. 18A, an N-type impurity is added to the P-type semiconductor substrate 12. is ion-implanted to form an N-type semiconductor region 23. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through a mask (not shown) to form the trench portion 25. Subsequently, as shown in FIG. 34A, a semiconductor crystal is epitaxially grown while adding an N-type impurity to the side wall surface S4 of the trench portion 25, etc., so that the entire side wall surface S4 and bottom surface of the trench portion 25, as well as the semiconductor substrate 12 are grown. An N-type epitaxial growth layer 53 is formed in the trench portion 25 and on the surface S2 of the semiconductor substrate 12 so as to continuously cover the surface S2. Subsequently, as shown in FIG. 34B, a semiconductor crystal is epitaxially grown while adding P-type impurities to the center side surface in the width direction of the trench portion 25 (center side surface S13) of the N-type epitaxial growth layer 53, and the N-type epitaxial growth is performed. A P-type epitaxial growth layer 54 is formed in the trench portion 25 or the like so as to continuously cover the entire center side surface S13 of the layer 53. Thereafter, the step shown in FIG. 18C is omitted and the steps shown in FIGS. 18D to 18I are performed to form the element isolation portion 26 shown in FIG. 34C. Note that, as shown in FIG. 34C, the configuration of the second element isolation part 26b when formed by this manufacturing method is different from the configuration of the second element isolation part 26b when formed by the above manufacturing method (the second element isolation part 26b in FIG. 31). The configuration is slightly different from that of the element isolation section 26b (configuration of the element isolation section 26b). Subsequently, as shown in FIG. 31, an insulating film 14, a light shielding film 15, a planarizing film 16, a color filter layer 18, and a microlens array 19 are formed. As a result, the solid-state imaging device 1 shown in FIG. 31 is manufactured.
［４－３　変形例］
（１）なお、本技術は、上述したイメージセンサとしての固体撮像装置１の他、ＴｏＦ（Time of Flight）センサとも呼ばれる距離を測定する測距センサ等も含む光検出装置全般に適用することができる。測距センサは、物体に向かって照射光を発光し、その照射光が物体の表面で反射され返ってくる反射光を検出し、照射光が発光されてから反射光が受光されるまでの飛行時間に基づいて物体までの距離を算出するセンサである。この測距センサの受光画素構造として、上述した画素８の構造を採用することができる。 [4-3 Modification example]
(1) In addition to the solid-state imaging device 1 as an image sensor described above, the present technology can also be applied to photodetection devices in general, including a ranging sensor that measures distance, also called a ToF (Time of Flight) sensor. can. A distance measurement sensor emits illumination light toward an object, detects the reflected light that is reflected back from the object's surface, and measures the flight from the time the illumination light is emitted until the reflected light is received. This is a sensor that calculates the distance to an object based on time. As the light-receiving pixel structure of this distance measurement sensor, the structure of the pixel 8 described above can be adopted.
〈５．第５の実施形態：電子機器への応用例〉
　本開示に係る技術（本技術）は、各種の電子機器に適用されてもよい。
　図３５は、本技術を適用した電子機器としての撮像装置（ビデオカメラ、デジタルスチルカメラ等）の概略的な構成の一例を示す図である。
　図３５に示すように、撮像装置１０００は、レンズ群１００１と、固体撮像装置１００２（第１の実施形態に係る固体撮像装置１）と、ＤＳＰ(Digital Signal Processor)回路１００３と、フレームメモリ１００４と、モニタ１００５と、メモリ１００６とを備えている。ＤＳＰ回路１００３、フレームメモリ１００４、モニタ１００５及びメモリ１００６は、バスライン１００７を介して相互に接続されている。 <5. Fifth embodiment: Application example to electronic equipment>
The technology according to the present disclosure (this technology) may be applied to various electronic devices.
FIG. 35 is a diagram illustrating an example of a schematic configuration of an imaging device (video camera, digital still camera, etc.) as an electronic device to which the present technology is applied.
As shown in FIG. 35, the imaging device 1000 includes a lens group 1001, a solid-state imaging device 1002 (solid-state imaging device 1 according to the first embodiment), a DSP (Digital Signal Processor) circuit 1003, and a frame memory 1004. , a monitor 1005, and a memory 1006. DSP circuit 1003, frame memory 1004, monitor 1005, and memory 1006 are interconnected via bus line 1007.
　レンズ群１００１は、被写体からの入射光（像光）を固体撮像装置１００２に導き、固体撮像装置１００２の光入射面（画素領域）に結像させる。
　固体撮像装置１００２は、上述した第１の実施の形態のＣＭＯＳイメージセンサからなる。固体撮像装置１００２は、レンズ群１００１によって光入射面上に結像された入射光の光量を画素単位で電気信号に変換して画素信号としてＤＳＰ回路１００３に供給する。
　ＤＳＰ回路１００３は、固体撮像装置１００２から供給される画素信号に対して所定の画像処理を行う。そして、ＤＳＰ回路１００３は、画像処理後の画像信号をフレーム単位でフレームメモリ１００４に供給し、フレームメモリ１００４に一時的に記憶させる。
　モニタ１００５は、例えば、液晶パネルや、有機ＥＬ(Electro Luminescence)パネル等のパネル型表示装置からなる。モニタ１００５は、フレームメモリ１００４に一時的に記憶されたフレーム単位の画素信号に基づいて、被写体の画像（動画）を表示する。
　メモリ１００６は、ＤＶＤ、フラッシュメモリ等からなる。メモリ１００６は、フレームメモリ１００４に一時的に記憶されたフレーム単位の画素信号を読み出して記録する。 A lens group 1001 guides incident light (image light) from a subject to a solid-state imaging device 1002, and forms an image on a light entrance surface (pixel region) of the solid-state imaging device 1002.
The solid-state imaging device 1002 is composed of the CMOS image sensor of the first embodiment described above. The solid-state imaging device 1002 converts the amount of incident light imaged on the light entrance surface by the lens group 1001 into an electric signal for each pixel, and supplies the electric signal to the DSP circuit 1003 as a pixel signal.
The DSP circuit 1003 performs predetermined image processing on pixel signals supplied from the solid-state imaging device 1002. Then, the DSP circuit 1003 supplies the image signal after image processing to the frame memory 1004 in units of frames, and causes the frame memory 1004 to temporarily store the image signal.
The monitor 1005 is composed of a panel display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel. The monitor 1005 displays an image (moving image) of the subject based on pixel signals for each frame temporarily stored in the frame memory 1004.
The memory 1006 consists of a DVD, flash memory, etc. The memory 1006 reads out and records pixel signals in frame units temporarily stored in the frame memory 1004.
　なお、固体撮像装置１を適用できる電子機器は、撮像装置１０００に限られるものではなく、他の電子機器にも適用できる。また、固体撮像装置１００２として、第１の実施形態に係る固体撮像装置１を用いる構成としたが、他の構成を採用することもできる。例えば、第２～第４の実施形態に係る固体撮像装置１、及び第２～第４の実施形態の変形例に係る固体撮像装置１等、本技術を適用した他の光検出装置を用いる構成としてもよい。 Note that the electronic device to which the solid-state imaging device 1 can be applied is not limited to the imaging device 1000, but can also be applied to other electronic devices. Furthermore, although the solid-state imaging device 1 according to the first embodiment is used as the solid-state imaging device 1002, other configurations may also be adopted. For example, a configuration using other photodetecting devices to which the present technology is applied, such as the solid-state imaging device 1 according to the second to fourth embodiments and the solid-state imaging device 1 according to a modification of the second to fourth embodiments. You can also use it as
　なお、本開示は、以下のような構成であってもよい。
（１）
　複数の光電変換部が形成された半導体基板と、
　前記半導体基板のうちの前記光電変換部間に形成されたトレンチ部、前記トレンチ部内に配置され、前記トレンチ部の側壁面を被覆する半導体層、及び前記半導体層で被覆された前記トレンチ部の内部の空間に配置された機能層を有する素子分離部と、を備え、
　前記光電変換部は、前記半導体層と接する領域にＮ型半導体領域を有しており、
　前記半導体層は、Ｐ型の不純物濃度が１ｅ１６/ｃｍ3以下であり、
　前記機能層は、前記半導体層の前記機能層側にホールを誘起させる層である
　光検出装置。
（２）
　前記Ｎ型半導体領域は、前記半導体層と前記Ｎ型半導体領域との界面において、Ｎ型の不純物濃度のピークを有する
　前記（１）に記載の光検出装置。
（３）
　前記機能層は、前記半導体層の面のうちの、前記トレンチ部の側壁面から遠い側の面に沿って配置され、負の固定電荷を有する固定電荷膜である
　前記（１）又は（２）に記載の光検出装置。
（４）
　前記機能層は、前記半導体層の面のうちの、前記トレンチ部の側壁面から遠い側の面に沿って配置され、負のバイアス電圧が印加される導体部である
　前記（１）又は（２）に記載の光検出装置。
（５）
　前記導体部は、前記トレンチ部の内部に側壁が前記導体部で形成された溝状の空間を有するように、前記トレンチ部の側壁面を被覆している
　前記（４）に記載の光検出装置。
（６）
　前記半導体層は、前記半導体基板と異なるタイミングで形成された半導体層である
　前記（４）に記載の光検出装置。
（７）
　前記半導体層は、エピタキシャル成長層である
　前記（４）に記載の光検出装置。
（８）
　複数の光電変換部が形成された半導体基板と、
　前記半導体基板のうちの前記光電変換部間に形成されたトレンチ部、及び前記トレンチ部内に配置され、前記トレンチ部の側壁面を被覆するＰ型固相拡散層を有する素子分離部と、を備え、
　前記光電変換部は、前記Ｐ型固相拡散層と接する領域にＮ型半導体領域を有しており、
　前記Ｐ型固相拡散層は、Ｎ型の不純物濃度が１ｅ１６/ｃｍ3以下である
　光検出装置。
（９）
　複数の光電変換部が形成された半導体基板と、
　前記半導体基板のうちの前記光電変換部間に形成されたトレンチ部、前記トレンチ部内に配置され、前記トレンチ部の側壁面を被覆するＮ型エピタキシャル成長層、及び前記Ｎ型エピタキシャル成長層で被覆された前記トレンチ部の内部の空間に配置され、前記Ｎ型エピタキシャル成長層と接するＰ型エピタキシャル成長層を有する素子分離部を備え、
　前記Ｎ型エピタキシャル成長層は、Ｐ型の不純物濃度が１ｅ１６/ｃｍ3以下であり、
　前記Ｐ型エピタキシャル成長層は、Ｎ型の不純物濃度が１ｅ１６/ｃｍ3以下である
　光検出装置。
（１０）
　複数の光電変換部が形成された半導体基板、並びに前記半導体基板のうちの前記光電変換部間に形成されたトレンチ部、前記トレンチ部内に配置され、前記トレンチ部の側壁面を被覆する半導体層、及び前記半導体層で被覆された前記トレンチ部の内部の空間に配置された機能層を有する素子分離部を備え、前記光電変換部は、前記半導体層と接する領域にＮ型半導体領域を有しており、前記半導体層は、Ｐ型の不純物濃度が１ｅ１６/ｃｍ3以下であり、前記機能層は、前記半導体層の前記機能層側にホールを誘起させる層である光検出装置を備える
　電子機器。
（１１）
　複数の光電変換部が形成された半導体基板、並びに前記半導体基板のうちの前記光電変換部間に形成されたトレンチ部、及び前記トレンチ部内に配置され、前記トレンチ部の側壁面を被覆するＰ型固相拡散層を有する素子分離部を備え、前記光電変換部は、前記Ｐ型固相拡散層と接する領域にＮ型半導体領域を有しており、前記Ｐ型固相拡散層は、Ｎ型の不純物濃度が１ｅ１６/ｃｍ3以下である光検出装置を備える
　電子機器。
（１２）
　複数の光電変換部が形成された半導体基板、並びに前記半導体基板のうちの前記光電変換部間に形成されたトレンチ部、前記トレンチ部内に配置され、前記トレンチ部の側壁面を被覆するＮ型エピタキシャル成長層、及び前記Ｎ型エピタキシャル成長層で被覆された前記トレンチ部の内部の空間に配置され、前記Ｎ型エピタキシャル成長層と接するＰ型エピタキシャル成長層を有する素子分離部を備え、前記Ｎ型エピタキシャル成長層は、Ｐ型の不純物濃度が１ｅ１６/ｃｍ3以下であり、前記Ｐ型エピタキシャル成長層は、Ｎ型の不純物濃度が１ｅ１６/ｃｍ3以下である光検出装置を備える
　電子機器。
（１３）
　半導体基板にトレンチ部を形成する工程と、
　エピタキシャル成長によって、前記トレンチ部の側壁面に不純物濃度が１ｅ１６/ｃｍ3以下のエピタキシャル成長層を形成する工程と、
　固相拡散によって、前記トレンチ部内から前記エピタキシャル成長層にＰ型の不純物をドープする工程と、を含む
　光検出装置の製造方法。
（１４）
　半導体基板にトレンチ部を形成する工程と、
　Ｎ型の不純物を添加しながらのエピタキシャル成長によって、前記トレンチ部の側壁面にＰ型の不純物濃度が１ｅ１６/ｃｍ3以下のＮ型エピタキシャル成長層を形成する工程と、
　Ｐ型の不純物を添加しながらのエピタキシャル成長によって、前記Ｎ型エピタキシャル成長層の前記トレンチ部幅方向中心側の面にＮ型の不純物濃度が１ｅ１６/ｃｍ3以下のＰ型エピタキシャル成長層を形成する工程と、を含む
　光検出装置の製造方法。 Note that the present disclosure may have the following configuration.
(1)
a semiconductor substrate on which a plurality of photoelectric conversion parts are formed;
A trench portion formed between the photoelectric conversion parts of the semiconductor substrate, a semiconductor layer disposed within the trench portion and covering a side wall surface of the trench portion, and an interior of the trench portion covered with the semiconductor layer. an element isolation section having a functional layer arranged in a space of
The photoelectric conversion section has an N-type semiconductor region in a region in contact with the semiconductor layer,
The semiconductor layer has a P-type impurity concentration of 1e16/cm 3 or less,
The functional layer is a layer that induces holes on the functional layer side of the semiconductor layer. The photodetecting device.
(2)
The photodetection device according to (1), wherein the N-type semiconductor region has an N-type impurity concentration peak at an interface between the semiconductor layer and the N-type semiconductor region.
(3)
(1) or (2) above, wherein the functional layer is a fixed charge film that is disposed along a surface of the semiconductor layer that is far from the side wall surface of the trench portion and has a negative fixed charge. The photodetection device described in .
(4)
The functional layer is a conductor portion disposed along a surface of the semiconductor layer that is far from the side wall surface of the trench portion, and to which a negative bias voltage is applied. (1) or (2) above. ).
(5)
The photodetecting device according to (4), wherein the conductor portion covers the side wall surface of the trench portion such that the trench portion has a groove-shaped space inside the trench portion, the side wall being formed by the conductor portion. .
(6)
The photodetecting device according to (4), wherein the semiconductor layer is a semiconductor layer formed at a different timing from that of the semiconductor substrate.
(7)
The photodetecting device according to (4) above, wherein the semiconductor layer is an epitaxially grown layer.
(8)
a semiconductor substrate on which a plurality of photoelectric conversion parts are formed;
A trench portion formed between the photoelectric conversion portions of the semiconductor substrate, and an element isolation portion having a P-type solid phase diffusion layer disposed within the trench portion and covering a side wall surface of the trench portion. ,
The photoelectric conversion section has an N-type semiconductor region in a region in contact with the P-type solid phase diffusion layer,
The P-type solid phase diffusion layer has an N-type impurity concentration of 1e16/cm 3 or less.
(9)
a semiconductor substrate on which a plurality of photoelectric conversion parts are formed;
A trench portion formed between the photoelectric conversion parts of the semiconductor substrate, an N-type epitaxial growth layer disposed within the trench portion and covering a side wall surface of the trench portion, and the N-type epitaxial growth layer covered with the N-type epitaxial growth layer. an element isolation part having a P-type epitaxial growth layer disposed in a space inside the trench part and in contact with the N-type epitaxial growth layer;
The N-type epitaxial growth layer has a P-type impurity concentration of 1e16/cm 3 or less,
The P-type epitaxial growth layer has an N-type impurity concentration of 1e16/cm 3 or less.
(10)
a semiconductor substrate on which a plurality of photoelectric conversion sections are formed; a trench section formed between the photoelectric conversion sections of the semiconductor substrate; a semiconductor layer disposed within the trench section and covering a side wall surface of the trench section; and an element isolation section having a functional layer disposed in a space inside the trench section covered with the semiconductor layer, and the photoelectric conversion section has an N-type semiconductor region in a region in contact with the semiconductor layer. The semiconductor layer has a P-type impurity concentration of 1e16/cm 3 or less, and the functional layer includes a photodetection device that is a layer that induces holes on the functional layer side of the semiconductor layer.
(11)
A semiconductor substrate on which a plurality of photoelectric conversion parts are formed, a trench part formed between the photoelectric conversion parts of the semiconductor substrate, and a P type disposed in the trench part and covering a side wall surface of the trench part. The photoelectric conversion section includes an element isolation section having a solid phase diffusion layer, the photoelectric conversion section has an N type semiconductor region in a region in contact with the P type solid phase diffusion layer, and the P type solid phase diffusion layer has an N type semiconductor region. An electronic device equipped with a photodetector having an impurity concentration of 1e16/cm 3 or less.
(12)
A semiconductor substrate on which a plurality of photoelectric conversion sections are formed, a trench section formed between the photoelectric conversion sections of the semiconductor substrate, and N-type epitaxial growth disposed within the trench section and covering a side wall surface of the trench section. and an element isolation portion having a P-type epitaxial growth layer disposed in a space inside the trench portion covered with the N-type epitaxial growth layer and in contact with the N-type epitaxial growth layer, the N-type epitaxial growth layer comprising a P-type epitaxial growth layer. An electronic device comprising: a photodetector having a type impurity concentration of 1e16/cm 3 or less, and the P-type epitaxial growth layer has an N-type impurity concentration of 1e16/cm 3 or less.
(13)
a step of forming a trench portion in a semiconductor substrate;
forming an epitaxial growth layer with an impurity concentration of 1e16/cm 3 or less on the sidewall surface of the trench portion by epitaxial growth;
A method for manufacturing a photodetector, comprising the step of doping a P-type impurity from within the trench portion into the epitaxial growth layer by solid-phase diffusion.
(14)
a step of forming a trench portion in a semiconductor substrate;
forming an N-type epitaxial growth layer with a P-type impurity concentration of 1e16/cm 3 or less on the side wall surface of the trench portion by epitaxial growth while adding N-type impurities;
forming a P-type epitaxial growth layer with an N-type impurity concentration of 1e16/cm 3 or less on a surface of the N-type epitaxial growth layer on the center side in the trench width direction by epitaxial growth while adding P-type impurities; A method for manufacturing a photodetection device.
　１…固体撮像装置、２…画素領域、３…垂直駆動回路、４…カラム信号処理回路、５…水平駆動回路、６…出力回路、７…制御回路、８…画素、９…画素駆動配線、１０…垂直信号線、１１…水平信号線、１２…半導体基板、１３…固定電荷膜、１４…絶縁膜、１５…遮光膜、１６…平坦化膜、１７…受光層、１８…カラーフィルタ層、１９…マイクロレンズアレイ、２０…配線層、２１…光電変換部、２２…Ｐ型半導体領域、２３…Ｎ型半導体領域、２４…Ｐ型半導体領域、２５…トレンチ部、２６…素子分離部、２７…半導体層、２７ａ…ホール誘起層、２８…カラーフィルタ、２９…マイクロレンズ、３０…マスク、３２…ドープドポリシリコン、３３…絶縁膜、３４…導体部、３５…導体部、３７…半導体層、３８…Ｐ型固相拡散層、３９…絶縁材料、４０…マスク、４１…窒化シリコン膜、４２…酸化シリコン膜、４３…半導体層、４４…酸化シリコン、４５…ドープドポリシリコン、４６…絶縁材料、４７…マスク、４８…窒化シリコン膜、４９…酸化シリコン膜、５０…トレンチ部、５１…Ｎ＋型半導体領域、５２…Ｐ型エピタキシャル成長層、５３…Ｎ型エピタキシャル成長層、５４…Ｐ型エピタキシャル成長層、５５…Ｐ型半導体領域、１０００…撮像装置、１００１…レンズ群、１００２…固体撮像装置、１００３…ＤＳＰ回路、１００４…フレームメモリ、１００５…モニタ、１００６…メモリ、１００７…バスライン DESCRIPTION OF SYMBOLS 1... Solid-state imaging device, 2... Pixel area, 3... Vertical drive circuit, 4... Column signal processing circuit, 5... Horizontal drive circuit, 6... Output circuit, 7... Control circuit, 8... Pixel, 9... Pixel drive wiring, 10... Vertical signal line, 11... Horizontal signal line, 12... Semiconductor substrate, 13... Fixed charge film, 14... Insulating film, 15... Light shielding film, 16... Flattening film, 17... Light receiving layer, 18... Color filter layer, 19... Microlens array, 20... Wiring layer, 21... Photoelectric conversion section, 22... P-type semiconductor region, 23... N-type semiconductor region, 24... P-type semiconductor region, 25... Trench section, 26... Element separation section, 27 ... Semiconductor layer, 27a... Hole inducing layer, 28... Color filter, 29... Microlens, 30... Mask, 32... Doped polysilicon, 33... Insulating film, 34... Conductor part, 35... Conductor part, 37... Semiconductor layer , 38... P-type solid phase diffusion layer, 39... Insulating material, 40... Mask, 41... Silicon nitride film, 42... Silicon oxide film, 43... Semiconductor layer, 44... Silicon oxide, 45... Doped polysilicon, 46... Insulating material, 47... Mask, 48... Silicon nitride film, 49... Silicon oxide film, 50... Trench portion, 51... N+ type semiconductor region, 52... P type epitaxial growth layer, 53... N type epitaxial growth layer, 54... P type epitaxial growth layer, 55... P-type semiconductor region, 1000... imaging device, 1001... lens group, 1002... solid-state imaging device, 1003... DSP circuit, 1004... frame memory, 1005... monitor, 1006... memory, 1007... bus line

Claims (14)

  1. 　複数の光電変換部が形成された半導体基板と、
    　前記半導体基板のうちの前記光電変換部間に形成されたトレンチ部、前記トレンチ部内に配置され、前記トレンチ部の側壁面を被覆する半導体層、及び前記半導体層で被覆された前記トレンチ部の内部の空間に配置された機能層を有する素子分離部と、を備え、
    　前記光電変換部は、前記半導体層と接する領域にＮ型半導体領域を有しており、
    　前記半導体層は、Ｐ型の不純物濃度が１ｅ１６/ｃｍ3以下であり、
    　前記機能層は、前記半導体層の前記機能層側にホールを誘起させる層である
    　光検出装置。     a semiconductor substrate on which a plurality of photoelectric conversion parts are formed;
    A trench portion formed between the photoelectric conversion parts of the semiconductor substrate, a semiconductor layer disposed within the trench portion and covering a side wall surface of the trench portion, and an interior of the trench portion covered with the semiconductor layer. an element isolation section having a functional layer arranged in a space of
    The photoelectric conversion section has an N-type semiconductor region in a region in contact with the semiconductor layer,
    The semiconductor layer has a P-type impurity concentration of 1e16/cm 3 or less,
    The functional layer is a layer that induces holes on the functional layer side of the semiconductor layer. The photodetecting device.
  2. 　前記Ｎ型半導体領域は、前記半導体層と前記Ｎ型半導体領域との界面において、Ｎ型の不純物濃度のピークを有する
    　請求項１に記載の光検出装置。     The photodetection device according to claim 1, wherein the N-type semiconductor region has an N-type impurity concentration peak at an interface between the semiconductor layer and the N-type semiconductor region.
  3. 　前記機能層は、前記半導体層の面のうちの、前記トレンチ部の側壁面から遠い側の面に沿って配置され、負の固定電荷を有する固定電荷膜である
    　請求項１に記載の光検出装置。     The photodetection according to claim 1, wherein the functional layer is a fixed charge film having a negative fixed charge and arranged along a surface of the semiconductor layer that is far from the side wall surface of the trench portion. Device.
  4. 　前記機能層は、前記半導体層の面のうちの、前記トレンチ部の側壁面から遠い側の面に沿って配置され、負のバイアス電圧が印加される導体部である
    　請求項１に記載の光検出装置。     The optical device according to claim 1, wherein the functional layer is a conductor portion that is arranged along a surface of the semiconductor layer that is far from the side wall surface of the trench portion, and to which a negative bias voltage is applied. Detection device.
  5. 　前記導体部は、前記トレンチ部の内部に側壁が前記導体部で形成された溝状の空間を有するように、前記トレンチ部の側壁面を被覆している
    　請求項４に記載の光検出装置。     The photodetecting device according to claim 4, wherein the conductor portion covers a side wall surface of the trench portion such that a groove-shaped space is formed inside the trench portion by a side wall formed by the conductor portion.
  6. 　前記半導体層は、前記半導体基板と異なるタイミングで形成された半導体層である
    　請求項１に記載の光検出装置。     The photodetection device according to claim 1, wherein the semiconductor layer is a semiconductor layer formed at a different timing than the semiconductor substrate.
  7. 　前記半導体層は、エピタキシャル成長層である
    　請求項６に記載の光検出装置。     The photodetection device according to claim 6, wherein the semiconductor layer is an epitaxially grown layer.
  8. 　複数の光電変換部が形成された半導体基板と、
    　前記半導体基板のうちの前記光電変換部間に形成されたトレンチ部、及び前記トレンチ部内に配置され、前記トレンチ部の側壁面を被覆するＰ型固相拡散層を有する素子分離部と、を備え、
    　前記光電変換部は、前記Ｐ型固相拡散層と接する領域にＮ型半導体領域を有しており、
    　前記Ｐ型固相拡散層は、Ｎ型の不純物濃度が１ｅ１６/ｃｍ3以下である
    　光検出装置。     a semiconductor substrate on which a plurality of photoelectric conversion parts are formed;
    A trench portion formed between the photoelectric conversion portions of the semiconductor substrate, and an element isolation portion having a P-type solid phase diffusion layer disposed within the trench portion and covering a side wall surface of the trench portion. ,
    The photoelectric conversion section has an N-type semiconductor region in a region in contact with the P-type solid phase diffusion layer,
    The P-type solid phase diffusion layer has an N-type impurity concentration of 1e16/cm 3 or less.
  9. 　複数の光電変換部が形成された半導体基板と、
    　前記半導体基板のうちの前記光電変換部間に形成されたトレンチ部、前記トレンチ部内に配置され、前記トレンチ部の側壁面を被覆するＮ型エピタキシャル成長層、及び前記Ｎ型エピタキシャル成長層で被覆された前記トレンチ部の内部の空間に配置され、前記Ｎ型エピタキシャル成長層と接するＰ型エピタキシャル成長層を有する素子分離部を備え、
    　前記Ｎ型エピタキシャル成長層は、Ｐ型の不純物濃度が１ｅ１６/ｃｍ3以下であり、
    　前記Ｐ型エピタキシャル成長層は、Ｎ型の不純物濃度が１ｅ１６/ｃｍ3以下である
    　光検出装置。     a semiconductor substrate on which a plurality of photoelectric conversion parts are formed;
    A trench portion formed between the photoelectric conversion parts of the semiconductor substrate, an N-type epitaxial growth layer disposed within the trench portion and covering a side wall surface of the trench portion, and the N-type epitaxial growth layer covered with the N-type epitaxial growth layer. an element isolation part having a P-type epitaxial growth layer disposed in a space inside the trench part and in contact with the N-type epitaxial growth layer;
    The N-type epitaxial growth layer has a P-type impurity concentration of 1e16/cm 3 or less,
    The P-type epitaxial growth layer has an N-type impurity concentration of 1e16/cm 3 or less.
  10. 　複数の光電変換部が形成された半導体基板、並びに前記半導体基板のうちの前記光電変換部間に形成されたトレンチ部、前記トレンチ部内に配置され、前記トレンチ部の側壁面を被覆する半導体層、及び前記半導体層で被覆された前記トレンチ部の内部の空間に配置された機能層を有する素子分離部を備え、前記光電変換部は、前記半導体層と接する領域にＮ型半導体領域を有しており、前記半導体層は、Ｐ型の不純物濃度が１ｅ１６/ｃｍ3以下であり、前記機能層は、前記半導体層の前記機能層側にホールを誘起させる層である光検出装置を備える
    　電子機器。     a semiconductor substrate on which a plurality of photoelectric conversion sections are formed; a trench section formed between the photoelectric conversion sections of the semiconductor substrate; a semiconductor layer disposed within the trench section and covering a side wall surface of the trench section; and an element isolation section having a functional layer disposed in a space inside the trench section covered with the semiconductor layer, and the photoelectric conversion section has an N-type semiconductor region in a region in contact with the semiconductor layer. The semiconductor layer has a P-type impurity concentration of 1e16/cm 3 or less, and the functional layer includes a photodetection device that is a layer that induces holes on the functional layer side of the semiconductor layer.
  11. 　複数の光電変換部が形成された半導体基板、並びに前記半導体基板のうちの前記光電変換部間に形成されたトレンチ部、及び前記トレンチ部内に配置され、前記トレンチ部の側壁面を被覆するＰ型固相拡散層を有する素子分離部を備え、前記光電変換部は、前記Ｐ型固相拡散層と接する領域にＮ型半導体領域を有しており、前記Ｐ型固相拡散層は、Ｎ型の不純物濃度が１ｅ１６/ｃｍ3以下である光検出装置を備える
    　電子機器。     A semiconductor substrate on which a plurality of photoelectric conversion parts are formed, a trench part formed between the photoelectric conversion parts of the semiconductor substrate, and a P type disposed in the trench part and covering a side wall surface of the trench part. The photoelectric conversion section includes an element isolation section having a solid phase diffusion layer, the photoelectric conversion section has an N type semiconductor region in a region in contact with the P type solid phase diffusion layer, and the P type solid phase diffusion layer has an N type semiconductor region. An electronic device equipped with a photodetector having an impurity concentration of 1e16/cm 3 or less.
  12. 　複数の光電変換部が形成された半導体基板、並びに前記半導体基板のうちの前記光電変換部間に形成されたトレンチ部、前記トレンチ部内に配置され、前記トレンチ部の側壁面を被覆するＮ型エピタキシャル成長層、及び前記Ｎ型エピタキシャル成長層で被覆された前記トレンチ部の内部の空間に配置され、前記Ｎ型エピタキシャル成長層と接するＰ型エピタキシャル成長層を有する素子分離部を備え、前記Ｎ型エピタキシャル成長層は、Ｐ型の不純物濃度が１ｅ１６/ｃｍ3以下であり、前記Ｐ型エピタキシャル成長層は、Ｎ型の不純物濃度が１ｅ１６/ｃｍ3以下である光検出装置を備える
    　電子機器。     A semiconductor substrate on which a plurality of photoelectric conversion sections are formed, a trench section formed between the photoelectric conversion sections of the semiconductor substrate, and N-type epitaxial growth disposed within the trench section and covering a side wall surface of the trench section. and an element isolation portion having a P-type epitaxial growth layer disposed in a space inside the trench portion covered with the N-type epitaxial growth layer and in contact with the N-type epitaxial growth layer, the N-type epitaxial growth layer comprising a P-type epitaxial growth layer. An electronic device comprising: a photodetector having a type impurity concentration of 1e16/cm 3 or less, and the P-type epitaxial growth layer has an N-type impurity concentration of 1e16/cm 3 or less.
  13. 　半導体基板にトレンチ部を形成する工程と、
    　エピタキシャル成長によって、前記トレンチ部の側壁面に不純物濃度が１ｅ１６/ｃｍ3以下のエピタキシャル成長層を形成する工程と、
    　固相拡散によって、前記トレンチ部内から前記エピタキシャル成長層にＰ型の不純物をドープする工程と、を含む
    　光検出装置の製造方法。     a step of forming a trench portion in a semiconductor substrate;
    forming an epitaxial growth layer with an impurity concentration of 1e16/cm 3 or less on the sidewall surface of the trench portion by epitaxial growth;
    A method for manufacturing a photodetector, comprising the step of doping a P-type impurity from within the trench portion into the epitaxial growth layer by solid-phase diffusion.
  14. 　半導体基板にトレンチ部を形成する工程と、
    　Ｎ型の不純物を添加しながらのエピタキシャル成長によって、前記トレンチ部の側壁面にＰ型の不純物濃度が１ｅ１６/ｃｍ3以下のＮ型エピタキシャル成長層を形成する工程と、
    　Ｐ型の不純物を添加しながらのエピタキシャル成長によって、前記Ｎ型エピタキシャル成長層の前記トレンチ部幅方向中心側の面にＮ型の不純物濃度が１ｅ１６/ｃｍ3以下のＰ型エピタキシャル成長層を形成する工程と、を含む
    　光検出装置の製造方法。     a step of forming a trench portion in a semiconductor substrate;
    forming an N-type epitaxial growth layer with a P-type impurity concentration of 1e16/cm 3 or less on the side wall surface of the trench portion by epitaxial growth while adding N-type impurities;
    forming a P-type epitaxial growth layer with an N-type impurity concentration of 1e16/cm 3 or less on a surface of the N-type epitaxial growth layer on the center side in the trench width direction by epitaxial growth while adding P-type impurities; A method for manufacturing a photodetection device.
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JPH08186257A (en) * 1995-01-04 1996-07-16 Nec Corp Field effect type transistor and its production
JP2006114795A (en) * 2004-10-18 2006-04-27 Matsushita Electric Ind Co Ltd Semiconductor device
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JPH08186257A (en) * 1995-01-04 1996-07-16 Nec Corp Field effect type transistor and its production
JP2006114795A (en) * 2004-10-18 2006-04-27 Matsushita Electric Ind Co Ltd Semiconductor device
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