WO2024053401A1 - Appareil de détection de lumière, dispositif numérique et procédé de production d'appareil de détection de lumière - Google Patents

Appareil de détection de lumière, dispositif numérique et procédé de production d'appareil de détection de lumière Download PDF

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WO2024053401A1
WO2024053401A1 PCT/JP2023/030367 JP2023030367W WO2024053401A1 WO 2024053401 A1 WO2024053401 A1 WO 2024053401A1 JP 2023030367 W JP2023030367 W JP 2023030367W WO 2024053401 A1 WO2024053401 A1 WO 2024053401A1
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type
layer
epitaxial growth
photoelectric conversion
trench
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PCT/JP2023/030367
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English (en)
Japanese (ja)
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慎一 吉田
尚人 北條
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ソニーセミコンダクタソリューションズ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors

Definitions

  • the present disclosure relates to a photodetection device, an electronic device, and a method of manufacturing the photodetection device.
  • a photodetection device has been proposed that has a trench portion between photoelectric conversion portions and a P-type semiconductor layer formed by epitaxial growth is disposed within the trench portion (see, for example, Patent Document 1).
  • the P-type semiconductor layer functions as a hole pinning layer to suppress the generation of dark current on the sidewall surface of the trench portion.
  • An object of the present disclosure is to provide a photodetection device, an electronic device, and a method for manufacturing a photodetection device that can improve the saturation charge amount Qs of a photoelectric conversion unit.
  • a photodetecting device of the present disclosure includes: (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed; (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate; (c) the photoelectric conversion section includes a semiconductor layer covering a side wall surface of the trench section; and an element isolation section having a functional layer disposed in a space inside the trench section covered with the semiconductor layer; It has an N-type semiconductor region in the contacting region, (d) the semiconductor layer has a P-type impurity concentration of 1e16/cm 3 or less, and (e) the functional layer has holes on the functional layer side of the semiconductor layer.
  • the gist is that it is a layer that induces
  • Another photodetection device of the present disclosure includes (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed, (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate, and a trench section disposed within the trench section. and (c) the photoelectric conversion section has an N-type semiconductor region in a region in contact with the P-type solid-phase diffusion layer. (d) The P-type solid phase diffusion layer has an N-type impurity concentration of 1e16/cm 3 or less.
  • Another photodetection device of the present disclosure includes (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed, (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate, and a trench section disposed within the trench section. , an element isolation section having an N-type epitaxial growth layer covering a side wall surface of the trench portion, and a P-type epitaxial growth layer disposed in a space inside the trench portion covered with the N-type epitaxial growth layer and in contact with the N-type epitaxial growth layer.
  • the N-type epitaxial growth layer has a P-type impurity concentration of 1e16/cm 3 or less, and (d) The P-type epitaxial growth layer has an N-type impurity concentration of 1e16/cm 3 or less. do.
  • An electronic device of the present disclosure includes (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed, (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate, and a trench section disposed within the trench section. (c) a photoelectric conversion section is provided in a region in contact with the semiconductor layer; It has an N-type semiconductor region, (d) the semiconductor layer has a P-type impurity concentration of 1e16/cm 3 or less, and (e) the functional layer is a layer that induces holes on the functional layer side of the semiconductor layer.
  • the gist is to provide a photodetecting device that is.
  • Another electronic device of the present disclosure includes (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed, (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate, and a trench section disposed within the trench section. (c) the photoelectric conversion section has an N-type semiconductor region in a region in contact with the P-type solid-phase diffusion layer; , (d) The P-type solid phase diffusion layer is provided with a photodetector having an N-type impurity concentration of 1e16/cm 3 or less.
  • Another electronic device of the present disclosure includes (a) a semiconductor substrate on which a plurality of photoelectric conversion sections are formed, (b) a trench section formed between the photoelectric conversion sections of the semiconductor substrate, and a trench section disposed within the trench section; an element isolation section having an N-type epitaxial growth layer covering a side wall surface of the trench portion, and a P-type epitaxial growth layer disposed in a space inside the trench portion covered with the N-type epitaxial growth layer and in contact with the N-type epitaxial growth layer; (c) The N-type epitaxial growth layer has a P-type impurity concentration of 1e16/cm 3 or less, and (d) The P-type epitaxial growth layer includes a photodetector having an N-type impurity concentration of 1e16/cm 3 or less.
  • the gist is that.
  • a method for manufacturing a photodetection device includes (a) forming a trench portion in a semiconductor substrate; and (b) forming an epitaxial growth layer with an impurity concentration of 1e16/cm 3 or less on the side wall surface of the trench portion by epitaxial growth. and (c) a step of doping the epitaxial growth layer with a P-type impurity from within the trench portion by solid-phase diffusion.
  • Another method of manufacturing a photodetecting device includes (a) forming a trench in a semiconductor substrate, and (b) epitaxial growth while adding N-type impurities to form a P-type on the side wall surface of the trench.
  • N is formed on the center side in the trench width direction of the N-type epitaxial growth layer.
  • the method includes the step of forming a P-type epitaxial growth layer having a type impurity concentration of 1e16/cm 3 or less.
  • FIG. 1 is a diagram showing the overall configuration of a solid-state imaging device according to a first embodiment.
  • 2 is a diagram illustrating a cross-sectional configuration of the solid-state imaging device taken along line AA in FIG. 1.
  • FIG. 3 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region B in FIG. 2 is enlarged.
  • 4 is a diagram showing the distribution of N-type impurity concentration at the position of line CC in FIG. 3.
  • FIG. FIG. 2 is a diagram showing a cross-sectional configuration of a solid-state imaging device when the semiconductor layer is of P type. It is a figure showing the manufacturing method of a solid-state imaging device. It is a figure showing the manufacturing method of a solid-state imaging device.
  • FIG. 3 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a second embodiment.
  • 9 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region D in FIG. 8 is enlarged.
  • FIG. FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification.
  • 11 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region E in FIG. 10 is enlarged.
  • FIG. FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a third embodiment.
  • 13 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region F in FIG. 12 is enlarged.
  • FIG. 3 is a diagram showing potential distribution.
  • FIG. 2 is a diagram showing a cross-sectional configuration of a solid-state imaging device having a P-type semiconductor region.
  • FIG. 3 is a diagram showing potential distribution.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method
  • FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification.
  • FIG. 20 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region G in FIG. 19 is enlarged.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification.
  • 24 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region H in FIG. 23 is enlarged.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification. 28 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region I in FIG. 27 is enlarged.
  • FIG. FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 7 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a fourth embodiment.
  • 32 is a diagram showing a cross-sectional configuration of the solid-state imaging device when region J in FIG. 31 is enlarged.
  • FIG. FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram illustrating a method of forming an element isolation section.
  • FIG. 3 is a diagram showing the overall configuration of an electronic device according to a fifth embodiment.
  • FIGS. 1 to 35 An example of a photodetection device, an electronic device, and a method of manufacturing the photodetection device according to an embodiment of the present disclosure will be described below with reference to FIGS. 1 to 35. Embodiments of the present disclosure will be described in the following order. Note that the present disclosure is not limited to the following examples. Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.
  • First embodiment Solid-state imaging device 1-1 Overall configuration of solid-state imaging device 1-2 Configuration of main parts 1-3 Manufacturing method of solid-state imaging device 1-4 Modification example 2.
  • Second embodiment Solid-state imaging device 2-1 Configuration of main parts 2-2 Modification example 3.
  • Third embodiment Solid-state imaging device 3-1 Configuration of main parts 3-2 Manufacturing method of solid-state imaging device 3-3 Modification example 4.
  • Fourth embodiment Solid-state imaging device 4-1 Configuration of main parts 4-2 Manufacturing method of solid-state imaging device 4-3 Modification example 5.
  • Fifth embodiment Application example to electronic equipment
  • FIG. 1 is a diagram showing the overall configuration of a solid-state imaging device 1 according to the first embodiment.
  • the solid-state imaging device 1 in FIG. 1 is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor.
  • CMOS Complementary Metal Oxide Semiconductor
  • the solid-state imaging device 1 (1002) captures image light (incident light) from a subject through a lens group 1001, and calculates the amount of incident light formed on the imaging surface in pixel units.
  • the solid-state imaging device 1 includes a pixel region 2, a vertical drive circuit 3, a column signal processing circuit 4, a horizontal drive circuit 5, an output circuit 6, and a control circuit 7. .
  • the pixel area 2 has a plurality of pixels 8 arranged in a two-dimensional array.
  • the pixel 8 includes the photoelectric conversion section 21 shown in FIG. 2 and a plurality of pixel transistors. Examples of the plurality of pixel transistors include four MOS transistors including a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor.
  • the vertical drive circuit 3 is configured by, for example, a shift register, selects a desired pixel drive wiring 9, supplies pulses for driving the pixels 8 to the selected pixel drive wiring 9, and drives each pixel 8 in rows.
  • the vertical drive circuit 3 sequentially selectively scans each pixel 8 in the pixel region 2 in the vertical direction row by row, and generates a pixel signal based on the signal charge generated in the photoelectric conversion section 21 of each pixel 8 according to the amount of light received. , are supplied to the column signal processing circuit 4 through the vertical signal line 10.
  • the column signal processing circuit 4 is arranged, for example, for each column of pixels 8, and performs signal processing such as noise removal on the signals output from the pixels 8 of one row for each pixel column.
  • the column signal processing circuit 4 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog Digital) conversion to remove fixed pattern noise specific to pixels.
  • the horizontal drive circuit 5 is configured by, for example, a shift register, and sequentially outputs horizontal scanning pulses to the column signal processing circuits 4 to select each of the column signal processing circuits 4 in turn, and selects each of the column signal processing circuits 4 from each of the column signal processing circuits 4 in turn.
  • the pixel signal subjected to signal processing is output to the horizontal signal line 11.
  • the output circuit 6 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 4 through the horizontal signal line 11, and outputs the processed pixel signals.
  • signal processing for example, buffering, black level adjustment, column variation correction, various digital signal processing, etc. can be used.
  • the control circuit 7 generates clock signals and control signals that serve as operating standards for the vertical drive circuit 3, column signal processing circuit 4, horizontal drive circuit 5, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. generate. Then, the control circuit 7 outputs the generated clock signal and control signal to the vertical drive circuit 3, column signal processing circuit 4, horizontal drive circuit 5, and the like.
  • FIG. 2 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 taken along line AA in FIG.
  • FIG. 3 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 when region B in FIG. 2 is enlarged.
  • the solid-state imaging device 1 includes a semiconductor substrate 12, a fixed charge film 13 (“functional layer” in a broad sense), an insulating film 14, a light shielding film 15, and a planarization film 16 stacked in this order.
  • a light-receiving layer 17 is disposed.
  • a color filter layer 18 and a microlens array 19 are arranged in this order.
  • a wiring layer 20 is arranged on the surface of the light-receiving layer 17 on the semiconductor substrate 12 side (hereinafter also referred to as "surface S2").
  • the semiconductor substrate 12 is made of silicon (Si), for example.
  • a photoelectric conversion section 21 is formed in each region of each pixel 8 on the semiconductor substrate 12 . That is, a plurality of photoelectric conversion units 21 are arranged in a two-dimensional array on the semiconductor substrate 12.
  • the photoelectric conversion unit 21 includes a P-type semiconductor region 22 containing a P-type impurity, and a P-type semiconductor region 22 containing a P-type impurity on the light incident surface (hereinafter also referred to as "back surface S3") side and the front surface S2 side of the semiconductor substrate 12, respectively.
  • a P-type semiconductor region 24 is formed.
  • an N-type semiconductor region 23 that is continuous in the thickness direction of the semiconductor substrate 12 is in contact with the semiconductor layer 27 surrounding the photoelectric conversion section 21. is formed. That is, the photoelectric conversion section 21 has an N-type semiconductor region 23 in a region in contact with the semiconductor layer 27 .
  • the semiconductor layer 27 is a layer that covers the side wall surface S4 of the trench section 25 formed between the photoelectric conversion sections 21.
  • boron (B) can be used as the P-type impurity.
  • the N-type impurity for example, phosphorus (P) or arsenic (As) can be used.
  • the photoelectric conversion section 21 constitutes a photodiode by a PN junction between a junction surface between the P-type semiconductor region 22 and the N-type semiconductor region 23 and a junction surface between the P-type semiconductor region 24 and the N-type semiconductor region 23. Then, photoelectric conversion is performed to generate charges according to the amount of received light. Further, the photoelectric conversion unit 21 accumulates charges generated by photoelectric conversion in the N-type semiconductor region 23 .
  • the N-type impurity concentration is higher on the trench portion 25 side than on the central portion side of the photoelectric conversion section 21, and the N-type impurity concentration is higher on the trench portion 25 (semiconductor The N-type impurity concentration has a peak at the interface between the layer 27) and the N-type semiconductor region 23.
  • the N-type impurity concentration near the interface can be increased, and the amount of charge that can be accumulated in the photoelectric conversion section 21 (ie, the saturated charge amount Qs) can be increased.
  • the higher the N-type impurity concentration the darker the color. Further, in FIG.
  • FIG. 4 is a diagram showing the distribution of N-type impurity concentration at the position of line CC in FIG. Further, the N-type semiconductor region 23 has a constant N-type impurity concentration in the thickness direction of the semiconductor substrate 12. Therefore, the peak of the N-type impurity concentration at the interface between the trench portion 25 (semiconductor layer 27) and the N-type semiconductor region 23 is continuous in the thickness direction of the semiconductor substrate 12.
  • the amount of charge that can be stored on the back surface S3 side of the semiconductor substrate 12 and the amount of charge that can be stored on the front surface S2 side can be increased, and the saturated charge amount Qs can be further increased.
  • the impurity concentration distribution of the N-type semiconductor region 23 and the semiconductor layer 27 shown in FIG. 4 can be obtained by, for example, analyzing with Nano-SIMS (Secondary Ion Mass Spectrometry).
  • a trench portion 25 is formed in the semiconductor substrate 12 between adjacent photoelectric conversion portions 21 .
  • the trench portion 25 is formed along the side surface of the photoelectric conversion portion 21 from the front surface S2 to the back surface S3 of the semiconductor substrate 12. That is, the trench portions 25 are formed in a grid pattern on the semiconductor substrate 12 so as to surround each of the photoelectric conversion portions 21 .
  • the trench portion 25 forms an element isolation portion 26 together with the semiconductor layer 27, the fixed charge film 13, and the insulating film 14.
  • a semiconductor layer 27 is arranged to cover the side wall surface S4 of the trench portion 25. The semiconductor layer 27 is formed to surround each of the photoelectric conversion parts 21 when viewed from the thickness direction of the semiconductor substrate 12.
  • the semiconductor layer 27 for example, a non-doped semiconductor layer formed at a different timing from the semiconductor substrate 12, such as a non-doped epitaxial growth layer, can be used.
  • the epitaxial growth layer is a semiconductor layer formed by epitaxially growing a semiconductor crystal.
  • the P-type impurity concentration of the semiconductor layer 27 is 1e16/cm 3 or less (low value).
  • the semiconductor layer 27 can suppress the diffusion of P-type impurities from the semiconductor layer 27 into the photoelectric conversion section 21, as shown in FIG. Erosion of the N-type semiconductor region 23 can be suppressed. Therefore, a decrease in the saturation charge amount Qs of the photoelectric conversion section 21 can be suppressed. That is, the saturation charge amount Qs of the photoelectric conversion section 21 can be improved.
  • the N-type of the semiconductor layer 27 is The impurity concentration was 1e16/cm 3 or less.
  • a semiconductor layer for example, an epitaxially grown layer
  • an impurity concentration of 1e16/cm 3 or less is formed as the semiconductor layer 27. Therefore, almost all of the N-type impurities in the semiconductor layer 27 are diffused from the N-type semiconductor region 23.
  • the N-type impurity concentration (1e16/cm 3 or less) of the semiconductor layer 27 is achieved by adjusting the thickness of the N-type semiconductor region 23 and the semiconductor layer 27, etc.
  • the layer thickness (film thickness) of the semiconductor layer 27 for example, 10 nm or more can be adopted.
  • the hole inducing layer 27a can be formed by the fixed charge film 13 on the inner side surface S5 side of the semiconductor layer 27, as described later.
  • the material of the semiconductor layer 27 for example, the same material as the semiconductor substrate 12 (for example, silicon (Si)) can be used.
  • the inner side surface S5 of the semiconductor layer 27 is covered with the fixed charge film 13. That is, the fixed charge film 13 is arranged in a space inside the trench portion 25 covered with the semiconductor layer 27, along the inner side surface S5 of the semiconductor layer 27.
  • a material for the fixed charge film 13 for example, a material that can be deposited on the semiconductor layer 27 to generate negative fixed charges and realize pinning can be used.
  • a high refractive index material film or a high dielectric constant film having a negative fixed charge can be used.
  • oxides or nitrides Al 2 O 3 , HfO 2 , Ta 2 O 5 , etc.
  • a hole inducing layer 27a (also referred to as a "hole inducing layer 27a") is formed, and pinning of the sidewalls of the trench portion 25 is realized.
  • the fixed charge film 13 is a layer that induces holes on the fixed charge film 13 side (the inner side surface S5 side) of the semiconductor layer 27.
  • an insulating film 14 is embedded in a groove-shaped space inside the trench portion 25 covered with the semiconductor layer 27 and the fixed charge film 13.
  • the material of the insulating film 14 for example, silicon oxide (SiO 2 ) or silicon nitride (SiN) can be used.
  • the insulating film 14 prevents the occurrence of electrical color mixing between adjacent photoelectric conversion units 21 due to crosstalk in which charges photoelectrically converted in one photoelectric conversion unit 21 move to the other photoelectric conversion unit 21. suppressed.
  • the fixed charge film 13 covers the bottom surface of the trench portion 25 and the back surface S3 of the semiconductor substrate 12 together with the semiconductor layer 27. Further, the insulating film 14 not only fills the trench portion 25 but also covers the light incident surface (hereinafter also referred to as "back surface S7") of the fixed charge film 13.
  • the light shielding film 15 is disposed on the light incident surface (hereinafter also referred to as "back surface S8") side of the insulating film 14, and is formed so as to open the light incident surface of each of the photoelectric conversion sections 21.
  • the planarization film 16 is disposed on the back surface S8 side of the insulating film 14, and continuously covers the back surface S8 and the light shielding film 15 so that the back surface S1 side of the light-receiving layer 17 becomes a flat surface.
  • the material of the insulating film 14 for example, silicon oxide (SiO 2 ) or silicon nitride (SiN) can be used.
  • the color filter layer 18 is formed on the back surface S1 side of the planarizing film 16, and includes a plurality of color filters 28 arranged corresponding to the photoelectric conversion sections 21. That is, one color filter 28 is formed for one photoelectric conversion section 21.
  • the plurality of color filters 28 include a plurality of types of color filters that transmit light of a predetermined wavelength included in the light condensed by the microlens 29. As a result, each of the color filters 28 transmits light of a predetermined wavelength corresponding to the color filter 28, and the transmitted light is incident on the photoelectric conversion unit 21.
  • the microlens array 19 is formed on the back surface S9 side (light receiving surface side) of the color filter layer 18, and has a plurality of microlenses 29 arranged corresponding to the photoelectric conversion sections 21. That is, one microlens 29 is formed for one photoelectric conversion section 21. Thereby, each of the microlenses 29 collects image light (incident light) from the subject, and causes the collected incident light to enter the corresponding photoelectric conversion unit 21 via the color filter 28.
  • the wiring layer 20 is arranged on the surface S2 side of the semiconductor substrate 12.
  • the wiring layer 20 includes an interlayer insulating film and wiring (not shown) stacked in multiple layers with the interlayer insulating film interposed therebetween.
  • the wiring layer 20 drives the pixel transistor of each pixel 8 via multiple layers of wiring.
  • the solid-state imaging device 1 having the above configuration, light is irradiated from the back surface S3 side of the semiconductor substrate 12, the irradiated light is transmitted through the microlens 29 and the color filter 28, and the transmitted light is photoelectrically converted by the photoelectric conversion unit 21.
  • the signal charge is generated by conversion.
  • the generated signal charge is then output as a pixel signal from the vertical signal line 10 of FIG. 1 formed by the wiring of the wiring layer 20.
  • the hole inducing layer 27a is formed on the fixed charge film 13 side of the semiconductor layer 27 by the fixed charge film 13, and pinning of the side wall of the trench portion 25 is realized. This pinning suppresses dark current generated on the sidewalls of the trench portion 25.
  • FIG. 5 illustrates a case where the width of the N-type semiconductor region 23 is reduced from W 1 to W 2 due to erosion by P-type impurities. Therefore, there was a possibility that the saturation charge amount Qs of the photoelectric conversion section 21 would decrease.
  • the higher the P-type impurity concentration the darker the color.
  • a curve indicating the P-type impurity concentration is shown by a broken line superimposed on the P+-type semiconductor layer 27.
  • the pixels 8 are made smaller.
  • the pixel 8 is miniaturized in the solid-state imaging device 1 shown in FIG. 23 also occurs, which may make it difficult to secure the necessary saturation charge amount Qs.
  • the semiconductor layer 27 is configured to have a P-type impurity concentration of 1e16/cm 3 or less. Therefore, diffusion of P-type impurities from the semiconductor layer 27 into the photoelectric conversion section 21 can be suppressed, and erosion of the N-type semiconductor region 23 within the photoelectric conversion section 21 can be suppressed.
  • FIG. 3 illustrates a case where the width of the N-type semiconductor region 23 is maintained at W 1 without being corroded by P-type impurities. Therefore, it is possible to suppress a decrease in the amount of charge that can be accumulated in the photoelectric conversion section 21 (the amount of saturated charge Qs).
  • the saturation charge amount Qs of the photoelectric conversion section 21 can be improved. Furthermore, even when the pixels 8 are miniaturized, the N-type semiconductor region 23 does not decrease due to the diffusion of P-type impurities, so the necessary saturation charge amount Qs can be secured, and the solid-state imaging device 1 can have a large number of pixels. can be realized relatively easily.
  • a method for manufacturing the solid-state imaging device 1 according to the first embodiment will be described.
  • a mask 30 having an opening at a position where the trench portion 25 is to be formed is formed on the surface S2 of the semiconductor substrate 12.
  • anisotropic dry etching is performed through the mask 30 to form the trench portion 25.
  • the processing damage during the formation of the trench portion 25 can be recovered using the heat treatment performed in the later process. white spots and dark current can be suppressed.
  • the N-type semiconductor region 23 of the photoelectric conversion section 21 is formed on the side wall surface S4 of the trench section 25 using a conformal doping technique, as shown in FIG. 6B.
  • the N-type semiconductor region 23 can be formed by a process of introducing N-type impurities from the inside of the trench portion 25.
  • a method for doping with N-type impurities for example, solid phase diffusion, plasma doping, and ion implantation can be used. Note that in FIG. 6B, only the portions of the N-type semiconductor region 23 shown in dark colors in FIG. 3 (only the portions where the N-type impurity concentration is high) are expressed with dots. Further, similar expressions were used in FIGS. 6C to 6H.
  • a semiconductor crystal for example, silicon (Si)
  • Si silicon
  • the trench portion 25 is grown so as to cover the side wall surface S4 and the bottom surface of the trench portion 25.
  • a semiconductor layer 27 is formed inside.
  • an epitaxially grown layer having an impurity concentration of 1e16/cm 3 or less is formed.
  • silicon oxide (SiO) 31 and doped polysilicon 32 are embedded in this order into the space inside the trench portion 25 covered with the semiconductor layer 27. Subsequently, as shown in FIG.
  • a wiring layer 20 is formed on the surface S2 side of the semiconductor substrate 12. Subsequently, after bonding the sensor substrate including the semiconductor substrate 12 and the wiring layer 20 and the logic substrate (not shown), the semiconductor substrate 12 is bonded to the back surface S3 side as shown in FIG. 6F using CMP technology. Polish it to make it thinner. Subsequently, as shown in FIG. 6G, silicon oxide 31 and doped polysilicon 32 are removed from within trench portion 25. Subsequently, as shown in FIG. 6H, the fixed charge film 13 and the insulating film 14 are formed in this order within the trench portion 25. Subsequently, as shown in FIG.
  • a light shielding film 15, a planarization film 16, a color filter layer 18, and a microlens array 19 are formed in this order on the back surface S8 of the insulating film 14. In this way, the solid-state imaging device 1 according to the first embodiment is manufactured.
  • the semiconductor layer 37 is formed in a process (FEOL process) before joining the sensor substrate and the logic board or thinning the semiconductor substrate 12.
  • FEOL process a process
  • it may be formed after the FEOL process.
  • silicon oxide (SiO) 31 and doped polysilicon 32 are placed in the space inside the trench portion 25 in this order. Embed.
  • a wiring layer 20 is formed on the surface S2 side of the semiconductor substrate 12.
  • the back surface of the semiconductor substrate 12 is polished using CMP (Chemical Mechanical Polishing) technology, as shown in FIG. 7C. Polish from the S3 side to make it thinner.
  • CMP Chemical Mechanical Polishing
  • silicon oxide (SiO) 31 and doped polysilicon 32 are removed from inside the trench portion 25.
  • a semiconductor crystal for example, silicon (Si)
  • Si silicon
  • FIG. 6G a semiconductor crystal (for example, silicon (Si)) is epitaxially grown on the side wall surface S4 of the trench portion 25, and the trench portion 25 is grown so as to cover the side wall surface S4 and the bottom surface of the trench portion 25.
  • a semiconductor layer 27 is formed inside.
  • the fixed charge film 13 and the insulating film 14 are formed in this order within the trench portion 25.
  • a light shielding film 15, a planarization film 16, a color filter layer 18, and a microlens array 19 are formed in this order on the back surface S8 of the insulating film 14.
  • FIG. 8 is a diagram showing a cross-sectional configuration of a solid-state imaging device 1 according to the second embodiment.
  • FIG. 9 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 when region D in FIG. 8 is enlarged.
  • parts corresponding to those in FIGS. 2 and 3 are denoted by the same reference numerals, and redundant explanation will be omitted.
  • the conductor portions 34 to which voltage is applied are embedded in this order.
  • An inner side surface S5 of the semiconductor layer 27 is covered with an insulating film 33.
  • the conductor section 34 and the photoelectric conversion section 21 are insulated by the insulating film 33.
  • silicon oxide (SiO) or a high dielectric constant insulating film can be used, for example.
  • a conductor portion 34 is embedded in a groove-shaped space inside the trench portion 25 covered with the semiconductor layer 27 and the insulating film 33.
  • the conductor portion 34 is arranged along the inner side surface S5 of the semiconductor layer 27 with the insulating film 33 interposed therebetween.
  • the material of the conductor portion 34 for example, polysilicon doped with boron (B) or a metal material can be used.
  • a negative bias voltage is applied to the conductor portion 34.
  • holes are induced by the conductor part 34 on the conductor part 34 side (inner side surface S5 side) of the semiconductor layer 27, and the high hole concentration state (hole inducing layer 27a ) is formed, and pinning of the side wall of the trench portion 25 is realized. By this pinning, dark current generated on the sidewalls of the trench portion 25 can be suppressed.
  • Examples of methods for applying a negative bias voltage to the conductor portion 34 include a method of supplying power from the logic board (not shown) side and a method of applying it from the back surface S3 side of the semiconductor substrate 12.
  • the second embodiment shows an example in which the conductor portion 34 is embedded in the space inside the trench portion 25
  • other configurations may also be adopted.
  • the side wall surface S4 of the trench portion 25 is formed so that the conductor portion 34 has a groove-shaped space inside the trench portion 25, the side wall portion of which is formed by the conductor portion 34.
  • polysilicon has the property of absorbing light. Therefore, for example, when the conductor portion 34 shown in FIGS. 8 and 9 is formed of polysilicon, that is, when the polysilicon is embedded in the space inside the trench portion 25 (filled configuration), the quantum There was a possibility that the efficiency QE would decrease.
  • the conductor portion 35 is formed so as to have a groove-shaped space inside the trench portion 25. Therefore, for example, when the conductor portion 34 is formed of polysilicon, the amount of polysilicon can be reduced by the space inside the trench portion 25, and light absorption by the polysilicon can be suppressed. As a result, a decrease in quantum efficiency QE can be suppressed.
  • FIG. 12 is a diagram showing a cross-sectional configuration of a solid-state imaging device 1 according to the third embodiment.
  • FIG. 13 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 when region F in FIG. 12 is enlarged.
  • parts corresponding to those in FIGS. 8 and 9 are designated by the same reference numerals, and redundant explanation will be omitted.
  • the third embodiment differs from the second embodiment in that, as shown in FIGS. 12 and 13, a P-type solid phase diffusion layer 38 is used instead of the semiconductor layer 27 shown in FIG. .
  • the P-type solid phase diffusion layer 38 is a layer that is disposed within the trench portion 25 and covers the side wall surface S4 of the trench portion 25.
  • a semiconductor layer obtained by introducing a P-type impurity (for example, boron (B)) into a non-doped epitaxial growth layer by solid-phase diffusion can be employed.
  • the N-type impurity concentration of the P-type solid phase diffusion layer 38 is 1e16/cm 3 or less (a low value).
  • FIG. 13 a curve showing the N-type impurity concentration overlapping the N-type semiconductor region 23 and the P-type solid phase diffusion layer 38 is shown by a broken line, and a curve showing the P-type impurity concentration is shown by a dashed line.
  • FIG. 14 is a diagram showing the potential distribution. Moreover, in FIG.
  • N-type and P-type impurity concentration distributions shown in FIG. 13 can be obtained by performing analysis using Nano-SIMS, for example.
  • the photoelectric conversion section 21 has an N-type semiconductor region 23 in a region in contact with the P-type solid phase diffusion layer 38 .
  • the N-type semiconductor region 23 for example, a semiconductor region obtained by ion-implanting N-type impurities from the surface S2 side of the semiconductor substrate 12 is used. Thereby, as shown in FIG. 13, the N-type impurity concentration of the N-type semiconductor region 23 is constant at each depth from the surface S2.
  • FIG. 12 illustrates a case where the fixed charge film 13 shown in FIG. 8 is omitted.
  • first element isolation section 26a a portion of the element isolation section 26 on the back surface S3 side
  • second element isolation section 26b a portion on the front surface S2 side
  • the width of the second element isolation part 26b is formed wider than the width of the first element isolation part 26a.
  • an insulating material 39 is embedded inside the second element isolation section 26b.
  • a P-type impurity is ion-implanted into the N-type semiconductor region 23 from the side wall surface S4 of the trench portion 25.
  • the P-type semiconductor region 55 is used, N-type impurities are mixed into the P-type semiconductor region 55, and a potential gradient due to the PN junction between the P-type semiconductor region 55 and the N-type semiconductor region 23 is created as shown in FIG. becomes more gradual. Therefore, the saturation charge amount Qs of the photoelectric conversion section 21 may decrease.
  • FIG. 15 instead of the P-type solid phase diffusion layer 38, a P-type impurity is ion-implanted into the N-type semiconductor region 23 from the side wall surface S4 of the trench portion 25.
  • FIG. 16 is a diagram showing the potential distribution. Further, in FIG. 16, a curve showing the potential distribution is shown by a broken line overlapping the N-type semiconductor region 23 and the P-type semiconductor region 55.
  • the P-type solid phase diffusion layer 38 has an N-type impurity concentration of 1e16/cm 3 or less. Therefore, it is possible to prevent N-type impurities from being mixed into the P-type solid-phase diffusion layer 38, to steepen the potential gradient due to the PN junction between the P-type solid-phase diffusion layer 38 and the N-type semiconductor region 23, and to make the photoelectric conversion section
  • the saturation charge amount Qs of 21 can be improved. Furthermore, even when the pixels 8 are miniaturized, the necessary saturation charge amount Qs can be ensured, and the solid-state imaging device 1 can be made to have a large number of pixels with relative ease.
  • a method for manufacturing the solid-state imaging device 1 according to the third embodiment will be described.
  • N-type impurities for example, phosphorus (P), arsenic (As)
  • P phosphorus
  • As arsenic
  • an N-type semiconductor region 23 is formed.
  • the N-type semiconductor region 23 has a constant N-type impurity concentration at each depth from the surface S2.
  • a mask 40 having an opening at a position where the trench portion 25 is to be formed is formed on the surface S2 of the semiconductor substrate 12.
  • the mask 40 is constructed by laminating a silicon nitride (SiN) film 41 and a silicon oxide (SiO) film 42. Subsequently, anisotropic dry etching is performed through the mask 40 to form the trench portion 25.
  • SiN silicon nitride
  • SiO silicon oxide
  • a semiconductor crystal (silicon (Si)) is epitaxially grown on the side wall surface S4 of the trench portion 25, and a semiconductor crystal (silicon (Si)) is grown in the trench portion 25 so as to cover the side wall surface S4 and the bottom surface of the trench portion 25.
  • a semiconductor layer 43 is formed.
  • the semiconductor layer 43 is formed by covering the surface S2 side of the trench portion 25 with the silicon nitride film 41, and is performed only at the position where the first element isolation portion 26a (see FIG. 12) is to be formed.
  • As the semiconductor layer 43 a non-doped epitaxial growth layer with an impurity concentration of 1e16/cm 3 or less is formed.
  • a P-type impurity for example, boron (B)
  • B boron
  • silicon oxide (SiO) 44 and doped polysilicon 45 are embedded in this order into the space inside the trench portion 25 covered with the P-type solid phase diffusion layer 38.
  • the silicon oxide 44 is buried so as to cover the side surfaces of the P-type solid phase diffusion layer 38.
  • the doped polysilicon 45 is buried until the doped polysilicon 45 covers the entire surface S10 of the mask 40.
  • an etch-back is performed to remove the doped polysilicon 45 from the surface S10 of the mask 40 and the position in the trench portion 25 where the insulating material 39 (see FIG. 12) is buried.
  • FIG. 17E an etch-back is performed to remove the doped polysilicon 45 from the surface S10 of the mask 40 and the position in the trench portion 25 where the insulating material 39 (see FIG. 12) is buried.
  • an insulating material 46 is embedded in the surface S2 side of the trench portion 25.
  • the insulating material 46 is embedded until the insulating material 46 covers the entire surface S10 of the mask 40.
  • the insulating material 46 is polished from the surface S11 side using the CMP technique to form the insulating material 39.
  • the element isolation portion 26 shown in FIG. 12 is formed.
  • an insulating film 14, a light shielding film 15, a planarizing film 16, a color filter layer 18, and a microlens array 19 are formed. In this way, the solid-state imaging device 1 shown in FIG. 12 is manufactured.
  • the configuration of the second element isolation part 26b when formed by this manufacturing method is slightly different from the configuration of the second element isolation part 26b when formed by the above-mentioned formation method. It becomes the composition.
  • N-type impurity ions are implanted into the P-type semiconductor substrate 12 to form the N-type semiconductor region 23.
  • etching is performed from the surface S2 side of the semiconductor substrate 12 through a mask (not shown) to form the trench portion 25.
  • a mask not shown
  • a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25, etc., so as to continuously cover the entire side wall surface S4 and the bottom surface of the trench portion 25, as well as the surface S2 of the semiconductor substrate 12.
  • a semiconductor layer 43 is formed within the trench portion 25 and on the surface S2 of the semiconductor substrate 12.
  • a non-doped epitaxial growth layer with an impurity concentration of 1e16/cm 3 or less is formed.
  • a P-type impurity for example, boron (B)
  • B solid-phase diffusion method
  • the semiconductor layer 43 is changed to the P-type solid phase diffusion layer 38. This can prevent N-type impurities from being mixed into the P-type solid-phase diffusion layer 38, and the concentration of N-type impurities in the P-type solid-phase diffusion layer 38 can be set to 1e16/cm 3 or less.
  • silicon oxide (SiO) 44 and doped polysilicon 45 are embedded in this order into the space inside the trench portion 25 covered with the P-type solid phase diffusion layer 38.
  • the silicon oxide 44 is buried so as to cover the side surfaces of the P-type solid phase diffusion layer 38.
  • the doped polysilicon 45 is buried until the doped polysilicon 45 covers the entire surface S12 of the silicon oxide 44.
  • the surface S2 of the semiconductor substrate 12 is exposed by polishing or the like from the surface S2 side of the semiconductor substrate 12 using CMP technology or etchback. Subsequently, as shown in FIG.
  • a mask 47 having an opening at a position where the second element isolation portion 26b (see FIG. 12) is to be formed is formed on the surface S2 of the semiconductor substrate 12.
  • the mask 47 is constructed by laminating a silicon nitride (SiN) film 48 and a silicon oxide (SiO) film 49.
  • SiN silicon nitride
  • SiO silicon oxide
  • FIG. 18G etching is performed through the mask 47 to form a portion of the trench portion 25 where the second element isolation portion 26b (see FIG. 12) is to be formed (hereinafter also referred to as “trench portion 50”). form).
  • an insulating material 46 is embedded in the trench portion 50.
  • the insulating material 46 is embedded until the insulating material 46 covers the entire surface S10 of the mask 47. Subsequently, as shown in FIG. 18I, the insulating material 46 is polished from the surface S11 side using the CMP technique to form the insulating material 39 shown in FIG. 12. Through such a procedure, the element isolation portion 26 shown in FIG. 12 is formed. Subsequently, as shown in FIG. 12, an insulating film 14, a light shielding film 15, a planarizing film 16, a color filter layer 18, and a microlens array 19 are formed. In this way, the solid-state imaging device 1 shown in FIG. 12 is manufactured.
  • N-type semiconductor region 23 is provided as the N-type region of the photoelectric conversion section 21, but other configurations may also be adopted.
  • FIGS. 19 and 20 as part of the N-type semiconductor region 23, an N-type semiconductor with a relatively high N-type impurity concentration is added to a region of the photoelectric conversion section 21 that is in contact with the trench section 25.
  • a structure having a region hereinafter also referred to as "N+ type semiconductor region 51" may be used.
  • a PN junction is formed between the P-type solid phase diffusion layer 38 and the N+ type semiconductor region 51 (a region with a relatively high N-type impurity concentration), so that the potential gradient can be made steeper, and the photoelectric conversion section 21
  • the saturation charge amount Qs can be increased.
  • the curve showing the N-type impurity concentration overlapping the N-type semiconductor region 23 and the P-type solid phase diffusion layer 38 is shown by a broken line, and the curve showing the P-type impurity concentration is shown by a dashed line.
  • a method for forming the element isolation portion 26 when adopting such a configuration will be described.
  • a manufacturing method similar to the manufacturing method shown in FIGS. 17A to 17G first, similar to the process shown in FIG. 17A, an N-type impurity is ion-implanted into the P-type semiconductor substrate 12, A semiconductor region 23 is formed. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through the mask 40 to form the trench portion 25. Subsequently, as shown in FIG. 21, N type impurity ions are implanted from within the trench portion 25 to form an N+ type semiconductor region 51 on the side wall surface S4 and the bottom surface of the trench portion 25. Subsequently, similarly to the step shown in FIG.
  • a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25, and a semiconductor layer 43 is formed in the trench portion 25 so as to cover the side wall surface S4 and the bottom surface of the trench portion 25. form.
  • the element isolation portion 26 shown in FIG. 19 is formed.
  • an N-type impurity is added to the P-type semiconductor substrate 12 in the same manner as the step shown in FIG. 18A. is ion-implanted to form an N-type semiconductor region 23. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through a mask (not shown) to form the trench portion 25. Subsequently, as shown in FIG. 22A, N type impurity ions are implanted from within the trench portion 25 to form an N + type semiconductor region 51 on the entire sidewall surface S4 and the bottom surface of the trench portion 25. Subsequently, similarly to the step shown in FIG.
  • a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25 to continuously cover the entire side wall surface S4 and the bottom surface of the trench portion 25, as well as the surface S2 of the semiconductor substrate 12.
  • the semiconductor layer 43 is formed in the trench portion 25 and on the surface S2 of the semiconductor substrate 12 so as to do so.
  • the element isolation portion 26 shown in FIG. 22B is formed. Note that, as shown in FIG. 22B, the configuration of the second element isolation part 26b when formed by this formation method is the same as the configuration of the second element isolation part 26b when formed by the above-mentioned formation method (the second element isolation part 26b in FIG. 19). The configuration is slightly different from the configuration of the element isolation section 26b.
  • the P-type solid phase diffusion layer 38 is provided as the P-type layer of the element isolation section 26, but other configurations may also be adopted.
  • a P-type epitaxial growth layer 52 formed by epitaxial growth while adding P-type impurities may be used instead of the P-type solid phase diffusion layer 38.
  • the P-type impurity is added to the N-type semiconductor region 23 when forming this layer. may be ion-implanted.
  • the P-type impurity is not mixed into the N-type semiconductor region 23 as shown in FIG. 24 when the P-type epitaxial growth layer 52 is formed. Therefore, since a PN junction is formed between the N-type semiconductor region 23 with a low P-type impurity concentration and the P-type epitaxial growth layer 52, the potential gradient can be made steeper, and the saturated charge amount Qs of the photoelectric conversion section 21 can be increased. be able to.
  • the curve showing the N-type impurity concentration overlapping the N-type semiconductor region 23 and the P-type solid phase diffusion layer 38 is shown by a broken line, and the curve showing the P-type impurity concentration is shown by a dashed line.
  • a method for forming the element isolation portion 26 when adopting such a configuration will be described.
  • a manufacturing method similar to the manufacturing method shown in FIGS. 17A to 17G first, similar to the process shown in FIG. 17A, an N-type impurity is ion-implanted into the P-type semiconductor substrate 12, A semiconductor region 23 is formed. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through the mask 40 to form the trench portion 25. Subsequently, as shown in FIG. 25, a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25 while adding a P-type impurity, and the trench portion is grown so as to cover the side wall surface S4 and the bottom surface of the trench portion 25. A P-type epitaxial growth layer 52 is formed within 25. Thereafter, by omitting the step shown in FIG. 17C and passing through the steps shown in FIGS. 17D to 17G, the element isolation portion 26 shown in FIG. 23 is formed.
  • an N-type impurity is added to the P-type semiconductor substrate 12 in the same manner as the step shown in FIG. 18A. is ion-implanted to form an N-type semiconductor region 23.
  • etching is performed from the surface S2 side of the semiconductor substrate 12 through a mask (not shown) to form the trench portion 25.
  • a semiconductor crystal is epitaxially grown while adding P-type impurities to the sidewall surface S4 of the trench portion 25, etc., so that the entire sidewall surface S4 and bottom surface of the trench portion 25, as well as the semiconductor substrate 12 are grown.
  • a P-type epitaxial growth layer 52 is formed in the trench portion 25 and on the surface S2 of the semiconductor substrate 12 so as to continuously cover the surface S2. Thereafter, by omitting the step shown in FIG. 18C and passing through the steps shown in FIGS. 18D to 18I, the element isolation portion 26 shown in FIG. 26B is formed. Note that, as shown in FIG. 26B, the configuration of the second element isolation part 26b when formed by this formation method is different from the configuration of the second element isolation part 26b when formed by the above-mentioned formation method (the second element isolation part 26b in FIG. 23). The configuration is slightly different from the configuration of the element isolation section 26b.
  • the N+ type semiconductor region 51 shown in FIG. 19 and the P type semiconductor region 51 shown in FIG. A structure including an epitaxial growth layer 52 may also be used. Thereby, the saturated charge amount Qs of the photoelectric conversion section 21 can be increased.
  • a curve showing the N-type impurity concentration overlapping the N-type semiconductor region 23 and the P-type solid phase diffusion layer 38 is shown by a broken line, and a curve showing the P-type impurity concentration is shown by a dashed line.
  • a method of forming the element isolation portion 26 when such a configuration is adopted will be described. When adopting a manufacturing method similar to the manufacturing method shown in FIGS.
  • a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25 while adding a P-type impurity, and the trench portion is grown so as to cover the side wall surface S4 and the bottom surface of the trench portion 25.
  • a P-type epitaxial growth layer 52 is formed within 25.
  • an N-type impurity is added to the P-type semiconductor substrate 12 in the same manner as the step shown in FIG. 18A. is ion-implanted to form an N-type semiconductor region 23. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through a mask (not shown) to form the trench portion 25. Subsequently, similarly to the step shown in FIG. 22A, N type impurity ions are implanted from within the trench portion 25 to form an N + type semiconductor region 51 on the entire sidewall surface S4 and the bottom surface of the trench portion 25. Subsequently, as shown in FIG.
  • a semiconductor crystal is epitaxially grown while adding P-type impurities to the sidewall surface S4 of the trench portion 25, etc., so that the entire sidewall surface S4 and bottom surface of the trench portion 25 and the semiconductor substrate 12 are grown.
  • a P-type epitaxial growth layer 52 is formed in the trench portion 25 and on the surface S2 of the semiconductor substrate 12 so as to continuously cover the surface S2. Thereafter, by omitting the step shown in FIG. 18C and passing through the steps shown in FIGS. 18D to 18I, the element isolation portion 26 shown in FIG. 30B is formed. Note that, as shown in FIG.
  • the configuration of the second element isolation part 26b when formed by this formation method is different from the configuration of the second element isolation part 26b when formed by the above-mentioned formation method (the second element isolation part 26b in FIG. 27).
  • the configuration is slightly different from the configuration of the element isolation section 26b.
  • FIG. 31 is a diagram showing a cross-sectional configuration of a solid-state imaging device 1 according to the fourth embodiment.
  • FIG. 32 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 when region J in FIG. 31 is enlarged.
  • parts corresponding to those in FIGS. 12 and 13 are denoted by the same reference numerals, and redundant explanation will be omitted.
  • an N-type epitaxial growth layer 53 and a P-type epitaxial growth layer 54 are used in place of the P-type solid phase diffusion layer 38 shown in FIG.
  • This embodiment is different from the third embodiment.
  • the N-type epitaxial growth layer 53 and the P-type epitaxial growth layer 54 are laminated in this order on the side wall surface S4 of the trench portion 25.
  • the N-type epitaxial growth layer 53 is a layer disposed within the trench portion 25 and covering the side wall surface S4 of the trench portion 25.
  • an epitaxial growth layer formed by epitaxial growth while adding N-type impurities can be used.
  • the P-type impurity concentration of the N-type epitaxial growth layer 53 is 1e16/cm 3 or less.
  • the N-type epitaxial growth layer 53 can steepen the potential gradient due to the PN junction between the N-type epitaxial growth layer 53 and the P-type epitaxial growth layer 54. Therefore, the saturation charge amount Qs of the photoelectric conversion section 21 can be improved.
  • the curve showing the N-type impurity concentration overlapping the N-type semiconductor region 23, the N-type epitaxial growth layer 53, and the P-type epitaxial growth layer 54 is shown by a broken line, and the curve showing the P-type impurity concentration is shown by a dashed line. ing.
  • the P-type epitaxial growth layer 54 is a layer that is disposed in the space inside the trench portion 25 covered with the N-type epitaxial growth layer 53 and is in contact with the N-type epitaxial growth layer 53 .
  • the P-type epitaxial growth layer 54 is stacked on the surface of the N-type epitaxial growth layer 53 on the center side in the width direction of the trench portion 25, forming a PN junction with the N-type epitaxial growth layer 53.
  • the P-type epitaxial growth layer 54 for example, an epitaxial growth layer formed by epitaxial growth while adding P-type impurities can be employed. By using such an epitaxial growth layer, as shown in FIG.
  • the N-type impurity concentration of the P-type epitaxial growth layer 54 is 1e16/cm 3 or less.
  • the P-type epitaxial growth layer 54 can have a steeper potential gradient due to the PN junction. Therefore, a decrease in the saturation charge amount Qs of the photoelectric conversion section 21 can be further suppressed.
  • FIG. 12 illustrates a case where the fixed charge film 13 shown in FIG. 8 is omitted.
  • a semiconductor crystal is epitaxially grown on the side wall surface S4 of the trench portion 25 while adding an N-type impurity, and the trench portion is grown so as to cover the side wall surface S4 and the bottom surface of the trench portion 25.
  • An N-type epitaxial growth layer 53 is formed within 25.
  • a semiconductor crystal is epitaxially grown on the surface of the N-type epitaxial growth layer 53 on the center side in the width direction of the trench portion 25 (hereinafter also referred to as "center side surface S13") while adding P-type impurities.
  • a P-type epitaxial growth layer 54 is formed in the trench portion 25 so as to cover the central side surface S13 of the N-type epitaxial growth layer 53.
  • the element isolation portion 26 shown in FIG. 31 is formed.
  • an insulating film 14, a light shielding film 15, a planarizing film 16, a color filter layer 18, and a microlens array 19 are formed. As a result, the solid-state imaging device 1 shown in FIG. 31 is manufactured.
  • an N-type impurity is added to the P-type semiconductor substrate 12. is ion-implanted to form an N-type semiconductor region 23. Subsequently, etching is performed from the surface S2 side of the semiconductor substrate 12 through a mask (not shown) to form the trench portion 25. Subsequently, as shown in FIG. 34A, a semiconductor crystal is epitaxially grown while adding an N-type impurity to the side wall surface S4 of the trench portion 25, etc., so that the entire side wall surface S4 and bottom surface of the trench portion 25, as well as the semiconductor substrate 12 are grown.
  • An N-type epitaxial growth layer 53 is formed in the trench portion 25 and on the surface S2 of the semiconductor substrate 12 so as to continuously cover the surface S2. Subsequently, as shown in FIG. 34B, a semiconductor crystal is epitaxially grown while adding P-type impurities to the center side surface in the width direction of the trench portion 25 (center side surface S13) of the N-type epitaxial growth layer 53, and the N-type epitaxial growth is performed. A P-type epitaxial growth layer 54 is formed in the trench portion 25 or the like so as to continuously cover the entire center side surface S13 of the layer 53. Thereafter, the step shown in FIG. 18C is omitted and the steps shown in FIGS. 18D to 18I are performed to form the element isolation portion 26 shown in FIG.
  • the configuration of the second element isolation part 26b when formed by this manufacturing method is different from the configuration of the second element isolation part 26b when formed by the above manufacturing method (the second element isolation part 26b in FIG. 31).
  • the configuration is slightly different from that of the element isolation section 26b (configuration of the element isolation section 26b).
  • an insulating film 14, a light shielding film 15, a planarizing film 16, a color filter layer 18, and a microlens array 19 are formed.
  • the solid-state imaging device 1 shown in FIG. 31 is manufactured.
  • the present technology can also be applied to photodetection devices in general, including a ranging sensor that measures distance, also called a ToF (Time of Flight) sensor.
  • a ranging sensor that measures distance
  • ToF Time of Flight
  • a distance measurement sensor emits illumination light toward an object, detects the reflected light that is reflected back from the object's surface, and measures the flight from the time the illumination light is emitted until the reflected light is received. This is a sensor that calculates the distance to an object based on time.
  • the structure of the pixel 8 described above can be adopted.
  • FIG. 35 is a diagram illustrating an example of a schematic configuration of an imaging device (video camera, digital still camera, etc.) as an electronic device to which the present technology is applied.
  • the imaging device 1000 includes a lens group 1001, a solid-state imaging device 1002 (solid-state imaging device 1 according to the first embodiment), a DSP (Digital Signal Processor) circuit 1003, and a frame memory 1004. , a monitor 1005, and a memory 1006.
  • DSP circuit 1003, frame memory 1004, monitor 1005, and memory 1006 are interconnected via bus line 1007.
  • a lens group 1001 guides incident light (image light) from a subject to a solid-state imaging device 1002, and forms an image on a light entrance surface (pixel region) of the solid-state imaging device 1002.
  • the solid-state imaging device 1002 is composed of the CMOS image sensor of the first embodiment described above.
  • the solid-state imaging device 1002 converts the amount of incident light imaged on the light entrance surface by the lens group 1001 into an electric signal for each pixel, and supplies the electric signal to the DSP circuit 1003 as a pixel signal.
  • the DSP circuit 1003 performs predetermined image processing on pixel signals supplied from the solid-state imaging device 1002.
  • the DSP circuit 1003 supplies the image signal after image processing to the frame memory 1004 in units of frames, and causes the frame memory 1004 to temporarily store the image signal.
  • the monitor 1005 is composed of a panel display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel.
  • the monitor 1005 displays an image (moving image) of the subject based on pixel signals for each frame temporarily stored in the frame memory 1004.
  • the memory 1006 consists of a DVD, flash memory, etc.
  • the memory 1006 reads out and records pixel signals in frame units temporarily stored in the frame memory 1004.
  • the electronic device to which the solid-state imaging device 1 can be applied is not limited to the imaging device 1000, but can also be applied to other electronic devices.
  • the solid-state imaging device 1 according to the first embodiment is used as the solid-state imaging device 1002
  • other configurations may also be adopted.
  • a configuration using other photodetecting devices to which the present technology is applied such as the solid-state imaging device 1 according to the second to fourth embodiments and the solid-state imaging device 1 according to a modification of the second to fourth embodiments. You can also use it as
  • the present disclosure may have the following configuration.
  • a trench portion formed between the photoelectric conversion parts of the semiconductor substrate, a semiconductor layer disposed within the trench portion and covering a side wall surface of the trench portion, and an interior of the trench portion covered with the semiconductor layer.
  • an element isolation section having a functional layer arranged in a space of The photoelectric conversion section has an N-type semiconductor region in a region in contact with the semiconductor layer,
  • the semiconductor layer has a P-type impurity concentration of 1e16/cm 3 or less
  • the functional layer is a layer that induces holes on the functional layer side of the semiconductor layer.
  • the photodetecting device is a layer that induces holes on the functional layer side of the semiconductor layer.
  • the photodetection device according to (1), wherein the N-type semiconductor region has an N-type impurity concentration peak at an interface between the semiconductor layer and the N-type semiconductor region.
  • the functional layer is a fixed charge film that is disposed along a surface of the semiconductor layer that is far from the side wall surface of the trench portion and has a negative fixed charge.
  • the functional layer is a conductor portion disposed along a surface of the semiconductor layer that is far from the side wall surface of the trench portion, and to which a negative bias voltage is applied. (1) or (2) above. ).
  • the photodetecting device according to (4) wherein the conductor portion covers the side wall surface of the trench portion such that the trench portion has a groove-shaped space inside the trench portion, the side wall being formed by the conductor portion. .
  • the semiconductor layer is a semiconductor layer formed at a different timing from that of the semiconductor substrate.
  • the semiconductor layer is an epitaxially grown layer.
  • the photoelectric conversion section has an N-type semiconductor region in a region in contact with the P-type solid phase diffusion layer,
  • the P-type solid phase diffusion layer has an N-type impurity concentration of 1e16/cm 3 or less.
  • a semiconductor substrate on which a plurality of photoelectric conversion parts are formed A trench portion formed between the photoelectric conversion parts of the semiconductor substrate, an N-type epitaxial growth layer disposed within the trench portion and covering a side wall surface of the trench portion, and the N-type epitaxial growth layer covered with the N-type epitaxial growth layer.
  • an element isolation part having a P-type epitaxial growth layer disposed in a space inside the trench part and in contact with the N-type epitaxial growth layer;
  • the N-type epitaxial growth layer has a P-type impurity concentration of 1e16/cm 3 or less,
  • the P-type epitaxial growth layer has an N-type impurity concentration of 1e16/cm 3 or less.
  • a semiconductor substrate on which a plurality of photoelectric conversion sections are formed a trench section formed between the photoelectric conversion sections of the semiconductor substrate; a semiconductor layer disposed within the trench section and covering a side wall surface of the trench section; and an element isolation section having a functional layer disposed in a space inside the trench section covered with the semiconductor layer, and the photoelectric conversion section has an N-type semiconductor region in a region in contact with the semiconductor layer.
  • the semiconductor layer has a P-type impurity concentration of 1e16/cm 3 or less
  • the functional layer includes a photodetection device that is a layer that induces holes on the functional layer side of the semiconductor layer.
  • the photoelectric conversion section includes an element isolation section having a solid phase diffusion layer, the photoelectric conversion section has an N type semiconductor region in a region in contact with the P type solid phase diffusion layer, and the P type solid phase diffusion layer has an N type semiconductor region.
  • An electronic device comprising: a photodetector having a type impurity concentration of 1e16/cm 3 or less, and the P-type epitaxial growth layer has an N-type impurity concentration of 1e16/cm 3 or less.
  • (13) a step of forming a trench portion in a semiconductor substrate; forming an epitaxial growth layer with an impurity concentration of 1e16/cm 3 or less on the sidewall surface of the trench portion by epitaxial growth;
  • a method for manufacturing a photodetector comprising the step of doping a P-type impurity from within the trench portion into the epitaxial growth layer by solid-phase diffusion.
  • (14) a step of forming a trench portion in a semiconductor substrate; forming an N-type epitaxial growth layer with a P-type impurity concentration of 1e16/cm 3 or less on the side wall surface of the trench portion by epitaxial growth while adding N-type impurities; forming a P-type epitaxial growth layer with an N-type impurity concentration of 1e16/cm 3 or less on a surface of the N-type epitaxial growth layer on the center side in the trench width direction by epitaxial growth while adding P-type impurities; A method for manufacturing a photodetection device.
  • SYMBOLS 1 Solid-state imaging device, 2... Pixel area, 3... Vertical drive circuit, 4... Column signal processing circuit, 5... Horizontal drive circuit, 6... Output circuit, 7... Control circuit, 8... Pixel, 9... Pixel drive wiring, 10... Vertical signal line, 11... Horizontal signal line, 12... Semiconductor substrate, 13... Fixed charge film, 14... Insulating film, 15... Light shielding film, 16... Flattening film, 17... Light receiving layer, 18... Color filter layer, 19... Microlens array, 20... Wiring layer, 21... Photoelectric conversion section, 22... P-type semiconductor region, 23... N-type semiconductor region, 24... P-type semiconductor region, 25... Trench section, 26... Element separation section, 27 ...
  • P type epitaxial growth layer 55... P-type semiconductor region, 1000... imaging device, 1001... lens group, 1002... solid-state imaging device, 1003... DSP circuit, 1004... frame memory, 1005... monitor, 1006... memory, 1007... bus line

Abstract

L'invention concerne un appareil de détection de lumière capable d'améliorer la quantité de charge de saturation Qs d'une unité de conversion photoélectrique. Spécifiquement, l'appareil de détection de lumière est conçue pour comprendre : un substrat semi-conducteur sur lequel une pluralité d'unités de conversion photoélectrique sont formées ; et une partie de séparation d'élément qui a une partie tranchée formée entre des unités de conversion photoélectrique sur le substrat semi-conducteur, une couche semi-conductrice disposée dans la partie tranchée et recouvrant des parois latérales de la partie tranchée, et une couche fonctionnelle disposée dans un espace dans la partie tranchée recouverte par la couche semi-conductrice. Les unités de conversion photoélectrique sont conçues pour avoir une région semi-conductrice de type N dans une région en contact avec la couche semi-conductrice. La couche semi-conductrice a une concentration en impuretés de type P inférieure ou égale à 1e16/cm3. La couche fonctionnelle induit des trous dans le côté couche fonctionnelle de la couche semi-conductrice.
PCT/JP2023/030367 2022-09-06 2023-08-23 Appareil de détection de lumière, dispositif numérique et procédé de production d'appareil de détection de lumière WO2024053401A1 (fr)

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JP2022141709 2022-09-06

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08186257A (ja) * 1995-01-04 1996-07-16 Nec Corp 電界効果型トランジスタおよびその製造方法
JP2006114795A (ja) * 2004-10-18 2006-04-27 Matsushita Electric Ind Co Ltd 半導体装置
JP2012038981A (ja) * 2010-08-09 2012-02-23 Sony Corp 固体撮像装置とその製造方法、並びに電子機器
WO2012117931A1 (fr) * 2011-03-02 2012-09-07 ソニー株式会社 Dispositif d'imagerie à semi-conducteurs et son procédé de fabrication, et instrument électronique
WO2019093151A1 (fr) * 2017-11-09 2019-05-16 ソニーセミコンダクタソリューションズ株式会社 Dispositif de capture d'image à semi-conducteur et appareil électronique

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08186257A (ja) * 1995-01-04 1996-07-16 Nec Corp 電界効果型トランジスタおよびその製造方法
JP2006114795A (ja) * 2004-10-18 2006-04-27 Matsushita Electric Ind Co Ltd 半導体装置
JP2012038981A (ja) * 2010-08-09 2012-02-23 Sony Corp 固体撮像装置とその製造方法、並びに電子機器
WO2012117931A1 (fr) * 2011-03-02 2012-09-07 ソニー株式会社 Dispositif d'imagerie à semi-conducteurs et son procédé de fabrication, et instrument électronique
WO2019093151A1 (fr) * 2017-11-09 2019-05-16 ソニーセミコンダクタソリューションズ株式会社 Dispositif de capture d'image à semi-conducteur et appareil électronique

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