JP2956097B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device.

[Related Art] Conventionally, as a method of dividing a semiconductor wafer into chips, a method of cutting a cutting line formed on a semiconductor wafer using a semiconductor cutting blade thinner than a cutting line width has been adopted. .

FIG. 5 is a view showing a semiconductor wafer before cutting, and FIG. 6 is an enlarged view of FIG. In the figure, 1 is a semiconductor wafer, 2 is an area where an electric circuit pattern is formed, 3
Is a cutting line.

In this method, first, a protective film for protecting an electric circuit pattern is grown on the semiconductor wafer 1, then patterned, and the protective film on the cutting line 3 is removed by etching. Thereafter, the semiconductor wafer 1 is divided into chips by cutting it on the cutting line 3.

As a method for cutting a semiconductor wafer, a dicing method is generally used. The dicing method refers to a method in which an ultra-thin outer peripheral dicing blade is rotated at a high speed by an ultra-precision spindle, and the blade is used to cut a semiconductor wafer along a cutting line. Dicing equipment is manufactured by Disco Corporation.
DAD2H / 6T and A-WD-2500B / TC manufactured by Tokyo Seimitsu Co., Ltd. are used.

When a semiconductor wafer is cut by a dicing method, a part of a cutting line remains on an outer peripheral portion of the cut chip.
This state is shown in FIG. In FIG. 7, 7 is a cutting line remaining, 8 is a chip electrode (Al pad) on the chip, and 9 is chip damage.

Chip damage occurs when a semiconductor wafer is cut, and a portion where an upper surface of the semiconductor wafer intersects with a cut surface is damaged. The chip damage is not limited to the dicing method, but necessarily occurs when the semiconductor wafer is mechanically cut.

In the conventional wafer, the protective film on the cutting line is removed by etching. There are two reasons for this.

One is to etch the protective film on the cutting line in order to monitor the etching amount in the process of exposing the chip electrode by etching the protective film, and use this etching amount as a substitute for monitoring the etching amount of the protective film on the chip electrode. Another reason is to perform the inspection process smoothly rather than the wafer manufacturing process. The inspection step is performed by a method of inspecting the electrical characteristics of all the chips in the wafer by bringing a measuring instrument and a thin metal wire connected on a power supply into contact with the chip electrodes. This thin metal wire has a diameter of about 30 μm and requires careful alignment when contacting the chip electrode. In order to perform this alignment, a He-Ne laser is applied to the wafer, and the reflected light is used to detect the position of the cutting line from which the protective film has been removed by etching, which is used for alignment of the chip electrode and the fine metal wire.

In order to perform the above two points, conventionally, the protective film on the cutting line is removed by etching.

[Problems to be Solved by the Invention] However, recently, in order to manufacture a large number of chips from one semiconductor wafer, the width of the cutting line has been extremely narrowed, and furthermore, the electric circuit pattern has been formed to the vicinity of the cutting line. Since they are close to each other, a problem has arisen that a part of the electric circuit pattern is damaged by chip damage.

In other words, if the width of the cutting line is wide, the remaining cutting line after cutting is wide, so chip damage occurs almost only on the remaining cutting line. If the pattern does not exist, it does not affect the electric operation of the electric circuit pattern. However, if the width of the cutting line is narrow as in the current semiconductor wafer, the remaining cutting line after cutting is extremely narrow, and chip damage easily penetrates into the chip. Furthermore, since the current highly integrated electric circuit pattern is close to the vicinity of the cutting line, penetration of chip damage directly damages the electric circuit pattern and affects the operation of the electric circuit. The circuit stops working at all. Specifically,
For example, conventionally, the width of a cutting line is generally 100 μm, and the width of a dicing blade for cutting a semiconductor wafer is 30 μm.
μm. When a semiconductor wafer is cut under these conditions,
At least the remaining cutting line on the outer periphery of the chip is 30 μm or more. In an experiment by the inventor, the cutting speed was set to 30 when the diamond powder of the dicing blade was 2 to 6 μm.
Assuming mm / sec, the size of the chip damage was 20 μm.
In contrast, if the cutting line width is 50 μm, the dicing blade width is 30 μm, and the remaining cutting line is 10 μm.
And the chip damage penetrates the electric circuit pattern beyond the rest of the cutting line. FIG. 3 schematically shows this state, and is a cross section taken along line CC 'of FIG.
FIG. 4 is an enlarged view of the portion B in FIG.
3 and 4, reference numeral 4 denotes a protective film, 5 denotes an electric circuit pattern, and 6 denotes a damaged electric circuit pattern.

In general, in order to prevent this, methods such as reducing the cutting speed and reducing the width of the dicing blade have been adopted. However, in this case, the manufacturing time of the semiconductor device becomes extremely slow, which leads to a problem that the cost increases in mass production. In addition, in the case of (1), the blade must be frequently replaced during manufacturing due to the occurrence of blade cracks and intensified wear of the blade due to the inferior mechanical strength of the blade, which is not suitable for mass production.

There is also an opinion that chip damage that occurs when cutting the cutting line can be suppressed by the edge of the protective film near the cutting line, but this is a stochastic problem, and if the cutting speed is fast, it is impossible to do so. is there.

Means for Solving the Problems The gist of the present invention includes a step of dividing a semiconductor wafer, in which a plurality of electric circuit patterns each having a chip electrode are arranged adjacent to each other with a gap therebetween, into chips at the gap. In the method for manufacturing a semiconductor device, the step may be such that the upper surface of the element isolation region is higher inside the plurality of electric circuit patterns and lower as the upper surface is outside the plurality of electric circuit patterns. Formed by bending, and then forming a protective film covering the plurality of electric circuit patterns on the element isolation region and the gap, and further leaving the protective film provided on the gap. After removing the protective film on the chip electrode, the semiconductor wafer positioned under the protective film together with the protective film in the gap covered with the protective film is moved forward. There is a method of manufacturing a semiconductor device, characterized in that a semiconductor device is divided into chips by using a dicing blade having a width equal to or slightly smaller than the width of the gap.

According to the present invention, since the semiconductor wafer is cut from above the protective film, chip damage at the time of cutting can be reduced, and the semiconductor wafer can be cut without affecting the circuit pattern. .

Further, by forming an element isolation region (LOCOS) between an electric circuit pattern and a dicing line in advance and forming the protective film thereafter, a curve which becomes lower as approaching the cutting line and becomes higher as approaching the electric circuit pattern is obtained. The protective film having a uniform shape can be easily formed. By providing the protective film having such a shape, the force acting in the horizontal direction when the dicing blade contacts the protective film can be reduced, and the substrate having the protective film can be diced by the force acting in the vertical direction. As a result, even if dicing is performed with the protective film on the cutting line, the amount of chip damage can be reduced, and the manufacturing cost can be improved.

Reference Examples and Examples Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be specifically described with reference to the drawings.

(Reference Example) Table 1 shows a comparison of the amount of chip damage between a case where the protective film is cut from above and a case where the protective film is removed and cut. The protective film used in the present embodiment is a silicon nitride film of 8000 °. The dicing machine uses DAD-2SP / 6T manufactured by Disco Co., Ltd., and the blade uses 27HCCF (diamond particles 2-4 μm, width = 40-50 μm) manufactured by the company.
Blade rotation at cutting is 30,000rpm, cutting speed is 5
3030 mm / sec. The chip damage amount was measured from the cut edge. As a result, it can be seen that the amount of chip damage is reduced when cutting from the protective film.

FIG. 1 shows a cut surface when a semiconductor wafer having a protective film on a cutting line is cut at a cutting speed of 30 mm / sec. FIG. 2 is an enlarged view of a portion A in FIG. As can be seen from FIGS. 1 and 2, the amount of chip damage 10 due to the cutting is small and does not affect the electric circuit pattern.

The protective film is grown on the entire surface of the wafer, and thereafter, only the protective film on the chip electrode (Al pad) on each chip is etched to expose the chip electrode.

In this embodiment, the case where the silicon nitride film is used as the protective film has been described.
For example, it is clear that a similar effect can be obtained with a PSG film, an NSG film, a BPSG film, or the like.

(Embodiment) FIGS. 8 and 9 show an embodiment of the present invention. FIG. 9 shows that, up to the dicing position (corresponding to the edge of the dicing blade), the element 11 (LOCOS) having no electric circuit pattern and the area 11 of only the interlayer insulating film in the electric circuit pattern area 5 are installed and then protected. A film is formed, and only the protective film on the chip electrode is removed. Here, 12 is a dicing line. Here, the protective film has a step 13 due to the presence of the region 11 at the edge of the dicing line. The step 14 between the upper surface of the region 11 and the upper surface of the dicing line 12 depends on the semiconductor manufacturing process, including the element isolation (LOCOS) and the thickness of the interlayer insulating film. Value. In this embodiment, the step
The cut is made using a dicing blade equal to or slightly thinner than width 13 of 13. FIG. 8 shows the result in this case, and the amount of cracks is smaller than in the first embodiment because of the steps 13 and 14.

[Effects of the Invention] As described above, according to the present invention, a semiconductor wafer having an electric circuit pattern near the cutting line and having a narrow cutting line width damages the electric circuit pattern on the chip. It is possible to cut without performing.

[Brief description of the drawings]

FIG. 1 is a view for explaining chip damage when cutting is performed on a cutting line where a protective film is present, and FIG.
FIG. 3 is an enlarged view of a portion A of FIG. 3, FIG. 3 is a diagram for explaining chip damage when cutting is performed on a cutting line without a protective film, FIG. 4 is an enlarged view of a portion B of FIG. FIG. 5 is a view of a wafer divided for each circuit pattern by a cutting line, FIG. 6 is an enlarged view of FIG. 5, FIG. 7 is a view of a chip after cutting, FIG. 8 and FIG. It is a figure which shows the Example of. DESCRIPTION OF SYMBOLS 1 ... Semiconductor wafer, 2 ... Area where electric circuit pattern exists, 3 ... Cutting line, 4 ... Protective film, 5 ... Electric circuit pattern, 6 ... Damaged electric circuit pattern, 7
... cutting line remaining, 8 ... chip electrode (Al pad),
9: Chip damage, 10: Chip damage amount, 12: Dicing line, 13: Step.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kenichi Nakamura 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (56) References JP-A-58-197743 (JP, A) JP-A-56 -33852 (JP, A) JP-A-57-80719 (JP, A) JP-A-63-12149 (JP, A)

Claims (4)

(57) [Claims] 1. A method of manufacturing a semiconductor device, comprising: dividing a semiconductor wafer in which a plurality of electric circuit patterns having chip electrodes are arranged adjacent to each other with a gap therebetween into chips at the gap. Forming an element isolation region by curving such that the upper surface of the element isolation region is high inside the plurality of electric circuit patterns and becomes low as it goes outside the plurality of electric circuit patterns; Forming a protective film covering the plurality of electric circuit patterns on the isolation region and the gap; and removing the protective film on the chip electrode so as to leave the protective film provided on the gap. After that, in the gap covered with the protective film, the semiconductor wafer positioned under the protective film together with the protective film is equal to the width of the gap or The method of manufacturing a semiconductor device characterized by dividing into chips by using the thin dicing blade or without. 2. The method according to claim 1, wherein said protective film is made of silicon nitride. 3. The step of removing the protective film on the chip electrode so as to leave the protective film provided on the gap, the step of removing only the protective film on the chip electrode. 2. The method for manufacturing a semiconductor device according to claim 1, wherein: 4. The method according to claim 3, wherein the step of removing only the protective film is performed by etching.