JP2948412B2 - Method for manufacturing side-emitting semiconductor light emitting device - Google Patents

Method for manufacturing side-emitting semiconductor light emitting device

Info

Publication number
JP2948412B2
JP2948412B2 JP4116305A JP11630592A JP2948412B2 JP 2948412 B2 JP2948412 B2 JP 2948412B2 JP 4116305 A JP4116305 A JP 4116305A JP 11630592 A JP11630592 A JP 11630592A JP 2948412 B2 JP2948412 B2 JP 2948412B2
Authority
JP
Japan
Prior art keywords
semiconductor light
light emitting
material plate
substrate
synthetic resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP4116305A
Other languages
Japanese (ja)
Other versions
JPH05315651A (en
Inventor
裕宣 西田
勉 澤邊
宏基 石長
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP4116305A priority Critical patent/JP2948412B2/en
Publication of JPH05315651A publication Critical patent/JPH05315651A/en
Application granted granted Critical
Publication of JP2948412B2 publication Critical patent/JP2948412B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、側面を発光するように
した発光ダイオード又は半導体レーザ等の半導体発光素
子を製造する方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor light emitting device such as a light emitting diode or a semiconductor laser having a side surface emitting light.

【0002】[0002]

【従来の技術】一般に、この種の側面発光型の半導体発
光素子1は、例えば、実開昭63−188967号公報
又は実開昭64−8759号公報等に記載され、且つ、
図1〜図4に示すように、基板2の上面に、少なくとも
一対のリード電極パターン3,4を形成し、その一方の
リード電極パターン3の上面に、半導体発光チップ5を
マウントしたのち、この半導体発光チップ5と他方のリ
ード電極パターン4との間を、金属線6にてワイヤーボ
ンディングし、次いで、前記基板2の上面に、少なくと
も一つの側面に開口部7aを備えて成る非透明体製のカ
バー体7を、前記半導体発光チップ5及び金属線6を覆
うように装着し、このカバー体7の内部に、透明な合成
樹脂8を充填して、半導体発光チップ5及び金属線6の
部分を密封し、この透明合成樹脂8のうち前記カバー体
7の開口部7a箇所における露出面8aから光を発射す
ると言う構成している。なお、符号9は、一方のリード
電極パターン3に対する接続用端子を、符号10は、他
方のリード電極パターン4に対する接続用端子を各々示
す。
2. Description of the Related Art In general, this type of side-emitting type semiconductor light emitting device 1 is described in, for example, Japanese Utility Model Application Laid-Open No. 63-188967 or Japanese Utility Model Application Laid-Open No. 64-8759, and
As shown in FIGS. 1 to 4, at least a pair of lead electrode patterns 3 and 4 are formed on the upper surface of the substrate 2, and the semiconductor light emitting chip 5 is mounted on the upper surface of one of the lead electrode patterns 3. A wire is bonded between the semiconductor light emitting chip 5 and the other lead electrode pattern 4 with a metal wire 6, and then a non-transparent body having an opening 7 a on at least one side surface on the upper surface of the substrate 2. Is mounted so as to cover the semiconductor light emitting chip 5 and the metal wire 6, and the inside of the cover 7 is filled with a transparent synthetic resin 8, so that the portion of the semiconductor light emitting chip 5 and the metal wire 6 is formed. Is sealed, and light is emitted from the exposed surface 8a of the transparent synthetic resin 8 at the opening 7a of the cover body 7. Reference numeral 9 denotes a connection terminal for one lead electrode pattern 3, and reference numeral 10 denotes a connection terminal for the other lead electrode pattern 4.

【0003】[0003]

【発明が解決しようとする課題】ところで、従来、前記
した側面発光型の半導体発光素子1を製造するに際して
は、基板2及びカバー体7を製造すること、基板2の上
面にカバー体7を固着すること、このカバー体7の内部
に透明合成樹脂8を充填することの各工程を、半導体発
光素子1の一個ずつについて行うと共に、前記透明合成
樹脂8における露出面8aを平面状に仕上げることの工
程をも、半導体発光素子1の一個ずつについて行うよう
にしているから、生産性がきわめて低くて、製造コスト
が大幅にアップすると言う問題があった。
Conventionally, when manufacturing the above-mentioned side emission type semiconductor light emitting device 1, the substrate 2 and the cover 7 are manufactured, and the cover 7 is fixed to the upper surface of the substrate 2. The steps of filling the inside of the cover 7 with the transparent synthetic resin 8 are performed for each of the semiconductor light emitting elements 1, and the exposed surface 8 a of the transparent synthetic resin 8 is finished in a planar shape. Since the process is performed for each semiconductor light emitting element 1 one by one, there is a problem that productivity is extremely low and manufacturing cost is significantly increased.

【0004】本発明は、前記した各工程を複数個の半導
体発光素子について同時に行うようにすることによっ
て、生産性の向上を図ることを技術的課題とするもので
ある。
[0004] It is a technical object of the present invention to improve the productivity by simultaneously performing the above-described steps for a plurality of semiconductor light emitting devices.

【0005】[0005]

【課題を解決するための手段】この技術的課題を達成す
るため本発明は、「一つの半導体発光素子を構成する基
板の複数個を一体的に連接して成る基板用素材板には、
前記各基板の箇所の各々にリード電極パターンを形成す
ると共に半導体発光チップをマウントする一方、一つの
半導体発光素子を構成するカバー体の複数個を一体的に
連接したカバー体用素材板には、前記各カバー体の箇所
の各々に凹所を形成し、この各凹所内に液状の合成樹脂
を充填し、次いで、前記基板用素材板及び前記カバー体
用素材板を、これらを互いに重ね合わせ接合して前記
状の合成樹脂を硬化したのち、一つの半導体発光素子ご
とに、前記硬化した合成樹脂の一部がカバー体外に露出
するように切断する。」という方法を採用した。
In order to achieve this technical object, the present invention provides a method of manufacturing a semiconductor light-emitting device comprising:
While forming a lead electrode pattern on each of the portions of each substrate and mounting the semiconductor light emitting chip, a cover body material plate integrally connected to a plurality of cover bodies constituting one semiconductor light emitting element, A recess is formed at each of the portions of the cover body, a liquid synthetic resin is filled in each recess, and then the base material plate and the cover body material are overlapped and joined together. And the liquid
After curing the synthetic resin in a shape, the semiconductor resin is cut for each semiconductor light emitting element so that a part of the cured synthetic resin is exposed outside the cover body. Method was adopted.

【0006】[0006]

【作 用】このようにすると、一つの半導体発光素子
を構成する基板、及び同じく一つの半導体発光素子を構
成するカバー体を製造すること、前記基板の上面にカバ
ー体を固着すること、このカバー体の内部に液体の合成
樹脂を充填することの各工程を、複数個の基板を一体的
に連接した基板用素材板と、複数個のカバー体を一体的
に連接したカバー体用素材板によって、半導体発光素子
の複数個ずつについて行うことができると共に、前記硬
化した合成樹脂における露出面を平面状に仕上げること
の工程を、基板用素材板及びカバー体用素材板を一つの
半導体発光素子ごと切断することで同時に行うことがで
きる。
In this manner, a substrate constituting one semiconductor light emitting element and a cover body also constituting one semiconductor light emitting element are manufactured, and the cover body is fixed to the upper surface of the substrate. Each step of filling the inside of the body with liquid synthetic resin is performed by a substrate material plate that integrally connects a plurality of substrates and a cover material plate that integrally connects a plurality of cover bodies. , it is possible to perform the one by a plurality of semiconductor light-emitting device, the hard
The step of finishing the exposed surface of the converted synthetic resin into a planar shape can be performed simultaneously by cutting the material plate for the substrate and the material plate for the cover together with one semiconductor light emitting element.

【0007】[0007]

【発明の効果】従って、本発明によると、側面発光型の
半導体発光素子を製造する場合において、その生産性を
大幅にアップすることができ、製造コストの低減を達成
できる効果を有する。
Therefore, according to the present invention, in the case of manufacturing a side emission type semiconductor light emitting device, the productivity can be greatly increased, and the manufacturing cost can be reduced.

【0008】[0008]

【実施例】以下、本発明の実施例を、前記図1〜図4に
示す構造の側面発光型半導体発光素子1を製造する場合
に適用した図面(図5〜図15)について説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described with reference to the drawings (FIGS. 5 to 15) in which the embodiment of the present invention is applied to the manufacture of the side emission type semiconductor light emitting device 1 having the structure shown in FIGS.

【0009】図5及び図6において符号Aは、複数枚の
基板2を縦方向及び横方向に並べて一体的に連接して成
る絶縁体製の基板用素材板を示す。但し、この場合にお
いて、上から第1列目における各基板2と第2列目にお
ける各基板2とは互いに相対向し、第2列目の各基板2
と第3列目の各基板2とは背中合わせになるようにして
配列されている。
In FIG. 5 and FIG. 6, reference numeral A denotes a substrate material plate made of an insulator formed by connecting a plurality of substrates 2 in a vertical direction and a horizontal direction and integrally connecting them. However, in this case, each substrate 2 in the first column and each substrate 2 in the second column are opposed to each other from the top, and each substrate 2 in the second column is
And the substrates 2 in the third row are arranged back to back.

【0010】また、前記基板用素材板Aには、縦横に並
べた各基板2のコーナーの部分に、貫通孔A1 が穿設さ
れている。更にまた、符号A2 は、各基板2を縦方向に
区分する縦切断線を、符号A3 は、各基板2を横方向に
区分する横切断線を示す。
Further, in the above substrate material for plate A, the corner portion of each substrate 2 arranged vertically and horizontally, the through hole A 1 is drilled. Further, reference numeral A 2 indicates a vertical cutting line that divides each substrate 2 in the vertical direction, and reference numeral A 3 indicates a horizontal cutting line that divides each substrate 2 in the horizontal direction.

【0011】そして、この基板用素材板Aの表面には、
各基板2の箇所の各々に、図7及び図8に示すように、
リード電極パターン3,4を形成すると共に、その各貫
通孔A1 の内面に、接続用端子9,10を構成するため
にスルーホール状の電極膜11を形成する。
Then, on the surface of the substrate material plate A,
As shown in FIG. 7 and FIG. 8,
To form a lead electrode patterns 3 and 4, the inner surface of the through-holes A 1, to form a through-hole-shaped electrode film 11 for forming the connection terminals 9 and 10.

【0012】次いで、図9及び図10に示すように、前
記各一方のリード電極パターン3の各々に対して半導体
発光チップ5をマウントしたのち、この各半導体発光チ
ップ5と他方のリード電極パターン4との各々間を、金
属線6にてワイヤーボンディングする。
Next, as shown in FIGS. 9 and 10, a semiconductor light emitting chip 5 is mounted on each of the one lead electrode patterns 3, and then each semiconductor light emitting chip 5 and the other lead electrode pattern 4 are mounted. Is wire-bonded with a metal wire 6.

【0013】一方、図11〜図13において符号Bは、
複数個のカバー体7を縦方向及び横方向に並べて一体的
に連接して成る非透明合成樹脂製のカバー体用素材板を
示し、このカバー体用素材板Bには、各カバー体7の箇
所の各々に、凹所B1 が形成されている。但し、この場
合において、上から第1列目における各カバー体7の凹
所B1 と第2列目における各カバー体7の凹所B1 とは
連続している。また、符号B2 は、各カバー体7を縦方
向に区分する縦切断線を、符号B3 は、各カバー体7を
横方向に区分する横切断線を示す。
On the other hand, in FIGS.
A cover body material plate made of a non-transparent synthetic resin is shown in which a plurality of cover bodies 7 are arranged in the longitudinal direction and the horizontal direction and integrally connected to each other. each location, the recess B 1 is formed. However, in this case, it is continuous from the recess B 1 of each cover member 7 recess B 1 of each cover member 7 in the first row from the top and in the second column. Reference numeral B 2 indicates a vertical cutting line that divides each cover body 7 in the vertical direction, and reference numeral B 3 indicates a horizontal cutting line that divides each cover body 7 in the horizontal direction.

【0014】そして、前記カバー体用素材板Bを、その
各凹所B1 を上向きにした状態で、各凹所B1 内の各々
に、図14に示すように、エポキシ樹脂等の透明合成樹
脂8を液体の状態で充填する一方、前記基板用素材板A
を、下向きの状態にして、前記カバー体用素材板Bに対
して重ね合わせることにより、前記基板用素材板Aと前
記カバー体用素材板Bとを、図15及び図16に示すよ
うに、一体的に接合すると共に、前記液状の状態で充填
した透明合成樹脂8を硬化させる。
[0014] Then, the cover member for the blank B, in a state in which the respective recess B 1 upwards, in each of the recesses B 1, as shown in FIG. 14, a transparent synthetic such as epoxy resin While the resin 8 is filled in a liquid state, the substrate material plate A
In a downward state, and superimposed on the cover body material plate B, the substrate material plate A and the cover body material plate B, as shown in FIGS. Integrally joined and filled in the liquid state
The transparent synthetic resin 8 thus cured is cured.

【0015】この場合において、基板用素材板Aとカバ
ー体用素材板Bとの一体的な接合は、その両者を接着剤
にて貼り合わせるようにしても良いが、前記カバー体用
素材板Bにおける各凹所B1 内に充填したエポキシ樹脂
等の透明合成樹脂8を、液体のままで接着剤として貼り
合わせるようにしても良いのである。
In this case, the substrate material plate A and the cover material plate B may be integrally joined together by bonding them together with an adhesive. a transparent synthetic resin 8 such as epoxy resin filled in the recess B 1 in, it's may be bonded as an adhesive remains liquid.

【0016】次いで、前記のように一体的に接合した基
板用素材板Aと前記カバー体用素材板Bとを、その各々
における縦切断線A2 ,B2 及び横切断線A3 ,B3
沿って薄い刃カッターC等にて、一つの半導体発光素子
1ごとに切断するのであり、この切断により、硬化した
透明合成樹脂8における一部がカバー体7外に露出し、
露出面8aになるから、前記図1〜図4に示すような半
導体発光素子1の複数個を同時に製造することができる
のである。
Next, the substrate material plate A and the cover body material plate B integrally joined as described above are separated from each other by vertical cutting lines A 2 , B 2 and horizontal cutting lines A 3 , B 3. The semiconductor light-emitting element 1 is cut for each semiconductor light-emitting element 1 by a thin blade cutter C or the like. By this cutting, a part of the cured transparent synthetic resin 8 is exposed outside the cover body 7.
Since it becomes the exposed surface 8a, a plurality of the semiconductor light emitting devices 1 as shown in FIGS. 1 to 4 can be manufactured at the same time.

【0017】なお、前記カバー体用素材板Bの表裏両面
のうち凹所B1 を設けない裏面には、当該カバー体用素
材板Bにおける各縦切断線B2 及び各横切断線B3 の箇
所に、切断用溝B2 ′,B3 ′を、前記縦切断線B2
び横切断線B3 に沿って延びるように予め形成するよう
にしても良いのである。また、前記各凹所B1 の内面
に、半導体発光チップ5からの光を、硬化した透明合成
樹脂8における一側面8aに向かうようにした光の反射
膜を形成するようにしても良いのである。
[0017] Note that the rear surface is not provided a recess B 1 of the front and back surfaces of the blank B for the cover member, each vertical cutting lines B 2 and the transversal cuts B 3 in the blank B for the cover body The cutting grooves B 2 ′ and B 3 ′ may be formed in advance at the locations so as to extend along the vertical cutting line B 2 and the horizontal cutting line B 3 . Moreover, the the inner surface of the recess B 1, the light from the semiconductor light emitting chip 5 is the may be formed a reflective film of the light to be directed to one side 8a of the cured transparent synthetic resin 8 .

【0018】更にまた、前記実施例は、基板用素材板A
における第1列目の各基板2と第2列目の各基板2を相
対向するように配設することによって、カバー体用素材
板Bの第1列目における各カバー体7の凹所B1 と第2
列目におけるカバー体7の凹所B1 とを連通するように
構成した場合を示したが、本発明はこれに限らず、基板
用素材板Aにおける各基板2を同じ向きに配設する一
方、カバー体用素材板Bの各カバー体7における凹所B
1 を、各カバー体7の各々について独立した形態にし、
切断に際して、各凹所B1 内に液状で充填して硬化した
透明合成樹脂8の一部がカバー体7の外に露出するよう
に切断すると言う構成にしても良いのである。
Further, the above-described embodiment is characterized in that the substrate material plate A
The substrate B of the first row and the substrate 2 of the second row are disposed so as to face each other, so that the recess B of each cover body 7 in the first row of the cover body material plate B is provided. 1 and 2
Shows the case that is configured to communicate the recess B 1 of the cover member 7 in the th column, while the present invention is not limited thereto, disposing the respective substrate 2 in the material plate A substrate in the same direction Recess B in each cover body 7 of the cover body material plate B
1 in an independent form for each of the cover bodies 7,
Upon cleavage, is the part of <br/> transparent synthetic resin 8 which is cured is filled with liquid each recess B 1 may be configured to refer to cut so as to be exposed to the outside of the cover member 7.

【0019】加えて、前記実施例は、側面発光型の発光
ダイオードを製造する場合であったが、本発明は、側面
発光型の半導体レーザ等のようなその他の発光素子の製
造にも適用できることは言うまでもない。
In addition, although the above embodiment is directed to the manufacture of a side-emitting type light emitting diode, the present invention can be applied to the manufacture of other light emitting devices such as a side emission type semiconductor laser. Needless to say.

【図面の簡単な説明】[Brief description of the drawings]

【図1】側面発光型半導体発光素子の縦断正面図であ
る。
FIG. 1 is a vertical sectional front view of a side emission type semiconductor light emitting device.

【図2】図1のII−II視断面図である。FIG. 2 is a sectional view taken along line II-II of FIG.

【図3】図1の平面図である。FIG. 3 is a plan view of FIG. 1;

【図4】図1のIV−IV視平面図である。FIG. 4 is a plan view as viewed from IV-IV in FIG. 1;

【図5】基板用素材板の平面図である。FIG. 5 is a plan view of a substrate material plate.

【図6】図5のVI−VI視断面図である。6 is a sectional view taken along line VI-VI of FIG.

【図7】基板用素材板の表面にリード電極パターンを形
成したときの平面図である。
FIG. 7 is a plan view when a lead electrode pattern is formed on the surface of a substrate material plate.

【図8】図7のVIII−VIII視断面図である。8 is a sectional view taken along line VIII-VIII of FIG.

【図9】基板用素材板の表面に半導体発光チップをマウ
ントしたのちワイヤーボンディングしたときの平面図で
ある。
FIG. 9 is a plan view when a semiconductor light emitting chip is mounted on the surface of a substrate material plate and then wire-bonded.

【図10】図9のX−X視断面図である。FIG. 10 is a sectional view taken along line XX of FIG. 9;

【図11】カバー体用素材板の平面図である。FIG. 11 is a plan view of a cover body material plate.

【図12】図11のXII −XII 視断面図である。12 is a sectional view taken along the line XII-XII in FIG.

【図13】図11のXIII−XIII視断面図である。13 is a sectional view taken along the line XIII-XIII of FIG.

【図14】カバー用素材板における各凹所内に透明合成
樹脂を充填したときの断面図である。
FIG. 14 is a cross-sectional view when a transparent synthetic resin is filled in each recess in the cover material plate.

【図15】基板用素材板とカバー用素材板とを接合した
ときにおける前記図13と同じ箇所の断面図である。
FIG. 15 is a cross-sectional view of the same place as in FIG. 13 when the substrate material plate and the cover material plate are joined.

【図16】基板用素材板とカバー用素材板とを接合した
ときにおける前記図12と同じ箇所の断面図である。
FIG. 16 is a cross-sectional view of the same place as in FIG. 12 when the substrate material plate and the cover material plate are joined.

【符号の説明】[Explanation of symbols]

1 側面発光型半導体発光素子 2 基板 3,4 リード電極パターン 5 半導体発光チップ 6 金属線 7 カバー体 8 透明合成樹脂 8a 透明合成樹脂の一側面 A 基板用素材板 A1 貫通孔 B カバー体用素材板 B1 凹所 A2 ,B2 縦切断線 A3 ,B3 横切断線DESCRIPTION OF SYMBOLS 1 Side emission type semiconductor light emitting element 2 Substrate 3, 4 Lead electrode pattern 5 Semiconductor light emitting chip 6 Metal wire 7 Cover body 8 Transparent synthetic resin 8a One side of transparent synthetic resin A Board material plate A 1 Through hole B Cover material Plate B 1 recess A 2 , B 2 vertical cutting line A 3 , B 3 horizontal cutting line

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 33/00 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 33/00

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】一つの半導体発光素子を構成する基板の複
数個を一体的に連接して成る基板用素材板には、前記各
基板の箇所の各々にリード電極パターンを形成すると共
に半導体発光チップをマウントする一方、一つの半導体
発光素子を構成するカバー体の複数個を一体的に連接し
たカバー体用素材板には、前記各カバー体の箇所の各々
に凹所を形成し、この各凹所内に液状の合成樹脂を充填
し、次いで、前記基板用素材板及び前記カバー体用素材
板を、これらを互いに重ね合わせ接合して前記液状の
成樹脂を硬化したのち、一つの半導体発光素子ごとに、
前記硬化した合成樹脂の一部がカバー体外に露出するよ
うに切断することを特徴とする側面発光型の半導体発光
素子を製造する方法。
1. A substrate material plate comprising a plurality of substrates integrally forming a semiconductor light emitting element, wherein a lead electrode pattern is formed at each of the portions of each substrate, and a semiconductor light emitting chip is formed. On the other hand, on a cover body material plate in which a plurality of cover bodies constituting one semiconductor light emitting element are integrally connected, a recess is formed at each of the cover bodies. After filling the place with a liquid synthetic resin, the substrate material plate and the cover body material plate are overlapped and joined together to cure the liquid synthetic resin. For each semiconductor light emitting element,
A method of manufacturing a side emission type semiconductor light emitting device, comprising cutting the synthetic resin so that a part of the cured synthetic resin is exposed outside the cover body.
JP4116305A 1992-05-08 1992-05-08 Method for manufacturing side-emitting semiconductor light emitting device Expired - Fee Related JP2948412B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4116305A JP2948412B2 (en) 1992-05-08 1992-05-08 Method for manufacturing side-emitting semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4116305A JP2948412B2 (en) 1992-05-08 1992-05-08 Method for manufacturing side-emitting semiconductor light emitting device

Publications (2)

Publication Number Publication Date
JPH05315651A JPH05315651A (en) 1993-11-26
JP2948412B2 true JP2948412B2 (en) 1999-09-13

Family

ID=14683727

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2948412B2 (en)

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