JP2924113B2 - Electronic component bonding method - Google Patents

Electronic component bonding method

Info

Publication number
JP2924113B2
JP2924113B2 JP2191375A JP19137590A JP2924113B2 JP 2924113 B2 JP2924113 B2 JP 2924113B2 JP 2191375 A JP2191375 A JP 2191375A JP 19137590 A JP19137590 A JP 19137590A JP 2924113 B2 JP2924113 B2 JP 2924113B2
Authority
JP
Japan
Prior art keywords
solder electrode
electronic component
electrode portion
lead
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2191375A
Other languages
Japanese (ja)
Other versions
JPH0476987A (en
Inventor
朝宏 湧川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2191375A priority Critical patent/JP2924113B2/en
Publication of JPH0476987A publication Critical patent/JPH0476987A/en
Application granted granted Critical
Publication of JP2924113B2 publication Critical patent/JP2924113B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は電子部品のボンディング方法に関し、基板に
形成された半田電極部の間に仕切壁部を形成することに
より、電子部品のリードを着地させる際に、リードが半
田電極部から滑り落ちないようにしたものである。
Description: FIELD OF THE INVENTION The present invention relates to a method for bonding electronic components, and relates to a method for bonding leads of an electronic component by forming a partition wall between solder electrode portions formed on a substrate. In this case, the lead is prevented from slipping off from the solder electrode portion.

(従来の技術) リードを有する電子部品を基板にボンディングする手
段として、基板の上面にメッキ手段や半田レベラーによ
り固形の半田電極部を形成し、この半田電極部にリード
を着地させたうえで,半田電極部を加熱処理することに
より、リードを半田電極部に接着することが知られてい
る。
(Prior Art) As means for bonding an electronic component having leads to a substrate, a solid solder electrode portion is formed on the upper surface of the substrate by plating means or a solder leveler, and the lead is landed on the solder electrode portion. It is known that a lead is adhered to a solder electrode portion by heating the solder electrode portion.

(発明が解決しようとする課題) ところが、第4図に示すように、基板100に形成され
た半田電極部101の上面は山形状の球面になりやすく、
このため、リード102を着地させる際に、リード102が滑
り落ちて、半田電極部101に正しく搭載しにくい問題が
あった。
(Problems to be Solved by the Invention) However, as shown in FIG. 4, the upper surface of the solder electrode portion 101 formed on the substrate 100 tends to be a mountain-shaped spherical surface.
Therefore, when the lead 102 lands, there is a problem that the lead 102 slides down and it is difficult to correctly mount the lead 102 on the solder electrode portion 101.

そこで本発明は、このような従来手段の問題点を解消
できる電子部品のボンディング方法を提供することを目
的とする。
Therefore, an object of the present invention is to provide a bonding method of an electronic component which can solve such a problem of the conventional means.

(課題を解決するための手段) 本発明は、基板にピッチをおいて形成された固形の半
田電極部の間に、この半田電極部よりも背高で両肩部が
円曲なテーパ面の仕切壁部を形成し、この半田電極部に
電子部品のリード部を着地させてボンディングするよう
にしたものである。
(Means for Solving the Problems) According to the present invention, between a solid solder electrode portion formed at a pitch on a substrate, a tapered surface which is taller than the solder electrode portion and both shoulder portions are curved. A partition wall portion is formed, and a lead portion of an electronic component is landed on the solder electrode portion for bonding.

(作用) 上記構成によれば、仕切壁部により、リードが半田電
極部から滑り落ちるのは防止され、リードを半田電極部
に正しく搭載してボンディングすることができる。
(Operation) According to the above configuration, the partition wall prevents the lead from slipping off the solder electrode, and the lead can be correctly mounted on the solder electrode and bonded.

(実施例) 次に、図面を参照しながら本発明の実施例を説明す
る。
Example Next, an example of the present invention will be described with reference to the drawings.

第1図において、1は基板であり、固形の半田電極部
2がピッチをおいて形成されている。この半田電極部2
は、基板1に形成された銅箔パターン3上に、メッキ手
段や半田レベラーにより形成されたものであり、その上
面は緩やかな球面になっている。
In FIG. 1, reference numeral 1 denotes a substrate, on which solid solder electrode portions 2 are formed at a pitch. This solder electrode part 2
Is formed on a copper foil pattern 3 formed on a substrate 1 by a plating means or a solder leveler, and its upper surface has a gentle spherical surface.

半田電極部2の間には、電気絶縁性の仕切壁部4が形
成されている。この仕切壁部4は、スクリーン印刷手段
などにより形成される。第2図に示すように、この仕切
壁部4は半田電極部2よりも背高であり、またその両肩
部は円曲なテーパ面5となっている。6は電子部品であ
り、ファインピッチのリード7が側方に多数本延出して
いる。
An electrically insulating partition wall portion 4 is formed between the solder electrode portions 2. The partition 4 is formed by screen printing means or the like. As shown in FIG. 2, the partition wall portion 4 is taller than the solder electrode portion 2 and both shoulder portions are curved tapered surfaces 5. Reference numeral 6 denotes an electronic component, and a large number of fine pitch leads 7 extend laterally.

第3図に示すように、この電子部品6は、移載ヘッド
8のノズル9に吸着され、基板1に搭載される。10は仮
止用のボンドである。この場合、半田電極部2の上面は
球面状であるから、リード7は側方へ滑り落ちようとす
るが、この滑り落ちは、仕切壁部4により阻止され、リ
ード7は半田電極部2上に正しく搭載される。また第2
図鎖線にて示すように、リード7が半田電極部2に対し
て位置ずれしている場合には、リード7は仕切壁部4の
テーパ面5に案内されて、半田電極部2上に正しく着地
する。
As shown in FIG. 3, the electronic component 6 is sucked by the nozzle 9 of the transfer head 8 and mounted on the substrate 1. 10 is a bond for temporary fixing. In this case, since the upper surface of the solder electrode portion 2 is spherical, the lead 7 tends to slide down sideways, but this sliding down is prevented by the partition wall portion 4 and the lead 7 is placed on the solder electrode portion 2. Is mounted correctly. Also the second
As shown by the chain line, when the lead 7 is displaced from the solder electrode portion 2, the lead 7 is guided by the tapered surface 5 of the partition wall portion 4, and is correctly positioned on the solder electrode portion 2. Land.

このようにして電子部品6が搭載された基板1は、続
いて加熱処理され、半田電極部2は溶融して、リード7
は半田電極部2に固着される。
The substrate 1 on which the electronic component 6 is mounted in this manner is subsequently subjected to a heat treatment, and the solder electrode portion 2 is melted to form the lead 7
Are fixed to the solder electrode portion 2.

(発明の効果) 以上説明したように本発明は、基板にピッチをおいて
形成された固形の半田電極部の間に、この半田電極部よ
りも背高で両肩部が円曲なテーパ面の仕切壁部を形成
し、この半田電極部に電子部品のリード部を着地させて
ボンディングするようにしているので、電子部品のリー
ドが半田電極部から滑り落ちないようにしてリードを半
田電極部に正しく搭載してボンディングすることができ
る。
(Effects of the Invention) As described above, according to the present invention, between the solid solder electrode portions formed at a pitch on the substrate, the tapered surface which is higher than the solder electrode portion and both shoulder portions are curved. Is formed, and the lead of the electronic component is landed on the solder electrode portion for bonding, so that the lead of the electronic component does not slip off from the solder electrode portion, and the lead is connected to the solder electrode portion. Can be mounted and bonded correctly.

【図面の簡単な説明】[Brief description of the drawings]

図は本発明の実施例を示すものであって、第1図は電子
部品を搭載中の斜視図、第2図は部分断面図、第3図は
正面図、第4図は従来手段による搭載中の斜視図であ
る。 1……基板 2……半田電極部 4……仕切壁部 6……電子部品 7……リード
FIG. 1 shows an embodiment of the present invention. FIG. 1 is a perspective view showing an electronic component being mounted, FIG. 2 is a partial sectional view, FIG. 3 is a front view, and FIG. It is a perspective view inside. DESCRIPTION OF SYMBOLS 1 ... Board | substrate 2 ... Solder electrode part 4 ... Partition wall part 6 ... Electronic component 7 ... Lead

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】基板にピッチをおいて形成された固形の半
田電極部の間に、この半田電極部よりも背高で両肩部が
円曲なテーパ面の仕切壁部を形成し、この半田電極部に
電子部品のリード部を着地させてボンディングするよう
にしたことを特徴とする電子部品のボンディング方法。
1. A partition wall portion having a tapered surface which is taller than the solder electrode portion and both shoulder portions are curved between solid solder electrode portions formed at a pitch on the substrate. An electronic component bonding method, wherein a lead portion of an electronic component lands on a solder electrode portion to perform bonding.
JP2191375A 1990-07-19 1990-07-19 Electronic component bonding method Expired - Fee Related JP2924113B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2191375A JP2924113B2 (en) 1990-07-19 1990-07-19 Electronic component bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2191375A JP2924113B2 (en) 1990-07-19 1990-07-19 Electronic component bonding method

Publications (2)

Publication Number Publication Date
JPH0476987A JPH0476987A (en) 1992-03-11
JP2924113B2 true JP2924113B2 (en) 1999-07-26

Family

ID=16273547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2191375A Expired - Fee Related JP2924113B2 (en) 1990-07-19 1990-07-19 Electronic component bonding method

Country Status (1)

Country Link
JP (1) JP2924113B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3432571A1 (en) * 2017-07-19 2019-01-23 Fujikura Ltd. Imaging module and method of manufacturing the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0550777U (en) * 1991-12-12 1993-07-02 ケル株式会社 Printed circuit board for surface mounting

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59111068U (en) * 1983-01-19 1984-07-26 クラリオン株式会社 Printed board
JPS6219788U (en) * 1985-07-19 1987-02-05
JPS62197881U (en) * 1986-06-07 1987-12-16
JPS6473696A (en) * 1987-09-14 1989-03-17 Canon Kk Printed-circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3432571A1 (en) * 2017-07-19 2019-01-23 Fujikura Ltd. Imaging module and method of manufacturing the same
US20190021581A1 (en) * 2017-07-19 2019-01-24 Fujikura Ltd. Imaging module and method of manufacturing the same
US11337597B2 (en) * 2017-07-19 2022-05-24 Fujikura Ltd. Imaging module and method of manufacturing the same

Also Published As

Publication number Publication date
JPH0476987A (en) 1992-03-11

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