JP2917577B2 - Arithmetic unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit in a digital signal processor for performing Viterbi decoding of a convolutional code for error correction.

[0002]

2. Description of the Related Art In recent years, a digital signal processor (hereinafter abbreviated as DSP) has been receiving attention as a processor for use in incorporating a device into a portable telephone or the like in accordance with the trend of introduction of a digital system in the field of mobile communication. .
In a DSP for realizing such a voice coding apparatus for digital mobile communication, it is necessary to perform error correction processing in addition to calculations such as voice coding processing. Some error correction techniques use Viterbi decoding.

The Viterbi algorithm realizes maximum likelihood decoding of a convolutional code by repeating simple processing such as addition, comparison and selection. In this Viterbi decoding, every time encoded data (reception sequence) corresponding to one information bit is obtained, the metric of the surviving path in each state at that time is calculated and updated. FIG. 3 shows a state S2n (n is a positive integer) at a certain time point in a convolutional encoder having a constraint length k.
On the other hand, two paths representing the state transition from the state Sn and the state Sn + 2k-1 at the immediately preceding time point are extended. a and b are Hamming distances (branch metrics) between the output symbols of the path input to the state S2n and the reception sequence. In selecting a path, a total metric of each path is calculated by adding the above branch metric to the value of each metric of the surviving path at the immediately preceding time from a metric table of each branch calculated in advance. . The metric of the two paths input to the state S2n is compared, and a path having a small total Hamming distance is left.
Discard others. As described above, the decoding of the convolutional code by the Viterbi algorithm is the addition of the branch metric to the path metric for the input up to the immediately preceding point, comparison of the metric, and selection of the optimal path. It is necessary to perform the addition / comparison / selection operation and storage of the path metric for 2 ^k−1 states for each time series.

FIG. 2 shows a block diagram of a conventional arithmetic unit. In FIG. 2, reference numeral 1 denotes a metric (cumulative metric) of a path in each state in a command word of a processor or Viterbi decoding, and a branch metric taken by each path with respect to a value of encoded data (reception sequence) corresponding to one information bit. , A main storage unit that stores a selection result of a surviving path in each state, a bus 2 connected to the main storage unit 1 for supplying data, storing a calculation result, and the like, and 12 performing an arithmetic and logic operation. It is an arithmetic logic operation circuit. 10 is a latch circuit for temporarily storing the value of the left input of the logical operation circuit 12, 6 is a latch circuit for temporarily storing the value of the right input, and 18 and 19 are registers for temporarily storing the operation results.

[0005] In the arithmetic unit configured as described above, the operation of addition / comparison / selection operation of Viterbi decoding performed on one received sequence and the operation of storing the path selection signal will be described in the following six steps. .

(1) First Addition Step of Path Metric and Branch Metric The value of the path metric in the state Sn shown in FIG. 3 is stored in the latch circuit 10 from the main storage unit 1 via the bus 2,
Similarly, the value of the branch metric a is stored in the latch circuit 6 from the main storage unit 1 via the bus 2. The arithmetic and logic operation circuit 12 adds the contents of the latch circuits 10 and 6 and stores the result in the register 18.

(2) Second Addition Step of Path Metric and Branch Metric The value of the path metric in the state Sn + 2 ^k-1 shown in FIG. 3 is stored in the latch circuit 10 from the main storage unit 1 via the bus 2. Then, the value of the branch metric b is similarly stored in the latch circuit 6 from the main storage unit 1 via the bus 2. The arithmetic and logic operation circuit 12 adds the contents of the latch circuits 10 and 6 and stores the result in the register 19.

(3) Subtraction of two addition results (comparing large and small)
The contents of the step registers 18 and 19 are stored in the latch circuits 10 and 6, respectively. The arithmetic and logic operation circuit 12 includes the latch circuit 10
And 6 are subtracted. No result is stored.

(4) Step of judging (selecting) sign of operation result A control unit (not shown) judges the sign of the subtraction result of (3) and performs program control (branch) of the following steps (5) and (6). I do.

(5) Storing the addition result determined to be small (updating the path metric) Step If the subtraction result of (3) is negative according to the result of (4), the contents of the register 18 are stored in the main storage unit 1. To be stored. If the subtraction result of (3) is positive, the contents of the register 19 are stored in the main storage unit 1.

(6) Step of storing path selection signal If the result of (3) is negative according to the result of (4),
The value “0” is stored in the main storage unit 1. If the subtraction result of (3) is positive, the value “1” is stored in the main storage unit 1.

As described above, in the above-described conventional arithmetic device, the arithmetic and logic operation circuit performs addition and comparison in Viterbi decoding, and performs program control based on the comparison result, thereby performing Viterbi decoding processing.

[0013]

However, in the above-mentioned conventional arithmetic unit, the number of operation steps required for one addition / comparison / selection operation is large, and a large amount of memory is required because one bit of the path selection signal is stored in one word of the memory. There was a problem that required.

An object of the present invention is to solve such a conventional problem and to provide an excellent arithmetic unit capable of performing Viterbi decoding with a small number of operation steps and a small memory amount. is there.

[0015]

According to the present invention, in order to achieve the above object, at least storage means for storing a path metric and a branch metric in Viterbi decoding, and addition of the path metric and the branch metric read out from the storage means. Arithmetic logic operation means for performing , and at least one of a plurality of addition results output by the arithmetic logic operation means
Temporary storage means for temporarily storing one, and comparing means for comparing a plurality of addition results output by the arithmetic and logic operation means, and outputting a selection control signal indicating which addition result is smaller,
Selection means for selecting and outputting the addition result according to the selection control signal output by the comparison means.

[0016]

Therefore, according to the present invention, the comparator compares the result of the addition by the adder with the result of the addition temporarily stored in the first register, and compares the result of the addition determined to be small by the comparator with the result of the comparison. The arithmetic and logic circuit performs an arithmetic and logic operation on a result stored in the memory of the second memory and output by the shifter by shifting the constant output to the left by n bits to the storage destination data of the selection control signal. By storing the selection control signal output from the comparator in the n-th bit position of the storage destination data, the addition / comparison / selection operation of the cumulative metric of the surviving path in Viterbi decoding and the storage of the path selection signal can be performed with a small number of steps. This has the effect that it can be performed with a small amount of memory.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An arithmetic unit according to one embodiment of the present invention will be described below.
This will be described with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an arithmetic unit according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a first
The main storage unit 1 stores a command word of a processor, a metric (cumulative metric) of a path in each state in Viterbi decoding, and encoded data (received sequence) corresponding to one information bit. ), A table of branch metric values taken by each path for each value, a selection result of a surviving path in each state, and the like are stored.

Reference numeral 2 denotes a bus connected to the main storage unit 1 for supplying data, storing operation results, and the like, 3 denotes a constant circuit for outputting a constant in which the value of the least significant bit is 1 and all other bits are 0; Reference numeral 4 denotes a register for temporarily storing the number of shift bits output from an instruction decoding unit (not shown) of a processor connected to the bus 2 and outputting it to the bus 2 or the like. Reference numeral 5 denotes an output of the constant circuit 3 or the register 4 , A barrel shifter for shifting the shift bit number indicated by the register 4 or outputting without shifting, 6 a latch circuit for latching the output of the barrel shifter 5, 9 an exclusive OR gate, and an output of the latch circuit 6 Is an inverting circuit that inverts or non-inverts and outputs a latch circuit 10 that latches the data bus output.

An operation 7 outputs a control signal 8 for instructing the inversion circuit 9 to perform an inversion operation or not and a control signal 11 for instructing the logical operation circuit 12 to perform a logical sum or a logical product. A control unit 12 is an arithmetic and logic operation circuit as an arithmetic means for performing an arithmetic and logic operation by using the outputs of the latch circuit 10 and the inversion circuit 9 as inputs, 13 is a register for temporarily storing the output of the arithmetic and logic operation circuit 12, and 14 is a register 13 The comparator 16 compares the contents of the register 13 with the output of the arithmetic and logic operation circuit 12 and outputs a selection control signal 15 to the operation control unit 7 and the selector 16. A selector 17 selects the smaller one of the outputs of the circuit 12, and 17 is a register as a second memory member for storing the selector output.

With respect to the arithmetic unit configured as described above,
The operation will be described below. First, (Table 1) shows the selection control signal 15
And the operation contents of the inversion circuit 9 and the arithmetic and logic operation circuit 12 are shown.

[0022]

[Table 1]

The arithmetic control unit 7 controls the inverting circuit 9 and the logical operation circuit 12 according to the relationship shown in (Table 1). That is, when the selection control signal 15 is “0” (register 1
The inversion circuit 9 performs an inversion operation, while the arithmetic and logic operation circuit 12 obtains a logical product by an operation. On the other hand, when the selection control signal 15 is "1" (when the addition result is small), the inversion circuit 9 performs a non-inversion operation, while the arithmetic and logic operation circuit 12 obtains a logical sum by operation.

Referring to FIG. 3, the operation of addition / comparison / selection operation of Viterbi decoding performed for one state of the convolutional encoder and storage of the path selection signal will be described with reference to FIG. (2) a second addition and comparison selection step, and (3) a bit selection signal transfer step.

(1) First Addition Step of Path Metric and Branch Metric The value of the path metric in the state Sn shown in FIG. 3 is stored in the latch circuit 10 from the main storage unit 1 via the bus 2,
Similarly, the value of the branch metric a is stored in the latch circuit 6 from the main storage unit 1 via the bus 2. At this time, the barrel shifter 6 does not perform the shift operation. Arithmetic logic operation circuit 1
2 adds the contents of the latch circuits 10 and 6 and stores the result in the register 13. Further, the value of the path metric temporarily stored in the register 17 and updated by the addition / comparison / selection operation one cycle before is stored in the main storage unit 1.

(2) Step of Second Addition and Comparison Selection The value of the path metric in the state Sn + 2 ^k-1 shown in FIG. 3 is stored in the latch circuit 10 from the main storage unit 1 via the bus 2; Similarly, the value of the branch metric b is stored in the latch circuit 6 from the main storage unit 1 via the bus 2. At this time, the barrel shifter 6 does not perform the shift operation. The arithmetic and logic operation circuit 12 adds the contents of the latch circuits 10 and 6 and outputs the result to the comparator 14. The comparator 14 calculates the addition result and the register 13
And outputs a 1-bit selection control signal 15 of "0" to the selector 16 and the arithmetic control unit 7 when the value of the register 13 is small and "1" when the addition result is small. I do. When the selection control signal 15 is “0”, the selector 16 selects the value of the register 13, and when the selection control signal 15 is “1”, selects the output of the arithmetic logic operation circuit and stores it in the register 17.

(3) Step of Bit Transfer of Path Selection Signal First, a destination word for storing the path selection signal in the main storage unit 1 is latched by the latch circuit 10 via the bus 2. At the same time, the barrel shifter 5 shifts the constant (00000001) input from the constant circuit 3 to the left by the value n stored in the register 4 from the instruction decoding unit and outputs the same, and latches it in the latch circuit 6. Next, as shown in (Table 1), the inversion circuit 9 changes the contents of the latch circuit 6 to the selection control signal 15 input to the arithmetic control unit in the step (2).
Is "0", it is inverted, and if it is "1", it is output to the arithmetic and logic operation circuit 12 without being inverted. Arithmetic logic operation circuit 12
Indicates the logical operation of the destination word stored in the latch circuit 10 and the output of the inverting circuit 9, as shown in (Table 1), the logical product when the selection control signal 15 is “0”, and the logical operation of “1” In this case, a logical sum is calculated, output to the bus 2 and stored in the main storage unit 1. As a result, the path selection signal (selection control signal 15) can be stored in an arbitrary bit position of the main storage unit 1 in 1-bit units.

As described above, according to the present embodiment, the magnitude comparison between the addition result by the arithmetic and logic operation circuit 12 in the step (2) and the addition result temporarily stored in the register 13 in the step (1) is compared. The selector 16 selects and temporarily stores in the register 17 the addition result determined by the comparator 14 to be small, and the barrel shifter 5 shifts the constant output by the constant circuit 3 to the left by n bits and outputs it. The inversion circuit 9 and the arithmetic and logic operation circuit 12 perform a logical operation on the result and the storage data of the selection control signal in accordance with the control rules shown in (Table 1), and the selection control signal 15 output from the comparator 14 is stored in the storage destination. By storing the data in bit units at the n-th bit position of the data, the addition / comparison / selection operation of the accumulated metric of the surviving path in Viterbi decoding and the storage of the path selection signal are performed. A small number of steps that half the example has the effect that can be performed in smaller amount of memory.

The barrel shifter 5 shifts a constant in which only the least significant bit output from the constant circuit 3 is 1 and all the other bits are 0, so that the bits necessary for updating the bit of the storage destination data of the path selection signal are changed. Pattern data can be generated. Instead of holding bit pattern data (16 bits for a data width of 16 bits) in a processor instruction word, the number of shift bits (data width) corresponding to the bit position of the bit transfer destination 4 for 16 bits
Bit) only, the Viterbi decoding process can be performed with an instruction word having a short word length. Further, the barrel shifter 5, the inverting circuit 9, the arithmetic and logic operation circuit 12 and the like, which are the components of the present embodiment, are usually installed in a digital signal processor or the like in advance for numerical operation, so that a slight hardware There is also an effect that an arithmetic unit can be realized only by adding hardware.

In the embodiment, the value of the constant circuit 3 is set such that only the least significant bit is 1 and the other bits are 0. However, only the most significant bit is set to 1 and the value is shifted to the right by the barrel shifter 5, Bit only 0, other bits 1
Alternatively, the control of inversion and non-inversion of the inversion circuit 9 in (Table 1) may be reversed.

[0031]

According to the present invention, as is apparent from the above embodiment, the comparator compares the addition result by the arithmetic means with the addition result temporarily stored in the first register in advance, and the comparator compares the addition result with the addition result. The addition result determined by the second memory is stored in the second memory, and the arithmetic means performs an arithmetic and logic operation on the result of shifting and outputting the constant output by the constant output means and the storage data of the selection control signal. Since the selection control signal output by the comparator is stored at a predetermined bit position of the storage destination data, the addition and selection of the cumulative metric of the surviving path in Viterbi decoding and the storage of the path selection signal can be performed with a small number of steps. There is an effect that the operation can be performed with a smaller memory amount.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an arithmetic unit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a conventional arithmetic unit.

FIG. 3 is a diagram showing a state transition path of a convolutional encoder in Viterbi decoding for explaining the operation of an arithmetic unit;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main storage part (1st memory member) 2 Bus 3 Constant circuit 4 Register 5 Barrel shifter 6 Latch circuit 7 Operation control part 8 Control signal 9 Inverting circuit 10 Latch circuit 11 Control signal 12 Arithmetic logic operation circuit (Operation means) 13 Register 14 comparator 15 selection control signal 16 selector 17 register (second memory member)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03M 13/00 G06F 11/10 310 G06F 17/10 H04L 25/08

Claims (2)

(57) [Claims] Storage means for storing path metrics and branch metrics in claim 1 wherein at least Viterbi decoding, and arithmetic logic means for adding the path metric and the branch metric read out from the storage means, the arithmetic Theory
At least one of the plurality of addition results output by the logical operation means.
Temporary storage means for temporarily storing one of them, comparison means for comparing a plurality of addition results outputted by the arithmetic and logic operation means and outputting a selection control signal indicating which addition result is smaller, Selecting means for selecting and outputting an addition result according to a selection control signal to be output. 2. A constant output means for outputting a predetermined constant, a shifter for shifting an output of the constant output means, and a shift bit number output means for outputting a shift bit number necessary for a shift operation of the shifter. , the selection control signal from the arithmetic logic <br/> calculating means said comparing means in addition to the sum, logical product of the data stored in the <br/> storage means output or the inverted result of the shifter 2. The arithmetic unit according to claim 1, wherein a logical sum is performed, and the selection control signal output from the comparing unit is stored in an arbitrary bit position of the storage unit in units of one bit.